Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	347682646	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347682646	0	0
T1	9743160	235224	0	0
T2	7951720	246249	0	0
T3	68096	2533	0	0
T4	6697376	182285	0	0
T17	37076200	577382	0	0
T18	13273624	1860198	0	0
T19	1868944	38831	0	0
T20	1240960	55255	0	0
T21	0	42787	0	0
T22	5236840	75724	0	0
T23	56560	1504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9743160	9739520	0	0
T2	7951720	7947688	0	0
T3	68096	66528	0	0
T4	6697376	6693512	0	0
T17	37076200	37073064	0	0
T18	13273624	13273456	0	0
T19	1868944	1866032	0	0
T20	1240960	1240064	0	0
T22	5236840	5233200	0	0
T23	56560	53760	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9743160	9739520	0	0
T2	7951720	7947688	0	0
T3	68096	66528	0	0
T4	6697376	6693512	0	0
T17	37076200	37073064	0	0
T18	13273624	13273456	0	0
T19	1868944	1866032	0	0
T20	1240960	1240064	0	0
T22	5236840	5233200	0	0
T23	56560	53760	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9743160	9739520	0	0
T2	7951720	7947688	0	0
T3	68096	66528	0	0
T4	6697376	6693512	0	0
T17	37076200	37073064	0	0
T18	13273624	13273456	0	0
T19	1868944	1866032	0	0
T20	1240960	1240064	0	0
T22	5236840	5233200	0	0
T23	56560	53760	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	127950975	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	127950975	0	0
T1	173985	99097	0	0
T2	141995	139340	0	0
T3	1216	988	0	0
T4	119596	115881	0	0
T17	662075	3695	0	0
T18	237029	134415	0	0
T19	33374	14195	0	0
T20	22160	21862	0	0
T22	93515	18935	0	0
T23	1010	588	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	90526816	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	90526816	0	0
T1	173985	44079	0	0
T2	141995	53120	0	0
T3	1216	515	0	0
T4	119596	32890	0	0
T17	662075	285156	0	0
T18	237029	554439	0	0
T19	33374	13124	0	0
T20	22160	12355	0	0
T22	93515	18934	0	0
T23	1010	306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1457449	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1457449	0	0
T1	173985	2401	0	0
T2	141995	20	0	0
T3	1216	19	0	0
T4	119596	1	0	0
T17	662075	0	0	0
T18	237029	17541	0	0
T19	33374	137	0	0
T20	22160	151	0	0
T21	0	571	0	0
T22	93515	709	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3343264	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3343264	0	0
T1	173985	1497	0	0
T2	141995	1267	0	0
T3	1216	19	0	0
T4	119596	1	0	0
T17	662075	0	0	0
T18	237029	15234	0	0
T19	33374	184	0	0
T20	22160	151	0	0
T21	0	570	0	0
T22	93515	781	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1411310	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1411310	0	0
T1	173985	1214	0	0
T2	141995	6	0	0
T3	1216	23	0	0
T4	119596	20	0	0
T17	662075	0	0	0
T18	237029	28523	0	0
T19	33374	234	0	0
T20	22160	659	0	0
T21	0	1082	0	0
T22	93515	586	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	2866326	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	2866326	0	0
T1	173985	2432	0	0
T2	141995	739	0	0
T3	1216	23	0	0
T4	119596	104	0	0
T17	662075	0	0	0
T18	237029	23295	0	0
T19	33374	173	0	0
T20	22160	659	0	0
T21	0	1082	0	0
T22	93515	560	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1496209	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1496209	0	0
T1	173985	1744	0	0
T2	141995	15	0	0
T3	1216	17	0	0
T4	119596	47	0	0
T17	662075	0	0	0
T18	237029	22954	0	0
T19	33374	196	0	0
T20	22160	352	0	0
T21	0	946	0	0
T22	93515	665	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3594747	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3594747	0	0
T1	173985	1424	0	0
T2	141995	1720	0	0
T3	1216	17	0	0
T4	119596	989	0	0
T17	662075	0	0	0
T18	237029	18185	0	0
T19	33374	161	0	0
T20	22160	352	0	0
T21	0	946	0	0
T22	93515	613	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1481636	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1481636	0	0
T1	173985	2434	0	0
T2	141995	31	0	0
T3	1216	10	0	0
T4	119596	17	0	0
T17	662075	0	0	0
T18	237029	25581	0	0
T19	33374	142	0	0
T20	22160	353	0	0
T21	0	996	0	0
T22	93515	682	0	0
T23	1010	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3043939	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3043939	0	0
T1	173985	3485	0	0
T2	141995	1274	0	0
T3	1216	10	0	0
T4	119596	1128	0	0
T17	662075	0	0	0
T18	237029	24274	0	0
T19	33374	177	0	0
T20	22160	353	0	0
T21	0	996	0	0
T22	93515	697	0	0
T23	1010	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1506778	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1506778	0	0
T1	173985	466	0	0
T2	141995	16	0	0
T3	1216	19	0	0
T4	119596	27	0	0
T17	662075	997	0	0
T18	237029	18026	0	0
T19	33374	166	0	0
T20	22160	151	0	0
T22	93515	703	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3175592	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3175592	0	0
T1	173985	608	0	0
T2	141995	1576	0	0
T3	1216	19	0	0
T4	119596	1765	0	0
T17	662075	84547	0	0
T18	237029	17741	0	0
T19	33374	155	0	0
T20	22160	151	0	0
T22	93515	724	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1498831	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1498831	0	0
T1	173985	979	0	0
T2	141995	27	0	0
T3	1216	22	0	0
T4	119596	31	0	0
T17	662075	0	0	0
T18	237029	21412	0	0
T19	33374	235	0	0
T20	22160	144	0	0
T21	0	275	0	0
T22	93515	773	0	0
T23	1010	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3496282	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3496282	0	0
T1	173985	1030	0	0
T2	141995	1759	0	0
T3	1216	22	0	0
T4	119596	1083	0	0
T17	662075	0	0	0
T18	237029	15438	0	0
T19	33374	260	0	0
T20	22160	144	0	0
T21	0	275	0	0
T22	93515	749	0	0
T23	1010	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1466341	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1466341	0	0
T1	173985	3403	0	0
T2	141995	26	0	0
T3	1216	24	0	0
T4	119596	37	0	0
T17	662075	0	0	0
T18	237029	26687	0	0
T19	33374	297	0	0
T20	22160	931	0	0
T21	0	1271	0	0
T22	93515	844	0	0
T23	1010	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3534026	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3534026	0	0
T1	173985	2943	0	0
T2	141995	2870	0	0
T3	1216	24	0	0
T4	119596	1120	0	0
T17	662075	0	0	0
T18	237029	22530	0	0
T19	33374	317	0	0
T20	22160	931	0	0
T21	0	1271	0	0
T22	93515	740	0	0
T23	1010	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1488167	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1488167	0	0
T1	173985	2111	0	0
T2	141995	19	0	0
T3	1216	19	0	0
T4	119596	20	0	0
T17	662075	0	0	0
T18	237029	19141	0	0
T19	33374	189	0	0
T20	22160	413	0	0
T21	0	1012	0	0
T22	93515	669	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	2843844	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	2843844	0	0
T1	173985	2659	0	0
T2	141995	1455	0	0
T3	1216	19	0	0
T4	119596	1473	0	0
T17	662075	0	0	0
T18	237029	20413	0	0
T19	33374	188	0	0
T20	22160	413	0	0
T21	0	1012	0	0
T22	93515	671	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1465433	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1465433	0	0
T1	173985	1639	0	0
T2	141995	11	0	0
T3	1216	22	0	0
T4	119596	18	0	0
T17	662075	0	0	0
T18	237029	21257	0	0
T19	33374	207	0	0
T20	22160	347	0	0
T21	0	851	0	0
T22	93515	784	0	0
T23	1010	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	2769300	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	2769300	0	0
T1	173985	1824	0	0
T2	141995	1473	0	0
T3	1216	22	0	0
T4	119596	1089	0	0
T17	662075	0	0	0
T18	237029	18543	0	0
T19	33374	197	0	0
T20	22160	347	0	0
T21	0	851	0	0
T22	93515	787	0	0
T23	1010	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1439392	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1439392	0	0
T1	173985	1643	0	0
T2	141995	22	0	0
T3	1216	16	0	0
T4	119596	16	0	0
T17	662075	0	0	0
T18	237029	27019	0	0
T19	33374	115	0	0
T20	22160	334	0	0
T21	0	495	0	0
T22	93515	796	0	0
T23	1010	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3581502	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3581502	0	0
T1	173985	2078	0	0
T2	141995	952	0	0
T3	1216	16	0	0
T4	119596	1113	0	0
T17	662075	0	0	0
T18	237029	25701	0	0
T19	33374	134	0	0
T20	22160	334	0	0
T21	0	495	0	0
T22	93515	771	0	0
T23	1010	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1511281	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1511281	0	0
T1	173985	1090	0	0
T2	141995	2	0	0
T3	1216	12	0	0
T4	119596	30	0	0
T17	662075	0	0	0
T18	237029	21730	0	0
T19	33374	188	0	0
T20	22160	137	0	0
T21	0	521	0	0
T22	93515	624	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3397918	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3397918	0	0
T1	173985	2362	0	0
T2	141995	115	0	0
T3	1216	12	0	0
T4	119596	1081	0	0
T17	662075	0	0	0
T18	237029	25912	0	0
T19	33374	199	0	0
T20	22160	137	0	0
T21	0	521	0	0
T22	93515	636	0	0
T23	1010	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1523147	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1523147	0	0
T1	173985	2154	0	0
T2	141995	47	0	0
T3	1216	17	0	0
T4	119596	20	0	0
T17	662075	0	0	0
T18	237029	24312	0	0
T19	33374	227	0	0
T20	22160	144	0	0
T21	0	524	0	0
T22	93515	725	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3586985	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3586985	0	0
T1	173985	1550	0	0
T2	141995	3216	0	0
T3	1216	17	0	0
T4	119596	1142	0	0
T17	662075	0	0	0
T18	237029	24016	0	0
T19	33374	284	0	0
T20	22160	144	0	0
T21	0	524	0	0
T22	93515	752	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1432053	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1432053	0	0
T1	173985	1879	0	0
T2	141995	25	0	0
T3	1216	22	0	0
T4	119596	5	0	0
T17	662075	0	0	0
T18	237029	20990	0	0
T19	33374	181	0	0
T20	22160	1232	0	0
T21	0	562	0	0
T22	93515	844	0	0
T23	1010	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3290697	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3290697	0	0
T1	173985	215	0	0
T2	141995	1125	0	0
T3	1216	22	0	0
T4	119596	202	0	0
T17	662075	0	0	0
T18	237029	22340	0	0
T19	33374	167	0	0
T20	22160	1232	0	0
T21	0	562	0	0
T22	93515	761	0	0
T23	1010	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1463620	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1463620	0	0
T1	173985	1654	0	0
T2	141995	25	0	0
T3	1216	21	0	0
T4	119596	34	0	0
T17	662075	0	0	0
T18	237029	22359	0	0
T19	33374	124	0	0
T20	22160	647	0	0
T21	0	548	0	0
T22	93515	658	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3534850	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3534850	0	0
T1	173985	1273	0	0
T2	141995	1788	0	0
T3	1216	21	0	0
T4	119596	1966	0	0
T17	662075	0	0	0
T18	237029	15505	0	0
T19	33374	143	0	0
T20	22160	647	0	0
T21	0	548	0	0
T22	93515	562	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1472338	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1472338	0	0
T1	173985	1662	0	0
T2	141995	25	0	0
T3	1216	18	0	0
T4	119596	12	0	0
T17	662075	0	0	0
T18	237029	21589	0	0
T19	33374	319	0	0
T20	22160	651	0	0
T21	0	713	0	0
T22	93515	947	0	0
T23	1010	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3631969	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3631969	0	0
T1	173985	904	0	0
T2	141995	1992	0	0
T3	1216	18	0	0
T4	119596	1007	0	0
T17	662075	0	0	0
T18	237029	17008	0	0
T19	33374	397	0	0
T20	22160	651	0	0
T21	0	713	0	0
T22	93515	943	0	0
T23	1010	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1423846	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1423846	0	0
T1	173985	4042	0	0
T2	141995	6	0	0
T3	1216	17	0	0
T4	119596	36	0	0
T17	662075	0	0	0
T18	237029	28563	0	0
T19	33374	206	0	0
T20	22160	123	0	0
T21	0	2172	0	0
T22	93515	640	0	0
T23	1010	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	2983366	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	2983366	0	0
T1	173985	2388	0	0
T2	141995	777	0	0
T3	1216	17	0	0
T4	119596	1409	0	0
T17	662075	0	0	0
T18	237029	24131	0	0
T19	33374	223	0	0
T20	22160	123	0	0
T21	0	2172	0	0
T22	93515	655	0	0
T23	1010	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1465705	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1465705	0	0
T1	173985	2272	0	0
T2	141995	37	0	0
T3	1216	29	0	0
T4	119596	25	0	0
T17	662075	0	0	0
T18	237029	22031	0	0
T19	33374	376	0	0
T20	22160	570	0	0
T21	0	789	0	0
T22	93515	626	0	0
T23	1010	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3239286	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3239286	0	0
T1	173985	2814	0	0
T2	141995	3705	0	0
T3	1216	29	0	0
T4	119596	166	0	0
T17	662075	0	0	0
T18	237029	20466	0	0
T19	33374	255	0	0
T20	22160	570	0	0
T21	0	789	0	0
T22	93515	624	0	0
T23	1010	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1478396	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1478396	0	0
T1	173985	1736	0	0
T2	141995	27	0	0
T3	1216	8	0	0
T4	119596	22	0	0
T17	662075	0	0	0
T18	237029	20703	0	0
T19	33374	348	0	0
T20	22160	156	0	0
T21	0	988	0	0
T22	93515	601	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3566824	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3566824	0	0
T1	173985	2409	0	0
T2	141995	2398	0	0
T3	1216	8	0	0
T4	119596	1985	0	0
T17	662075	0	0	0
T18	237029	19872	0	0
T19	33374	272	0	0
T20	22160	156	0	0
T21	0	988	0	0
T22	93515	674	0	0
T23	1010	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1397028	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1397028	0	0
T1	173985	1040	0	0
T2	141995	39	0	0
T3	1216	24	0	0
T4	119596	42	0	0
T17	662075	0	0	0
T18	237029	22823	0	0
T19	33374	231	0	0
T20	22160	434	0	0
T21	0	1228	0	0
T22	93515	651	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3033310	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3033310	0	0
T1	173985	1291	0	0
T2	141995	1340	0	0
T3	1216	24	0	0
T4	119596	2142	0	0
T17	662075	0	0	0
T18	237029	18209	0	0
T19	33374	227	0	0
T20	22160	434	0	0
T21	0	1228	0	0
T22	93515	650	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1497604	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1497604	0	0
T1	173985	2136	0	0
T2	141995	26	0	0
T3	1216	17	0	0
T4	119596	12	0	0
T17	662075	1295	0	0
T18	237029	24070	0	0
T19	33374	207	0	0
T20	22160	401	0	0
T22	93515	707	0	0
T23	1010	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3112802	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3112802	0	0
T1	173985	1348	0	0
T2	141995	2282	0	0
T3	1216	17	0	0
T4	119596	2218	0	0
T17	662075	105324	0	0
T18	237029	17229	0	0
T19	33374	208	0	0
T20	22160	401	0	0
T22	93515	731	0	0
T23	1010	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1504608	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1504608	0	0
T1	173985	1643	0	0
T2	141995	38	0	0
T3	1216	15	0	0
T4	119596	7	0	0
T17	662075	1243	0	0
T18	237029	29317	0	0
T19	33374	161	0	0
T20	22160	408	0	0
T22	93515	567	0	0
T23	1010	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3446091	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3446091	0	0
T1	173985	1324	0	0
T2	141995	2794	0	0
T3	1216	15	0	0
T4	119596	401	0	0
T17	662075	95125	0	0
T18	237029	29220	0	0
T19	33374	200	0	0
T20	22160	408	0	0
T22	93515	648	0	0
T23	1010	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1445223	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1445223	0	0
T1	173985	1604	0	0
T2	141995	25	0	0
T3	1216	18	0	0
T4	119596	7	0	0
T17	662075	0	0	0
T18	237029	20010	0	0
T19	33374	164	0	0
T20	22160	371	0	0
T21	0	971	0	0
T22	93515	658	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3890320	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3890320	0	0
T1	173985	1665	0	0
T2	141995	639	0	0
T3	1216	18	0	0
T4	119596	350	0	0
T17	662075	0	0	0
T18	237029	21678	0	0
T19	33374	161	0	0
T20	22160	371	0	0
T21	0	971	0	0
T22	93515	715	0	0
T23	1010	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1429207	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1429207	0	0
T1	173985	1186	0	0
T2	141995	15	0	0
T3	1216	29	0	0
T4	119596	55	0	0
T17	662075	0	0	0
T18	237029	20395	0	0
T19	33374	227	0	0
T20	22160	392	0	0
T21	0	1099	0	0
T22	93515	710	0	0
T23	1010	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3320978	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3320978	0	0
T1	173985	626	0	0
T2	141995	1853	0	0
T3	1216	29	0	0
T4	119596	2739	0	0
T17	662075	0	0	0
T18	237029	16752	0	0
T19	33374	225	0	0
T20	22160	392	0	0
T21	0	1099	0	0
T22	93515	795	0	0
T23	1010	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1510543	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1510543	0	0
T1	173985	2146	0	0
T2	141995	31	0	0
T3	1216	18	0	0
T4	119596	12	0	0
T17	662075	0	0	0
T18	237029	20663	0	0
T19	33374	230	0	0
T20	22160	412	0	0
T21	0	856	0	0
T22	93515	873	0	0
T23	1010	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3031036	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3031036	0	0
T1	173985	1760	0	0
T2	141995	2870	0	0
T3	1216	18	0	0
T4	119596	954	0	0
T17	662075	0	0	0
T18	237029	18109	0	0
T19	33374	193	0	0
T20	22160	412	0	0
T21	0	856	0	0
T22	93515	842	0	0
T23	1010	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1466907	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1466907	0	0
T1	173985	1442	0	0
T2	141995	26	0	0
T3	1216	27	0	0
T4	119596	45	0	0
T17	662075	0	0	0
T18	237029	20498	0	0
T19	33374	167	0	0
T20	22160	149	0	0
T21	0	554	0	0
T22	93515	765	0	0
T23	1010	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3539659	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3539659	0	0
T1	173985	1504	0	0
T2	141995	3629	0	0
T3	1216	27	0	0
T4	119596	3130	0	0
T17	662075	0	0	0
T18	237029	19542	0	0
T19	33374	175	0	0
T20	22160	149	0	0
T21	0	554	0	0
T22	93515	795	0	0
T23	1010	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1489325	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1489325	0	0
T1	173985	1629	0	0
T2	141995	39	0	0
T3	1216	16	0	0
T4	119596	9	0	0
T17	662075	0	0	0
T18	237029	23067	0	0
T19	33374	320	0	0
T20	22160	344	0	0
T21	0	1541	0	0
T22	93515	616	0	0
T23	1010	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3172321	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3172321	0	0
T1	173985	648	0	0
T2	141995	3747	0	0
T3	1216	16	0	0
T4	119596	1464	0	0
T17	662075	0	0	0
T18	237029	20268	0	0
T19	33374	241	0	0
T20	22160	344	0	0
T21	0	1541	0	0
T22	93515	547	0	0
T23	1010	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	1466294	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	1466294	0	0
T1	173985	620	0	0
T2	141995	43	0	0
T3	1216	16	0	0
T4	119596	17	0	0
T17	662075	0	0	0
T18	237029	26342	0	0
T19	33374	195	0	0
T20	22160	113	0	0
T21	0	829	0	0
T22	93515	505	0	0
T23	1010	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313475666	3488950	0	0
DepthKnown_A	313475666	313363193	0	0
RvalidKnown_A	313475666	313363193	0	0
WreadyKnown_A	313475666	313363193	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	3488950	0	0
T1	173985	18	0	0
T2	141995	3765	0	0
T3	1216	16	0	0
T4	119596	669	0	0
T17	662075	0	0	0
T18	237029	22130	0	0
T19	33374	207	0	0
T20	22160	113	0	0
T21	0	829	0	0
T22	93515	504	0	0
T23	1010	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313475666	313363193	0	0
T1	173985	173920	0	0
T2	141995	141923	0	0
T3	1216	1188	0	0
T4	119596	119527	0	0
T17	662075	662019	0	0
T18	237029	237026	0	0
T19	33374	33322	0	0
T20	22160	22144	0	0
T22	93515	93450	0	0
T23	1010	960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0