Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1689820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265964

1

T1

12

T2

23

T3

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	662152	1			T1	29		T2	36		T3	388
values[0x0]	632222	1			T1	32		T2	42		T3	360
values[0x1]	661410	1			T1	33		T2	41		T3	358

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1309832	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

645952

1

T1

30

T2

43

T3

361

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7458	1			T3	4		T16	13		T17	3
valid_sources[0x01]	6670	1			T3	3		T16	11		T17	4
valid_sources[0x02]	6699	1			T16	2		T17	2		T21	21
valid_sources[0x03]	7276	1			T3	7		T15	29		T16	10
valid_sources[0x04]	8487	1			T2	1		T4	3		T16	7
valid_sources[0x05]	9016	1			T16	11		T17	8		T20	20
valid_sources[0x06]	7106	1			T3	7		T16	10		T17	3
valid_sources[0x07]	7882	1			T1	21		T3	4		T4	1
valid_sources[0x08]	7226	1			T4	1		T16	2		T17	3
valid_sources[0x09]	7782	1			T3	7		T16	10		T17	3
valid_sources[0x0a]	7641	1			T2	1		T3	6		T4	1
valid_sources[0x0b]	8443	1			T3	8		T16	7		T21	12
valid_sources[0x0c]	9783	1			T3	6		T16	16		T17	3
valid_sources[0x0d]	6943	1			T16	9		T17	4		T18	1
valid_sources[0x0e]	7674	1			T16	2		T17	5		T21	332
valid_sources[0x0f]	7489	1			T3	11		T4	1		T16	16
valid_sources[0x10]	6866	1			T2	2		T3	8		T4	2
valid_sources[0x11]	7681	1			T4	1		T16	11		T17	2
valid_sources[0x12]	6894	1			T2	1		T3	16		T4	1
valid_sources[0x13]	7815	1			T2	1		T3	10		T16	13
valid_sources[0x14]	7445	1			T3	1		T16	11		T17	5
valid_sources[0x15]	8258	1			T3	2		T15	14		T16	9
valid_sources[0x16]	7193	1			T3	4		T16	1		T17	2
valid_sources[0x17]	7693	1			T3	12		T4	1		T16	17
valid_sources[0x18]	8210	1			T3	7		T4	1		T16	10
valid_sources[0x19]	7889	1			T2	1		T3	1		T16	2
valid_sources[0x1a]	6917	1			T2	2		T3	1		T16	9
valid_sources[0x1b]	7452	1			T2	1		T3	4		T16	12
valid_sources[0x1c]	7726	1			T3	2		T4	5		T16	10
valid_sources[0x1d]	7884	1			T3	9		T16	9		T17	4
valid_sources[0x1e]	7419	1			T3	8		T16	16		T17	1
valid_sources[0x1f]	7330	1			T3	16		T16	16		T17	2
valid_sources[0x20]	6827	1			T3	4		T15	33		T16	13
valid_sources[0x21]	6974	1			T3	11		T4	1		T16	10
valid_sources[0x22]	6754	1			T3	2		T16	9		T17	5
valid_sources[0x23]	8723	1			T3	17		T16	6		T18	1
valid_sources[0x24]	8523	1			T2	1		T3	7		T4	1
valid_sources[0x25]	7544	1			T3	8		T4	1		T16	9
valid_sources[0x26]	8187	1			T2	3		T16	7		T17	5
valid_sources[0x27]	8489	1			T1	6		T4	1		T16	13
valid_sources[0x28]	6758	1			T16	6		T21	36		T22	39
valid_sources[0x29]	6369	1			T2	1		T4	3		T16	8
valid_sources[0x2a]	7351	1			T15	25		T16	9		T17	1
valid_sources[0x2b]	7275	1			T16	4		T17	1		T18	1
valid_sources[0x2c]	7239	1			T2	3		T4	1		T16	17
valid_sources[0x2d]	7632	1			T3	2		T4	1		T16	6
valid_sources[0x2e]	7805	1			T3	11		T16	9		T17	2
valid_sources[0x2f]	9667	1			T2	4		T3	6		T4	1
valid_sources[0x30]	6391	1			T2	1		T4	1		T16	15
valid_sources[0x31]	10598	1			T16	16		T17	2		T21	504
valid_sources[0x32]	9565	1			T2	4		T16	10		T17	7
valid_sources[0x33]	9445	1			T3	2		T16	14		T21	50
valid_sources[0x34]	9479	1			T3	1		T4	2		T16	11
valid_sources[0x35]	6869	1			T2	1		T3	3		T4	1
valid_sources[0x36]	6608	1			T2	1		T3	1		T4	1
valid_sources[0x37]	7442	1			T3	8		T15	7		T16	7
valid_sources[0x38]	7559	1			T3	5		T16	13		T17	1
valid_sources[0x39]	7597	1			T3	5		T16	12		T17	1
valid_sources[0x3a]	7676	1			T3	1		T4	1		T16	10
valid_sources[0x3b]	8483	1			T3	4		T15	15		T16	8
valid_sources[0x3c]	8268	1			T2	2		T3	5		T16	12
valid_sources[0x3d]	6946	1			T16	5		T18	1		T21	36
valid_sources[0x3e]	7306	1			T16	8		T21	4		T22	36
valid_sources[0x3f]	7445	1			T2	1		T3	2		T16	8
valid_sources[0x40]	8001	1			T16	13		T17	4		T19	19
valid_sources[0x41]	8582	1			T4	1		T16	13		T21	120
valid_sources[0x42]	8870	1			T3	2		T16	8		T17	9
valid_sources[0x43]	8003	1			T3	8		T4	2		T15	7
valid_sources[0x44]	7470	1			T3	7		T16	6		T17	4
valid_sources[0x45]	7218	1			T3	1		T16	8		T17	4
valid_sources[0x46]	7707	1			T16	9		T17	2		T22	39
valid_sources[0x47]	7300	1			T3	1		T4	2		T16	15
valid_sources[0x48]	7539	1			T3	2		T4	1		T16	10
valid_sources[0x49]	9162	1			T3	8		T16	10		T17	2
valid_sources[0x4a]	7927	1			T16	12		T17	6		T18	5
valid_sources[0x4b]	6728	1			T3	5		T4	4		T16	11
valid_sources[0x4c]	7037	1			T16	18		T17	7		T21	167
valid_sources[0x4d]	7602	1			T2	1		T3	5		T4	1
valid_sources[0x4e]	7342	1			T4	1		T16	17		T17	6
valid_sources[0x4f]	10557	1			T3	8		T16	9		T17	1
valid_sources[0x50]	6892	1			T16	7		T17	5		T18	2
valid_sources[0x51]	7768	1			T3	3		T4	1		T16	5
valid_sources[0x52]	7668	1			T16	10		T20	1		T21	12
valid_sources[0x53]	7530	1			T3	2		T4	1		T16	14
valid_sources[0x54]	8225	1			T3	10		T16	12		T17	3
valid_sources[0x55]	6622	1			T3	2		T4	1		T16	9
valid_sources[0x56]	7232	1			T3	4		T16	5		T17	3
valid_sources[0x57]	7848	1			T4	1		T16	9		T17	3
valid_sources[0x58]	6844	1			T2	3		T3	10		T16	16
valid_sources[0x59]	7625	1			T3	1		T16	8		T17	10
valid_sources[0x5a]	8389	1			T4	1		T16	16		T17	11
valid_sources[0x5b]	7403	1			T3	2		T4	2		T16	11
valid_sources[0x5c]	7954	1			T3	1		T16	11		T17	2
valid_sources[0x5d]	8146	1			T3	5		T16	7		T17	1
valid_sources[0x5e]	7853	1			T3	9		T16	11		T19	5
valid_sources[0x5f]	8308	1			T16	15		T17	1		T20	11
valid_sources[0x60]	8034	1			T3	5		T16	13		T17	3
valid_sources[0x61]	7871	1			T2	5		T4	2		T16	9
valid_sources[0x62]	7093	1			T3	6		T4	1		T16	17
valid_sources[0x63]	7251	1			T3	3		T4	1		T16	5
valid_sources[0x64]	7112	1			T3	15		T4	1		T15	19
valid_sources[0x65]	8195	1			T2	4		T16	13		T17	5
valid_sources[0x66]	7873	1			T4	1		T16	16		T17	3
valid_sources[0x67]	8324	1			T3	7		T16	11		T17	2
valid_sources[0x68]	7001	1			T3	9		T16	15		T17	7
valid_sources[0x69]	7417	1			T3	2		T4	4		T16	13
valid_sources[0x6a]	7873	1			T16	15		T17	2		T21	10
valid_sources[0x6b]	8531	1			T3	2		T16	10		T17	1
valid_sources[0x6c]	7022	1			T15	18		T16	9		T17	13
valid_sources[0x6d]	7642	1			T1	45		T4	3		T16	6
valid_sources[0x6e]	7527	1			T3	5		T16	5		T17	1
valid_sources[0x6f]	7892	1			T3	11		T4	1		T16	8
valid_sources[0x70]	7233	1			T2	3		T3	1		T4	1
valid_sources[0x71]	6642	1			T3	1		T16	10		T17	2
valid_sources[0x72]	8076	1			T3	8		T16	10		T17	7
valid_sources[0x73]	7432	1			T3	5		T16	16		T17	2
valid_sources[0x74]	8855	1			T3	2		T16	9		T20	2
valid_sources[0x75]	7216	1			T3	11		T16	7		T17	6
valid_sources[0x76]	8931	1			T3	11		T4	1		T16	7
valid_sources[0x77]	7119	1			T3	5		T16	6		T17	18
valid_sources[0x78]	7974	1			T3	2		T16	9		T17	3
valid_sources[0x79]	7838	1			T3	10		T4	3		T16	10
valid_sources[0x7a]	7468	1			T2	1		T3	1		T4	1
valid_sources[0x7b]	7371	1			T2	1		T3	5		T16	8
valid_sources[0x7c]	7045	1			T2	1		T3	5		T16	9
valid_sources[0x7d]	8080	1			T3	1		T16	16		T17	2
valid_sources[0x7e]	8862	1			T3	4		T16	8		T19	30
valid_sources[0x7f]	7669	1			T3	3		T16	9		T17	4
valid_sources[0x80]	7917	1			T3	2		T4	1		T16	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28117

1

T1

2

T3

21

T4

5

values[0x0]

all_enables

biggest_size

209521

1

T1

9

T2

21

T3

122

values[0x1]

all_enables

biggest_size

28326

1

T1

1

T2

2

T3

21