Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	330161877	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	330161877	0	0
T1	157050	3678	0	0
T2	7999880	178913	0	0
T3	53637080	1734074	0	0
T4	3635856	75548	0	0
T15	634536	13698	0	0
T16	314272	10704	0	0
T17	30025800	703781	0	0
T18	2462208	35182	0	0
T19	1079344	15489	0	0
T20	154840	5751	0	0
T21	261217	5025	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	195440	178024	0	0
T2	7999880	7999264	0	0
T3	53637080	53635288	0	0
T4	3635856	3630816	0	0
T15	634536	630112	0	0
T16	314272	311696	0	0
T17	30025800	29902208	0	0
T18	2462208	2460472	0	0
T19	1079344	1077608	0	0
T20	154840	151536	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	195440	178024	0	0
T2	7999880	7999264	0	0
T3	53637080	53635288	0	0
T4	3635856	3630816	0	0
T15	634536	630112	0	0
T16	314272	311696	0	0
T17	30025800	29902208	0	0
T18	2462208	2460472	0	0
T19	1079344	1077608	0	0
T20	154840	151536	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	195440	178024	0	0
T2	7999880	7999264	0	0
T3	53637080	53635288	0	0
T4	3635856	3630816	0	0
T15	634536	630112	0	0
T16	314272	311696	0	0
T17	30025800	29902208	0	0
T18	2462208	2460472	0	0
T19	1079344	1077608	0	0
T20	154840	151536	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	117279905	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	117279905	0	0
T1	3490	1456	0	0
T2	142855	77009	0	0
T3	957805	944546	0	0
T4	64926	34829	0	0
T15	11331	5894	0	0
T16	5612	5288	0	0
T17	536175	256556	0	0
T18	43968	16014	0	0
T19	19274	3830	0	0
T20	2765	2241	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	86324681	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	86324681	0	0
T1	3490	710	0	0
T2	142855	30418	0	0
T3	957805	392698	0	0
T4	64926	9542	0	0
T15	11331	2507	0	0
T16	5612	2700	0	0
T17	536175	165585	0	0
T18	43968	5401	0	0
T19	19274	3925	0	0
T20	2765	1170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1543363	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1543363	0	0
T1	3490	50	0	0
T2	142855	2167	0	0
T3	957805	183	0	0
T4	64926	584	0	0
T15	11331	150	0	0
T16	5612	47	0	0
T17	536175	6062	0	0
T18	43968	387	0	0
T19	19274	204	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2565110	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2565110	0	0
T1	3490	16	0	0
T2	142855	1214	0	0
T3	957805	15809	0	0
T4	64926	298	0	0
T15	11331	115	0	0
T16	5612	47	0	0
T17	536175	5823	0	0
T18	43968	144	0	0
T19	19274	203	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1488875	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1488875	0	0
T1	3490	4	0	0
T2	142855	1123	0	0
T3	957805	190	0	0
T4	64926	930	0	0
T15	11331	85	0	0
T16	5612	58	0	0
T17	536175	4413	0	0
T18	43968	350	0	0
T19	19274	86	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3358646	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3358646	0	0
T1	3490	3	0	0
T2	142855	2174	0	0
T3	957805	13993	0	0
T4	64926	367	0	0
T15	11331	115	0	0
T16	5612	58	0	0
T17	536175	4653	0	0
T18	43968	147	0	0
T19	19274	87	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1522765	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1522765	0	0
T1	3490	40	0	0
T2	142855	743	0	0
T3	957805	173	0	0
T4	64926	824	0	0
T15	11331	113	0	0
T16	5612	45	0	0
T17	536175	5670	0	0
T18	43968	364	0	0
T19	19274	108	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3270236	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3270236	0	0
T1	3490	19	0	0
T2	142855	294	0	0
T3	957805	13881	0	0
T4	64926	328	0	0
T15	11331	124	0	0
T16	5612	45	0	0
T17	536175	6008	0	0
T18	43968	122	0	0
T19	19274	90	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1490643	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1490643	0	0
T2	142855	1021	0	0
T3	957805	160	0	0
T4	64926	660	0	0
T15	11331	94	0	0
T16	5612	36	0	0
T17	536175	5937	0	0
T18	43968	414	0	0
T19	19274	171	0	0
T20	2765	43	0	0
T21	23747	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3143589	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3143589	0	0
T2	142855	949	0	0
T3	957805	12876	0	0
T4	64926	344	0	0
T15	11331	124	0	0
T16	5612	36	0	0
T17	536175	5790	0	0
T18	43968	171	0	0
T19	19274	158	0	0
T20	2765	43	0	0
T21	23747	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1520106	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1520106	0	0
T2	142855	1545	0	0
T3	957805	210	0	0
T4	64926	791	0	0
T15	11331	143	0	0
T16	5612	56	0	0
T17	536175	5881	0	0
T18	43968	365	0	0
T19	19274	158	0	0
T20	2765	48	0	0
T21	23747	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3284822	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3284822	0	0
T2	142855	285	0	0
T3	957805	15587	0	0
T4	64926	389	0	0
T15	11331	140	0	0
T16	5612	56	0	0
T17	536175	5725	0	0
T18	43968	131	0	0
T19	19274	143	0	0
T20	2765	48	0	0
T21	23747	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1496519	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1496519	0	0
T1	3490	15	0	0
T2	142855	820	0	0
T3	957805	168	0	0
T4	64926	783	0	0
T15	11331	110	0	0
T16	5612	54	0	0
T17	536175	6147	0	0
T18	43968	411	0	0
T19	19274	161	0	0
T20	2765	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2646671	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2646671	0	0
T1	3490	13	0	0
T2	142855	618	0	0
T3	957805	16132	0	0
T4	64926	260	0	0
T15	11331	129	0	0
T16	5612	54	0	0
T17	536175	6019	0	0
T18	43968	121	0	0
T19	19274	126	0	0
T20	2765	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1586264	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1586264	0	0
T1	3490	4	0	0
T2	142855	2075	0	0
T3	957805	169	0	0
T4	64926	811	0	0
T15	11331	132	0	0
T16	5612	49	0	0
T17	536175	10017	0	0
T18	43968	351	0	0
T19	19274	115	0	0
T20	2765	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3227818	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3227818	0	0
T1	3490	20	0	0
T2	142855	864	0	0
T3	957805	10550	0	0
T4	64926	438	0	0
T15	11331	82	0	0
T16	5612	49	0	0
T17	536175	10081	0	0
T18	43968	167	0	0
T19	19274	145	0	0
T20	2765	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1565563	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1565563	0	0
T1	3490	33	0	0
T2	142855	1672	0	0
T3	957805	156	0	0
T4	64926	815	0	0
T15	11331	85	0	0
T16	5612	50	0	0
T17	536175	4914	0	0
T18	43968	383	0	0
T19	19274	192	0	0
T20	2765	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3345604	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3345604	0	0
T1	3490	33	0	0
T2	142855	828	0	0
T3	957805	14110	0	0
T4	64926	330	0	0
T15	11331	79	0	0
T16	5612	50	0	0
T17	536175	5127	0	0
T18	43968	198	0	0
T19	19274	214	0	0
T20	2765	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1528139	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1528139	0	0
T2	142855	672	0	0
T3	957805	228	0	0
T4	64926	811	0	0
T15	11331	135	0	0
T16	5612	48	0	0
T17	536175	6571	0	0
T18	43968	391	0	0
T19	19274	135	0	0
T20	2765	61	0	0
T21	23747	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2548797	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2548797	0	0
T2	142855	87	0	0
T3	957805	15517	0	0
T4	64926	396	0	0
T15	11331	144	0	0
T16	5612	48	0	0
T17	536175	6361	0	0
T18	43968	161	0	0
T19	19274	132	0	0
T20	2765	61	0	0
T21	23747	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1570154	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1570154	0	0
T1	3490	182	0	0
T2	142855	542	0	0
T3	957805	141	0	0
T4	64926	704	0	0
T15	11331	41	0	0
T16	5612	38	0	0
T17	536175	2577	0	0
T18	43968	405	0	0
T19	19274	93	0	0
T20	2765	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3395116	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3395116	0	0
T1	3490	139	0	0
T2	142855	523	0	0
T3	957805	12920	0	0
T4	64926	318	0	0
T15	11331	48	0	0
T16	5612	38	0	0
T17	536175	2670	0	0
T18	43968	194	0	0
T19	19274	95	0	0
T20	2765	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1512338	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1512338	0	0
T2	142855	1407	0	0
T3	957805	170	0	0
T4	64926	873	0	0
T15	11331	77	0	0
T16	5612	46	0	0
T17	536175	3783	0	0
T18	43968	309	0	0
T19	19274	111	0	0
T20	2765	43	0	0
T21	23747	756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3584185	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3584185	0	0
T2	142855	1130	0	0
T3	957805	11780	0	0
T4	64926	412	0	0
T15	11331	86	0	0
T16	5612	46	0	0
T17	536175	3930	0	0
T18	43968	166	0	0
T19	19274	148	0	0
T20	2765	43	0	0
T21	23747	756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1486873	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1486873	0	0
T1	3490	16	0	0
T2	142855	763	0	0
T3	957805	158	0	0
T4	64926	847	0	0
T15	11331	79	0	0
T16	5612	60	0	0
T17	536175	4994	0	0
T18	43968	414	0	0
T19	19274	129	0	0
T20	2765	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2590058	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2590058	0	0
T1	3490	10	0	0
T2	142855	262	0	0
T3	957805	12432	0	0
T4	64926	387	0	0
T15	11331	48	0	0
T16	5612	60	0	0
T17	536175	5361	0	0
T18	43968	154	0	0
T19	19274	202	0	0
T20	2765	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1491127	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1491127	0	0
T1	3490	207	0	0
T2	142855	1367	0	0
T3	957805	234	0	0
T4	64926	773	0	0
T15	11331	113	0	0
T16	5612	49	0	0
T17	536175	4526	0	0
T18	43968	313	0	0
T19	19274	148	0	0
T20	2765	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3205657	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3205657	0	0
T1	3490	148	0	0
T2	142855	2977	0	0
T3	957805	15100	0	0
T4	64926	317	0	0
T15	11331	81	0	0
T16	5612	49	0	0
T17	536175	4239	0	0
T18	43968	129	0	0
T19	19274	194	0	0
T20	2765	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1522293	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1522293	0	0
T1	3490	12	0	0
T2	142855	3154	0	0
T3	957805	155	0	0
T4	64926	824	0	0
T15	11331	151	0	0
T16	5612	51	0	0
T17	536175	5154	0	0
T18	43968	283	0	0
T19	19274	169	0	0
T20	2765	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3291802	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3291802	0	0
T1	3490	7	0	0
T2	142855	1878	0	0
T3	957805	11610	0	0
T4	64926	353	0	0
T15	11331	119	0	0
T16	5612	51	0	0
T17	536175	5177	0	0
T18	43968	126	0	0
T19	19274	148	0	0
T20	2765	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1542202	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1542202	0	0
T1	3490	24	0	0
T2	142855	1280	0	0
T3	957805	166	0	0
T4	64926	722	0	0
T15	11331	89	0	0
T16	5612	56	0	0
T17	536175	5379	0	0
T18	43968	343	0	0
T19	19274	161	0	0
T20	2765	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3029600	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3029600	0	0
T1	3490	36	0	0
T2	142855	455	0	0
T3	957805	13357	0	0
T4	64926	381	0	0
T15	11331	88	0	0
T16	5612	56	0	0
T17	536175	5156	0	0
T18	43968	155	0	0
T19	19274	123	0	0
T20	2765	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1503474	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1503474	0	0
T1	3490	5	0	0
T2	142855	2635	0	0
T3	957805	161	0	0
T4	64926	742	0	0
T15	11331	154	0	0
T16	5612	47	0	0
T17	536175	1963	0	0
T18	43968	382	0	0
T19	19274	142	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3305991	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3305991	0	0
T1	3490	18	0	0
T2	142855	1914	0	0
T3	957805	13366	0	0
T4	64926	337	0	0
T15	11331	81	0	0
T16	5612	47	0	0
T17	536175	1938	0	0
T18	43968	147	0	0
T19	19274	112	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1495106	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1495106	0	0
T1	3490	12	0	0
T2	142855	2818	0	0
T3	957805	155	0	0
T4	64926	853	0	0
T15	11331	26	0	0
T16	5612	56	0	0
T17	536175	6237	0	0
T18	43968	348	0	0
T19	19274	128	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2976372	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2976372	0	0
T1	3490	24	0	0
T2	142855	2315	0	0
T3	957805	14269	0	0
T4	64926	317	0	0
T15	11331	52	0	0
T16	5612	56	0	0
T17	536175	5712	0	0
T18	43968	148	0	0
T19	19274	110	0	0
T20	2765	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1508322	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1508322	0	0
T1	3490	16	0	0
T2	142855	2072	0	0
T3	957805	171	0	0
T4	64926	1076	0	0
T15	11331	135	0	0
T16	5612	54	0	0
T17	536175	5128	0	0
T18	43968	389	0	0
T19	19274	195	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3018601	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3018601	0	0
T1	3490	20	0	0
T2	142855	1623	0	0
T3	957805	13582	0	0
T4	64926	394	0	0
T15	11331	80	0	0
T16	5612	54	0	0
T17	536175	5336	0	0
T18	43968	190	0	0
T19	19274	228	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1523233	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1523233	0	0
T1	3490	36	0	0
T2	142855	908	0	0
T3	957805	145	0	0
T4	64926	805	0	0
T15	11331	134	0	0
T16	5612	47	0	0
T17	536175	2619	0	0
T18	43968	323	0	0
T19	19274	169	0	0
T20	2765	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3644643	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3644643	0	0
T1	3490	25	0	0
T2	142855	1401	0	0
T3	957805	13580	0	0
T4	64926	268	0	0
T15	11331	66	0	0
T16	5612	47	0	0
T17	536175	2665	0	0
T18	43968	131	0	0
T19	19274	110	0	0
T20	2765	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1512961	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1512961	0	0
T1	3490	13	0	0
T2	142855	3475	0	0
T3	957805	182	0	0
T4	64926	836	0	0
T15	11331	93	0	0
T16	5612	50	0	0
T17	536175	3493	0	0
T18	43968	343	0	0
T19	19274	124	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3490865	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3490865	0	0
T1	3490	27	0	0
T2	142855	3056	0	0
T3	957805	20147	0	0
T4	64926	407	0	0
T15	11331	83	0	0
T16	5612	50	0	0
T17	536175	3566	0	0
T18	43968	154	0	0
T19	19274	122	0	0
T20	2765	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1530178	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1530178	0	0
T1	3490	12	0	0
T2	142855	342	0	0
T3	957805	187	0	0
T4	64926	761	0	0
T15	11331	56	0	0
T16	5612	76	0	0
T17	536175	6955	0	0
T18	43968	480	0	0
T19	19274	192	0	0
T20	2765	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3460094	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3460094	0	0
T2	142855	544	0	0
T3	957805	12721	0	0
T4	64926	303	0	0
T15	11331	56	0	0
T16	5612	76	0	0
T17	536175	6799	0	0
T18	43968	117	0	0
T19	19274	170	0	0
T20	2765	36	0	0
T21	23747	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1574946	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1574946	0	0
T2	142855	1135	0	0
T3	957805	218	0	0
T4	64926	768	0	0
T15	11331	146	0	0
T16	5612	50	0	0
T17	536175	3381	0	0
T18	43968	301	0	0
T19	19274	131	0	0
T20	2765	46	0	0
T21	23747	1014	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2981566	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2981566	0	0
T2	142855	820	0	0
T3	957805	16306	0	0
T4	64926	350	0	0
T15	11331	154	0	0
T16	5612	50	0	0
T17	536175	3627	0	0
T18	43968	156	0	0
T19	19274	117	0	0
T20	2765	46	0	0
T21	23747	1014	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1468647	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1468647	0	0
T1	3490	35	0	0
T2	142855	459	0	0
T3	957805	220	0	0
T4	64926	828	0	0
T15	11331	64	0	0
T16	5612	51	0	0
T17	536175	6385	0	0
T18	43968	244	0	0
T19	19274	120	0	0
T20	2765	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2818270	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2818270	0	0
T1	3490	77	0	0
T2	142855	892	0	0
T3	957805	19602	0	0
T4	64926	391	0	0
T15	11331	60	0	0
T16	5612	51	0	0
T17	536175	6491	0	0
T18	43968	154	0	0
T19	19274	150	0	0
T20	2765	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1490494	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1490494	0	0
T1	3490	46	0	0
T2	142855	2870	0	0
T3	957805	191	0	0
T4	64926	676	0	0
T15	11331	52	0	0
T16	5612	46	0	0
T17	536175	6143	0	0
T18	43968	282	0	0
T19	19274	112	0	0
T20	2765	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	2883472	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	2883472	0	0
T1	3490	40	0	0
T2	142855	709	0	0
T3	957805	16929	0	0
T4	64926	342	0	0
T15	11331	60	0	0
T16	5612	46	0	0
T17	536175	6152	0	0
T18	43968	147	0	0
T19	19274	111	0	0
T20	2765	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1530951	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1530951	0	0
T1	3490	7	0	0
T2	142855	1440	0	0
T3	957805	191	0	0
T4	64926	809	0	0
T15	11331	104	0	0
T16	5612	45	0	0
T17	536175	8815	0	0
T18	43968	330	0	0
T19	19274	173	0	0
T20	2765	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3730816	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3730816	0	0
T1	3490	9	0	0
T2	142855	290	0	0
T3	957805	16976	0	0
T4	64926	326	0	0
T15	11331	71	0	0
T16	5612	45	0	0
T17	536175	8933	0	0
T18	43968	150	0	0
T19	19274	212	0	0
T20	2765	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1585433	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1585433	0	0
T1	3490	32	0	0
T2	142855	1031	0	0
T3	957805	214	0	0
T4	64926	789	0	0
T15	11331	108	0	0
T16	5612	51	0	0
T17	536175	5964	0	0
T18	43968	406	0	0
T19	19274	75	0	0
T20	2765	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3410706	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3410706	0	0
T1	3490	17	0	0
T2	142855	1209	0	0
T3	957805	16351	0	0
T4	64926	434	0	0
T15	11331	90	0	0
T16	5612	51	0	0
T17	536175	5555	0	0
T18	43968	252	0	0
T19	19274	99	0	0
T20	2765	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	1477023	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	1477023	0	0
T1	3490	1	0	0
T2	142855	1533	0	0
T3	957805	154	0	0
T4	64926	940	0	0
T15	11331	121	0	0
T16	5612	42	0	0
T17	536175	1911	0	0
T18	43968	267	0	0
T19	19274	126	0	0
T20	2765	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304049251	3280192	0	0
DepthKnown_A	304049251	303930992	0	0
RvalidKnown_A	304049251	303930992	0	0
WreadyKnown_A	304049251	303930992	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	3280192	0	0
T1	3490	9	0	0
T2	142855	1106	0	0
T3	957805	12497	0	0
T4	64926	355	0	0
T15	11331	132	0	0
T16	5612	42	0	0
T17	536175	1727	0	0
T18	43968	157	0	0
T19	19274	157	0	0
T20	2765	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304049251	303930992	0	0
T1	3490	3179	0	0
T2	142855	142844	0	0
T3	957805	957773	0	0
T4	64926	64836	0	0
T15	11331	11252	0	0
T16	5612	5566	0	0
T17	536175	533968	0	0
T18	43968	43937	0	0
T19	19274	19243	0	0
T20	2765	2706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0