Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1675215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263371

1

T1

222

T2

19

T3

3817

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	654250	1			T1	568		T2	49		T3	9624
values[0x0]	628012	1			T1	590		T2	48		T3	9192
values[0x1]	656324	1			T1	534		T2	46		T3	9513

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1298684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639902

1

T1

524

T2

51

T3

9288

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7446	1			T1	41		T3	25		T5	8
valid_sources[0x01]	7554	1			T3	115		T5	10		T11	12
valid_sources[0x02]	7720	1			T2	1		T3	7		T5	8
valid_sources[0x03]	6834	1			T1	7		T3	115		T5	6
valid_sources[0x04]	7767	1			T1	16		T3	24		T5	8
valid_sources[0x05]	8307	1			T1	2		T3	10		T5	13
valid_sources[0x06]	8003	1			T1	35		T3	107		T5	9
valid_sources[0x07]	6566	1			T1	18		T3	7		T5	9
valid_sources[0x08]	7418	1			T1	1		T2	1		T3	35
valid_sources[0x09]	8385	1			T3	244		T5	2		T11	24
valid_sources[0x0a]	8576	1			T1	16		T3	42		T5	10
valid_sources[0x0b]	7958	1			T1	16		T3	40		T5	17
valid_sources[0x0c]	7980	1			T1	7		T2	1		T3	19
valid_sources[0x0d]	7236	1			T1	5		T2	3		T3	28
valid_sources[0x0e]	7495	1			T1	3		T2	1		T3	52
valid_sources[0x0f]	8898	1			T1	4		T3	58		T5	11
valid_sources[0x10]	8816	1			T1	1		T3	17		T5	11
valid_sources[0x11]	7564	1			T1	17		T2	2		T3	117
valid_sources[0x12]	7613	1			T2	3		T3	291		T5	7
valid_sources[0x13]	7716	1			T1	5		T2	1		T3	22
valid_sources[0x14]	9542	1			T1	9		T3	5		T5	9
valid_sources[0x15]	8143	1			T1	21		T3	75		T5	7
valid_sources[0x16]	6992	1			T3	2		T5	7		T11	12
valid_sources[0x17]	6847	1			T1	1		T2	1		T3	22
valid_sources[0x18]	7626	1			T1	8		T3	36		T5	6
valid_sources[0x19]	7405	1			T2	4		T3	115		T5	5
valid_sources[0x1a]	7343	1			T1	5		T3	115		T5	6
valid_sources[0x1b]	7382	1			T1	1		T2	2		T3	23
valid_sources[0x1c]	6439	1			T1	11		T2	1		T3	20
valid_sources[0x1d]	7970	1			T1	1		T3	28		T5	12
valid_sources[0x1e]	7967	1			T2	1		T3	7		T5	11
valid_sources[0x1f]	6867	1			T3	1		T5	6		T11	15
valid_sources[0x20]	7170	1			T1	2		T3	323		T5	5
valid_sources[0x21]	7321	1			T3	98		T5	9		T16	6
valid_sources[0x22]	7946	1			T1	8		T3	32		T5	11
valid_sources[0x23]	7583	1			T2	1		T3	6		T5	8
valid_sources[0x24]	7526	1			T1	50		T3	40		T5	4
valid_sources[0x25]	7884	1			T2	1		T3	29		T5	6
valid_sources[0x26]	6937	1			T1	14		T2	1		T3	11
valid_sources[0x27]	8235	1			T1	31		T2	1		T3	61
valid_sources[0x28]	8333	1			T1	7		T3	33		T5	9
valid_sources[0x29]	7559	1			T1	10		T2	1		T3	163
valid_sources[0x2a]	7365	1			T3	19		T5	10		T16	6
valid_sources[0x2b]	7293	1			T1	4		T2	1		T3	4
valid_sources[0x2c]	7245	1			T1	2		T3	70		T5	9
valid_sources[0x2d]	7051	1			T1	16		T2	1		T3	78
valid_sources[0x2e]	7286	1			T1	11		T3	17		T5	10
valid_sources[0x2f]	7324	1			T1	11		T2	1		T3	76
valid_sources[0x30]	7193	1			T3	3		T5	10		T16	5
valid_sources[0x31]	7915	1			T1	24		T3	47		T5	6
valid_sources[0x32]	7594	1			T1	8		T3	35		T5	5
valid_sources[0x33]	7267	1			T1	22		T3	72		T5	9
valid_sources[0x34]	7420	1			T1	4		T2	1		T3	86
valid_sources[0x35]	8111	1			T3	947		T5	11		T11	16
valid_sources[0x36]	7772	1			T1	14		T2	1		T3	153
valid_sources[0x37]	7159	1			T1	13		T3	36		T5	7
valid_sources[0x38]	7750	1			T1	9		T3	9		T5	11
valid_sources[0x39]	6769	1			T1	1		T3	22		T5	13
valid_sources[0x3a]	7258	1			T1	16		T2	2		T3	71
valid_sources[0x3b]	7429	1			T1	5		T2	1		T3	56
valid_sources[0x3c]	7050	1			T1	6		T3	4		T4	32
valid_sources[0x3d]	7125	1			T1	24		T3	9		T5	6
valid_sources[0x3e]	7076	1			T1	8		T3	13		T5	7
valid_sources[0x3f]	8155	1			T2	1		T3	433		T5	2
valid_sources[0x40]	7642	1			T1	2		T2	2		T3	21
valid_sources[0x41]	7390	1			T1	2		T3	3		T5	6
valid_sources[0x42]	7727	1			T3	71		T5	9		T16	6
valid_sources[0x43]	6623	1			T1	1		T2	1		T3	23
valid_sources[0x44]	7419	1			T1	1		T3	22		T5	7
valid_sources[0x45]	7054	1			T1	3		T2	1		T3	18
valid_sources[0x46]	7368	1			T1	2		T3	226		T5	5
valid_sources[0x47]	9030	1			T1	11		T3	13		T5	10
valid_sources[0x48]	8441	1			T1	4		T2	1		T3	144
valid_sources[0x49]	7736	1			T1	7		T3	533		T5	9
valid_sources[0x4a]	7530	1			T1	12		T3	166		T5	10
valid_sources[0x4b]	8198	1			T2	1		T3	2		T5	11
valid_sources[0x4c]	7269	1			T1	3		T2	1		T3	75
valid_sources[0x4d]	7492	1			T1	37		T3	17		T5	11
valid_sources[0x4e]	7776	1			T2	1		T3	106		T5	15
valid_sources[0x4f]	7505	1			T1	1		T3	13		T5	9
valid_sources[0x50]	7027	1			T1	1		T3	141		T5	8
valid_sources[0x51]	7729	1			T1	12		T3	640		T5	5
valid_sources[0x52]	6860	1			T1	1		T3	31		T5	7
valid_sources[0x53]	7305	1			T1	6		T2	1		T3	153
valid_sources[0x54]	7617	1			T1	8		T3	249		T5	9
valid_sources[0x55]	7362	1			T1	10		T3	175		T5	6
valid_sources[0x56]	7477	1			T1	4		T3	15		T5	10
valid_sources[0x57]	8549	1			T1	1		T3	80		T4	38
valid_sources[0x58]	8199	1			T1	5		T2	2		T3	5
valid_sources[0x59]	8267	1			T1	1		T3	14		T5	7
valid_sources[0x5a]	7205	1			T1	3		T3	20		T5	7
valid_sources[0x5b]	7790	1			T1	5		T3	2		T5	5
valid_sources[0x5c]	7823	1			T1	2		T3	4		T5	3
valid_sources[0x5d]	7127	1			T1	8		T3	16		T5	8
valid_sources[0x5e]	6870	1			T1	15		T2	1		T3	2
valid_sources[0x5f]	7285	1			T3	78		T5	13		T16	8
valid_sources[0x60]	6631	1			T3	73		T5	5		T16	6
valid_sources[0x61]	8459	1			T1	10		T2	4		T3	2
valid_sources[0x62]	8230	1			T1	1		T3	68		T5	8
valid_sources[0x63]	8337	1			T1	7		T2	2		T3	8
valid_sources[0x64]	7331	1			T1	2		T2	5		T3	305
valid_sources[0x65]	6551	1			T3	2		T5	15		T11	16
valid_sources[0x66]	6923	1			T2	1		T5	14		T11	16
valid_sources[0x67]	7733	1			T1	8		T2	1		T3	42
valid_sources[0x68]	7026	1			T3	42		T5	5		T16	6
valid_sources[0x69]	7043	1			T1	14		T3	92		T5	6
valid_sources[0x6a]	7305	1			T1	6		T2	1		T3	67
valid_sources[0x6b]	7505	1			T1	5		T3	5		T5	6
valid_sources[0x6c]	7156	1			T1	2		T3	355		T5	7
valid_sources[0x6d]	7795	1			T1	19		T2	2		T3	123
valid_sources[0x6e]	8249	1			T1	2		T2	1		T3	631
valid_sources[0x6f]	7219	1			T3	25		T5	14		T11	15
valid_sources[0x70]	7380	1			T3	211		T5	9		T11	15
valid_sources[0x71]	7456	1			T1	12		T3	312		T5	11
valid_sources[0x72]	8621	1			T1	7		T3	11		T5	6
valid_sources[0x73]	6723	1			T1	2		T3	36		T5	6
valid_sources[0x74]	7873	1			T1	8		T3	776		T5	7
valid_sources[0x75]	7708	1			T1	5		T3	35		T5	8
valid_sources[0x76]	7218	1			T3	219		T5	7		T16	5
valid_sources[0x77]	7387	1			T3	5		T5	6		T16	6
valid_sources[0x78]	7641	1			T1	3		T3	376		T5	7
valid_sources[0x79]	7652	1			T1	12		T3	6		T5	5
valid_sources[0x7a]	8038	1			T1	9		T2	3		T3	214
valid_sources[0x7b]	7493	1			T1	2		T3	32		T5	11
valid_sources[0x7c]	8761	1			T3	954		T5	7		T16	5
valid_sources[0x7d]	8026	1			T1	13		T2	1		T3	7
valid_sources[0x7e]	8805	1			T1	9		T2	1		T3	13
valid_sources[0x7f]	7642	1			T2	1		T3	35		T5	8
valid_sources[0x80]	6987	1			T1	3		T3	377		T5	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27541

1

T1

24

T2

2

T3

405

values[0x0]

all_enables

biggest_size

208194

1

T1

174

T2

17

T3

3000

values[0x1]

all_enables

biggest_size

27636

1

T1

24

T3

412

T4

2