Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	338355432	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338355432	0	0
T1	505344	39922	0	0
T2	46312	699	0	0
T3	3095680	130600	0	0
T4	9479456	168307	0	0
T5	5973856	130077	0	0
T11	293048	9288	0	0
T13	0	1585	0	0
T15	227280	5312	0	0
T16	7235760	1067786	0	0
T17	4700360	83883	0	0
T18	37072	581	0	0
T19	6484856	108118	0	0
T20	0	8974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1768704	1763720	0	0
T2	46312	42392	0	0
T3	3095680	3058776	0	0
T4	9479456	9476096	0	0
T5	5973856	5973576	0	0
T11	293048	288008	0	0
T16	7235760	7235648	0	0
T17	4700360	4698680	0	0
T18	37072	33040	0	0
T19	6484856	6484016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1768704	1763720	0	0
T2	46312	42392	0	0
T3	3095680	3058776	0	0
T4	9479456	9476096	0	0
T5	5973856	5973576	0	0
T11	293048	288008	0	0
T16	7235760	7235648	0	0
T17	4700360	4698680	0	0
T18	37072	33040	0	0
T19	6484856	6484016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1768704	1763720	0	0
T2	46312	42392	0	0
T3	3095680	3058776	0	0
T4	9479456	9476096	0	0
T5	5973856	5973576	0	0
T11	293048	288008	0	0
T16	7235760	7235648	0	0
T17	4700360	4698680	0	0
T18	37072	33040	0	0
T19	6484856	6484016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T11	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	122155463	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	122155463	0	0
T1	31584	13009	0	0
T2	827	270	0	0
T3	55280	52566	0	0
T4	169276	76387	0	0
T5	106676	104219	0	0
T11	5233	2326	0	0
T16	129210	6812	0	0
T17	83935	82651	0	0
T18	662	224	0	0
T19	115801	46460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	88912061	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	88912061	0	0
T1	31584	6952	0	0
T2	827	143	0	0
T3	55280	28329	0	0
T4	169276	19439	0	0
T5	106676	8483	0	0
T11	5233	2326	0	0
T16	129210	527081	0	0
T17	83935	235	0	0
T18	662	119	0	0
T19	115801	14468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1474616	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1474616	0	0
T2	827	5	0	0
T3	55280	655	0	0
T4	169276	2408	0	0
T5	106676	332	0	0
T11	5233	92	0	0
T13	0	10	0	0
T15	5682	86	0	0
T16	129210	0	0	0
T17	83935	45	0	0
T18	662	5	0	0
T19	115801	1288	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3177179	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3177179	0	0
T2	827	5	0	0
T3	55280	655	0	0
T4	169276	1867	0	0
T5	106676	81	0	0
T11	5233	92	0	0
T13	0	3	0	0
T15	5682	86	0	0
T16	129210	0	0	0
T17	83935	11	0	0
T18	662	5	0	0
T19	115801	1451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1455714	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1455714	0	0
T2	827	4	0	0
T3	55280	1148	0	0
T4	169276	2619	0	0
T5	106676	374	0	0
T11	5233	82	0	0
T13	0	40	0	0
T15	5682	99	0	0
T16	129210	0	0	0
T17	83935	52	0	0
T18	662	5	0	0
T19	115801	1855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3783922	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3783922	0	0
T2	827	4	0	0
T3	55280	1148	0	0
T4	169276	556	0	0
T5	106676	327	0	0
T11	5233	82	0	0
T13	0	10	0	0
T15	5682	99	0	0
T16	129210	0	0	0
T17	83935	12	0	0
T18	662	5	0	0
T19	115801	156	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1486761	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1486761	0	0
T2	827	6	0	0
T3	55280	706	0	0
T4	169276	730	0	0
T5	106676	336	0	0
T11	5233	92	0	0
T13	0	14	0	0
T15	5682	100	0	0
T16	129210	0	0	0
T17	83935	32	0	0
T18	662	7	0	0
T19	115801	1405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3218018	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3218018	0	0
T2	827	6	0	0
T3	55280	706	0	0
T4	169276	442	0	0
T5	106676	821	0	0
T11	5233	92	0	0
T13	0	20	0	0
T15	5682	100	0	0
T16	129210	0	0	0
T17	83935	9	0	0
T18	662	7	0	0
T19	115801	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1464971	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1464971	0	0
T1	31584	2124	0	0
T2	827	8	0	0
T3	55280	719	0	0
T4	169276	1430	0	0
T5	106676	330	0	0
T11	5233	84	0	0
T15	0	114	0	0
T16	129210	0	0	0
T17	83935	23	0	0
T18	662	6	0	0
T19	115801	989	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3631279	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3631279	0	0
T1	31584	954	0	0
T2	827	8	0	0
T3	55280	719	0	0
T4	169276	1030	0	0
T5	106676	168	0	0
T11	5233	84	0	0
T15	0	114	0	0
T16	129210	0	0	0
T17	83935	10	0	0
T18	662	6	0	0
T19	115801	533	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1428011	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1428011	0	0
T2	827	6	0	0
T3	55280	942	0	0
T4	169276	2077	0	0
T5	106676	377	0	0
T11	5233	92	0	0
T13	0	58	0	0
T15	5682	125	0	0
T16	129210	0	0	0
T17	83935	15	0	0
T18	662	4	0	0
T19	115801	0	0	0
T20	0	1828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3004660	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3004660	0	0
T2	827	6	0	0
T3	55280	942	0	0
T4	169276	767	0	0
T5	106676	387	0	0
T11	5233	92	0	0
T13	0	28	0	0
T15	5682	125	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	4	0	0
T19	115801	0	0	0
T20	0	2814	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1472276	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1472276	0	0
T2	827	1	0	0
T3	55280	698	0	0
T4	169276	1057	0	0
T5	106676	281	0	0
T11	5233	81	0	0
T13	0	28	0	0
T15	5682	106	0	0
T16	129210	0	0	0
T17	83935	35	0	0
T18	662	4	0	0
T19	115801	1080	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3643976	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3643976	0	0
T2	827	1	0	0
T3	55280	698	0	0
T4	169276	589	0	0
T5	106676	79	0	0
T11	5233	81	0	0
T13	0	5	0	0
T15	5682	106	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	4	0	0
T19	115801	566	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1491841	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1491841	0	0
T2	827	4	0	0
T3	55280	698	0	0
T4	169276	1032	0	0
T5	106676	362	0	0
T11	5233	101	0	0
T13	0	52	0	0
T15	5682	107	0	0
T16	129210	0	0	0
T17	83935	29	0	0
T18	662	3	0	0
T19	115801	564	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3573854	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3573854	0	0
T2	827	4	0	0
T3	55280	698	0	0
T4	169276	175	0	0
T5	106676	154	0	0
T11	5233	101	0	0
T13	0	12	0	0
T15	5682	107	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	3	0	0
T19	115801	819	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1417332	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1417332	0	0
T2	827	5	0	0
T3	55280	733	0	0
T4	169276	1565	0	0
T5	106676	321	0	0
T11	5233	87	0	0
T15	5682	109	0	0
T16	129210	1165	0	0
T17	83935	42	0	0
T18	662	1	0	0
T19	115801	2604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3271114	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3271114	0	0
T2	827	5	0	0
T3	55280	733	0	0
T4	169276	1298	0	0
T5	106676	83	0	0
T11	5233	87	0	0
T15	5682	109	0	0
T16	129210	91936	0	0
T17	83935	10	0	0
T18	662	1	0	0
T19	115801	661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1439346	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1439346	0	0
T1	31584	1643	0	0
T2	827	3	0	0
T3	55280	963	0	0
T4	169276	2098	0	0
T5	106676	313	0	0
T11	5233	87	0	0
T15	0	109	0	0
T16	129210	0	0	0
T17	83935	7	0	0
T18	662	3	0	0
T19	115801	1517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2532628	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2532628	0	0
T1	31584	810	0	0
T2	827	3	0	0
T3	55280	962	0	0
T4	169276	338	0	0
T5	106676	78	0	0
T11	5233	87	0	0
T15	0	109	0	0
T16	129210	0	0	0
T17	83935	2	0	0
T18	662	3	0	0
T19	115801	882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1450263	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1450263	0	0
T2	827	3	0	0
T3	55280	706	0	0
T4	169276	1712	0	0
T5	106676	363	0	0
T11	5233	80	0	0
T13	0	79	0	0
T15	5682	112	0	0
T16	129210	0	0	0
T17	83935	52	0	0
T18	662	2	0	0
T19	115801	1352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3361433	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3361433	0	0
T2	827	3	0	0
T3	55280	706	0	0
T4	169276	933	0	0
T5	106676	436	0	0
T11	5233	80	0	0
T13	0	22	0	0
T15	5682	112	0	0
T16	129210	0	0	0
T17	83935	13	0	0
T18	662	2	0	0
T19	115801	928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1456776	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1456776	0	0
T1	31584	1906	0	0
T2	827	4	0	0
T3	55280	1503	0	0
T4	169276	1613	0	0
T5	106676	279	0	0
T11	5233	91	0	0
T15	0	91	0	0
T16	129210	0	0	0
T17	83935	15	0	0
T18	662	4	0	0
T19	115801	2407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2131830	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2131830	0	0
T1	31584	1151	0	0
T2	827	4	0	0
T3	55280	1503	0	0
T4	169276	588	0	0
T5	106676	81	0	0
T11	5233	91	0	0
T15	0	91	0	0
T16	129210	0	0	0
T17	83935	4	0	0
T18	662	4	0	0
T19	115801	1918	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1449340	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1449340	0	0
T2	827	11	0	0
T3	55280	676	0	0
T4	169276	3438	0	0
T5	106676	386	0	0
T11	5233	81	0	0
T15	5682	98	0	0
T16	129210	1002	0	0
T17	83935	60	0	0
T18	662	3	0	0
T19	115801	1678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3232740	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3232740	0	0
T2	827	11	0	0
T3	55280	676	0	0
T4	169276	948	0	0
T5	106676	91	0	0
T11	5233	81	0	0
T15	5682	98	0	0
T16	129210	79929	0	0
T17	83935	11	0	0
T18	662	3	0	0
T19	115801	768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1467458	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1467458	0	0
T2	827	4	0	0
T3	55280	1478	0	0
T4	169276	1962	0	0
T5	106676	341	0	0
T11	5233	85	0	0
T13	0	53	0	0
T15	5682	115	0	0
T16	129210	0	0	0
T17	83935	39	0	0
T18	662	9	0	0
T19	115801	909	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3211563	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3211563	0	0
T2	827	4	0	0
T3	55280	1478	0	0
T4	169276	325	0	0
T5	106676	806	0	0
T11	5233	85	0	0
T13	0	32	0	0
T15	5682	115	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	9	0	0
T19	115801	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1426357	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1426357	0	0
T2	827	5	0	0
T3	55280	665	0	0
T4	169276	2920	0	0
T5	106676	309	0	0
T11	5233	91	0	0
T15	5682	102	0	0
T16	129210	1232	0	0
T17	83935	17	0	0
T18	662	4	0	0
T19	115801	1714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3208840	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3208840	0	0
T2	827	5	0	0
T3	55280	665	0	0
T4	169276	674	0	0
T5	106676	72	0	0
T11	5233	91	0	0
T15	5682	102	0	0
T16	129210	89410	0	0
T17	83935	4	0	0
T18	662	4	0	0
T19	115801	511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1443344	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1443344	0	0
T2	827	4	0	0
T3	55280	1012	0	0
T4	169276	2360	0	0
T5	106676	330	0	0
T11	5233	73	0	0
T13	0	49	0	0
T15	5682	108	0	0
T16	129210	0	0	0
T17	83935	15	0	0
T18	662	6	0	0
T19	115801	1310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2936190	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2936190	0	0
T2	827	4	0	0
T3	55280	1012	0	0
T4	169276	743	0	0
T5	106676	1205	0	0
T11	5233	73	0	0
T13	0	37	0	0
T15	5682	108	0	0
T16	129210	0	0	0
T17	83935	4	0	0
T18	662	6	0	0
T19	115801	547	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1494861	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1494861	0	0
T1	31584	1872	0	0
T2	827	4	0	0
T3	55280	1037	0	0
T4	169276	1107	0	0
T5	106676	270	0	0
T11	5233	76	0	0
T16	129210	1083	0	0
T17	83935	14	0	0
T18	662	2	0	0
T19	115801	1194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2715303	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2715303	0	0
T1	31584	837	0	0
T2	827	4	0	0
T3	55280	1036	0	0
T4	169276	355	0	0
T5	106676	70	0	0
T11	5233	76	0	0
T16	129210	82221	0	0
T17	83935	3	0	0
T18	662	2	0	0
T19	115801	211	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1456441	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1456441	0	0
T2	827	8	0	0
T3	55280	714	0	0
T4	169276	2254	0	0
T5	106676	344	0	0
T11	5233	102	0	0
T13	0	38	0	0
T15	5682	95	0	0
T16	129210	0	0	0
T17	83935	35	0	0
T18	662	3	0	0
T19	115801	998	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3146203	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3146203	0	0
T2	827	8	0	0
T3	55280	714	0	0
T4	169276	1216	0	0
T5	106676	94	0	0
T11	5233	102	0	0
T13	0	26	0	0
T15	5682	95	0	0
T16	129210	0	0	0
T17	83935	9	0	0
T18	662	3	0	0
T19	115801	296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1420728	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1420728	0	0
T2	827	6	0	0
T3	55280	1204	0	0
T4	169276	1119	0	0
T5	106676	341	0	0
T11	5233	80	0	0
T13	0	54	0	0
T15	5682	108	0	0
T16	129210	0	0	0
T17	83935	37	0	0
T18	662	4	0	0
T19	115801	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3796200	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3796200	0	0
T2	827	6	0	0
T3	55280	1204	0	0
T4	169276	800	0	0
T5	106676	81	0	0
T11	5233	80	0	0
T13	0	27	0	0
T15	5682	108	0	0
T16	129210	0	0	0
T17	83935	7	0	0
T18	662	4	0	0
T19	115801	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1506921	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1506921	0	0
T2	827	11	0	0
T3	55280	1104	0	0
T4	169276	725	0	0
T5	106676	314	0	0
T11	5233	71	0	0
T13	0	44	0	0
T15	5682	109	0	0
T16	129210	0	0	0
T17	83935	22	0	0
T18	662	4	0	0
T19	115801	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3550631	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3550631	0	0
T2	827	11	0	0
T3	55280	1103	0	0
T4	169276	56	0	0
T5	106676	75	0	0
T11	5233	71	0	0
T13	0	11	0	0
T15	5682	109	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	4	0	0
T19	115801	352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1476048	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1476048	0	0
T2	827	5	0	0
T3	55280	704	0	0
T4	169276	1291	0	0
T5	106676	321	0	0
T11	5233	79	0	0
T13	0	467	0	0
T15	5682	136	0	0
T16	129210	0	0	0
T17	83935	22	0	0
T18	662	2	0	0
T19	115801	0	0	0
T20	0	1148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	4175117	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	4175117	0	0
T2	827	5	0	0
T3	55280	704	0	0
T4	169276	828	0	0
T5	106676	77	0	0
T11	5233	79	0	0
T13	0	213	0	0
T15	5682	136	0	0
T16	129210	0	0	0
T17	83935	4	0	0
T18	662	2	0	0
T19	115801	0	0	0
T20	0	3184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1448249	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1448249	0	0
T2	827	7	0	0
T3	55280	935	0	0
T4	169276	2381	0	0
T5	106676	340	0	0
T11	5233	83	0	0
T13	0	32	0	0
T15	5682	102	0	0
T16	129210	0	0	0
T17	83935	13	0	0
T18	662	7	0	0
T19	115801	979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3541674	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3541674	0	0
T2	827	7	0	0
T3	55280	934	0	0
T4	169276	625	0	0
T5	106676	76	0	0
T11	5233	83	0	0
T13	0	13	0	0
T15	5682	102	0	0
T16	129210	0	0	0
T17	83935	2	0	0
T18	662	7	0	0
T19	115801	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1468853	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1468853	0	0
T2	827	6	0	0
T3	55280	698	0	0
T4	169276	3149	0	0
T5	106676	305	0	0
T11	5233	85	0	0
T13	0	50	0	0
T15	5682	130	0	0
T16	129210	0	0	0
T17	83935	33	0	0
T18	662	3	0	0
T19	115801	572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3719135	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3719135	0	0
T2	827	6	0	0
T3	55280	698	0	0
T4	169276	583	0	0
T5	106676	73	0	0
T11	5233	85	0	0
T13	0	20	0	0
T15	5682	130	0	0
T16	129210	0	0	0
T17	83935	67	0	0
T18	662	3	0	0
T19	115801	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1476772	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1476772	0	0
T1	31584	2135	0	0
T2	827	9	0	0
T3	55280	1454	0	0
T4	169276	2343	0	0
T5	106676	316	0	0
T11	5233	85	0	0
T15	0	95	0	0
T16	129210	0	0	0
T17	83935	31	0	0
T18	662	6	0	0
T19	115801	1021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2676263	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2676263	0	0
T1	31584	1026	0	0
T2	827	9	0	0
T3	55280	1454	0	0
T4	169276	443	0	0
T5	106676	660	0	0
T11	5233	85	0	0
T15	0	95	0	0
T16	129210	0	0	0
T17	83935	7	0	0
T18	662	6	0	0
T19	115801	436	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1492951	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1492951	0	0
T1	31584	2023	0	0
T2	827	3	0	0
T3	55280	739	0	0
T4	169276	3147	0	0
T5	106676	319	0	0
T11	5233	82	0	0
T16	129210	1300	0	0
T17	83935	10	0	0
T18	662	6	0	0
T19	115801	2330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3277800	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3277800	0	0
T1	31584	1068	0	0
T2	827	3	0	0
T3	55280	739	0	0
T4	169276	1398	0	0
T5	106676	1170	0	0
T11	5233	82	0	0
T16	129210	107462	0	0
T17	83935	3	0	0
T18	662	6	0	0
T19	115801	642	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1450656	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1450656	0	0
T2	827	1	0	0
T3	55280	655	0	0
T4	169276	2770	0	0
T5	106676	364	0	0
T11	5233	100	0	0
T15	5682	100	0	0
T16	129210	1030	0	0
T17	83935	5	0	0
T18	662	7	0	0
T19	115801	2594	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3209444	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3209444	0	0
T2	827	1	0	0
T3	55280	655	0	0
T4	169276	475	0	0
T5	106676	1095	0	0
T11	5233	100	0	0
T15	5682	100	0	0
T16	129210	76123	0	0
T17	83935	1	0	0
T18	662	7	0	0
T19	115801	595	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1458973	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1458973	0	0
T2	827	5	0	0
T3	55280	1333	0	0
T4	169276	2795	0	0
T5	106676	317	0	0
T11	5233	89	0	0
T13	0	26	0	0
T15	5682	104	0	0
T16	129210	0	0	0
T17	83935	29	0	0
T18	662	5	0	0
T19	115801	1249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	2794599	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	2794599	0	0
T2	827	5	0	0
T3	55280	1333	0	0
T4	169276	1307	0	0
T5	106676	71	0	0
T11	5233	89	0	0
T13	0	12	0	0
T15	5682	104	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	5	0	0
T19	115801	643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	1456527	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	1456527	0	0
T1	31584	1306	0	0
T2	827	5	0	0
T3	55280	976	0	0
T4	169276	940	0	0
T5	106676	307	0	0
T11	5233	87	0	0
T15	0	96	0	0
T16	129210	0	0	0
T17	83935	33	0	0
T18	662	4	0	0
T19	115801	965	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313649065	3333927	0	0
DepthKnown_A	313649065	313536912	0	0
RvalidKnown_A	313649065	313536912	0	0
WreadyKnown_A	313649065	313536912	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	3333927	0	0
T1	31584	1106	0	0
T2	827	5	0	0
T3	55280	975	0	0
T4	169276	80	0	0
T5	106676	72	0	0
T11	5233	87	0	0
T15	0	96	0	0
T16	129210	0	0	0
T17	83935	6	0	0
T18	662	4	0	0
T19	115801	1179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313649065	313536912	0	0
T1	31584	31495	0	0
T2	827	757	0	0
T3	55280	54621	0	0
T4	169276	169216	0	0
T5	106676	106671	0	0
T11	5233	5143	0	0
T16	129210	129208	0	0
T17	83935	83905	0	0
T18	662	590	0	0
T19	115801	115786	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0