Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1685361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264140

1

T1

22

T2

414

T3

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	660496	1			T1	23		T2	1007		T3	515
values[0x0]	627333	1			T1	45		T2	996		T3	502
values[0x1]	661672	1			T1	41		T2	1016		T3	469

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1305210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644291

1

T1

41

T2

960

T3

476

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7467	1			T2	15		T3	2		T4	3
valid_sources[0x01]	7490	1			T2	13		T3	3		T4	3
valid_sources[0x02]	7054	1			T2	23		T3	7		T4	3
valid_sources[0x03]	7451	1			T2	34		T3	10		T4	7
valid_sources[0x04]	8159	1			T2	18		T3	5		T4	1
valid_sources[0x05]	7554	1			T2	1		T3	4		T18	2
valid_sources[0x06]	7529	1			T2	9		T3	18		T4	7
valid_sources[0x07]	7241	1			T2	4		T3	9		T4	1
valid_sources[0x08]	7063	1			T2	31		T3	7		T4	6
valid_sources[0x09]	7433	1			T2	4		T3	7		T4	10
valid_sources[0x0a]	8391	1			T1	2		T2	3		T3	5
valid_sources[0x0b]	6943	1			T2	19		T4	5		T18	1
valid_sources[0x0c]	7923	1			T2	22		T3	8		T4	7
valid_sources[0x0d]	7800	1			T2	5		T3	1		T16	2
valid_sources[0x0e]	7530	1			T2	9		T3	7		T4	1
valid_sources[0x0f]	7863	1			T2	14		T3	6		T4	4
valid_sources[0x10]	7923	1			T2	11		T3	2		T4	1
valid_sources[0x11]	9254	1			T2	16		T3	6		T4	11
valid_sources[0x12]	6438	1			T2	9		T3	3		T4	4
valid_sources[0x13]	6591	1			T2	19		T3	8		T4	4
valid_sources[0x14]	7007	1			T2	3		T3	6		T17	50
valid_sources[0x15]	8201	1			T2	7		T3	3		T4	1
valid_sources[0x16]	8107	1			T2	24		T3	12		T4	1
valid_sources[0x17]	6438	1			T2	1		T3	1		T4	4
valid_sources[0x18]	7662	1			T2	6		T3	6		T4	2
valid_sources[0x19]	6614	1			T2	3		T3	14		T4	2
valid_sources[0x1a]	7983	1			T2	13		T3	3		T4	1
valid_sources[0x1b]	7139	1			T2	13		T3	5		T4	2
valid_sources[0x1c]	7325	1			T2	6		T3	9		T16	2
valid_sources[0x1d]	7121	1			T3	3		T4	1		T16	3
valid_sources[0x1e]	7580	1			T2	19		T3	2		T4	5
valid_sources[0x1f]	8484	1			T2	19		T3	12		T16	1
valid_sources[0x20]	7256	1			T2	10		T3	6		T4	3
valid_sources[0x21]	7732	1			T2	2		T3	10		T4	4
valid_sources[0x22]	7683	1			T2	10		T3	11		T4	4
valid_sources[0x23]	7103	1			T2	24		T3	4		T4	1
valid_sources[0x24]	7272	1			T2	17		T3	14		T4	1
valid_sources[0x25]	7471	1			T1	2		T2	16		T3	4
valid_sources[0x26]	7696	1			T2	14		T3	9		T16	2
valid_sources[0x27]	7830	1			T2	18		T3	1		T4	2
valid_sources[0x28]	7694	1			T2	22		T3	2		T4	6
valid_sources[0x29]	7244	1			T2	22		T4	10		T16	3
valid_sources[0x2a]	7274	1			T2	8		T3	3		T4	3
valid_sources[0x2b]	7206	1			T2	8		T3	6		T16	1
valid_sources[0x2c]	7386	1			T3	16		T16	1		T17	100
valid_sources[0x2d]	7952	1			T2	26		T3	10		T4	7
valid_sources[0x2e]	6759	1			T2	2		T3	4		T4	4
valid_sources[0x2f]	7670	1			T2	4		T3	11		T4	5
valid_sources[0x30]	8476	1			T2	7		T3	8		T4	2
valid_sources[0x31]	9623	1			T2	19		T3	4		T4	1
valid_sources[0x32]	7268	1			T2	28		T3	2		T16	3
valid_sources[0x33]	8642	1			T2	8		T3	8		T16	2
valid_sources[0x34]	7133	1			T2	6		T3	1		T4	2
valid_sources[0x35]	7000	1			T2	14		T3	8		T4	1
valid_sources[0x36]	7617	1			T2	10		T3	17		T4	3
valid_sources[0x37]	7438	1			T2	11		T3	2		T4	3
valid_sources[0x38]	9387	1			T2	9		T3	11		T4	4
valid_sources[0x39]	10222	1			T3	9		T4	1		T17	80
valid_sources[0x3a]	7571	1			T2	10		T3	3		T4	1
valid_sources[0x3b]	8603	1			T2	4		T3	3		T4	3
valid_sources[0x3c]	7857	1			T2	27		T3	1		T4	3
valid_sources[0x3d]	7232	1			T3	1		T4	4		T17	80
valid_sources[0x3e]	6717	1			T2	16		T3	13		T4	1
valid_sources[0x3f]	6936	1			T2	49		T3	11		T4	3
valid_sources[0x40]	7869	1			T2	14		T3	4		T4	1
valid_sources[0x41]	7347	1			T2	8		T3	4		T16	2
valid_sources[0x42]	8365	1			T2	14		T3	4		T17	101
valid_sources[0x43]	8947	1			T2	7		T3	8		T17	61
valid_sources[0x44]	7682	1			T2	30		T3	2		T4	4
valid_sources[0x45]	8328	1			T2	10		T3	9		T4	1
valid_sources[0x46]	8599	1			T2	10		T3	8		T4	5
valid_sources[0x47]	7239	1			T2	6		T3	1		T16	3
valid_sources[0x48]	7534	1			T2	14		T3	8		T4	11
valid_sources[0x49]	8262	1			T2	1		T3	9		T4	2
valid_sources[0x4a]	6389	1			T2	7		T3	7		T4	3
valid_sources[0x4b]	8718	1			T2	32		T3	3		T4	3
valid_sources[0x4c]	6802	1			T2	8		T3	14		T4	7
valid_sources[0x4d]	7580	1			T2	5		T3	7		T4	4
valid_sources[0x4e]	6919	1			T2	13		T3	5		T4	2
valid_sources[0x4f]	9474	1			T2	13		T3	5		T4	3
valid_sources[0x50]	7822	1			T2	23		T3	11		T4	9
valid_sources[0x51]	8026	1			T2	11		T3	4		T4	4
valid_sources[0x52]	7194	1			T2	4		T3	2		T4	1
valid_sources[0x53]	7605	1			T2	8		T3	6		T4	3
valid_sources[0x54]	7156	1			T2	18		T3	2		T4	2
valid_sources[0x55]	6971	1			T2	7		T3	6		T4	1
valid_sources[0x56]	6579	1			T2	11		T3	16		T16	2
valid_sources[0x57]	7429	1			T3	3		T4	3		T18	1
valid_sources[0x58]	8889	1			T2	14		T3	8		T18	1
valid_sources[0x59]	6963	1			T2	18		T3	1		T4	2
valid_sources[0x5a]	7698	1			T2	8		T3	4		T4	3
valid_sources[0x5b]	6343	1			T2	12		T3	15		T4	1
valid_sources[0x5c]	7174	1			T2	17		T3	4		T4	9
valid_sources[0x5d]	7839	1			T2	2		T3	3		T17	72
valid_sources[0x5e]	7586	1			T2	28		T3	6		T4	4
valid_sources[0x5f]	6776	1			T1	17		T2	5		T3	5
valid_sources[0x60]	7007	1			T2	36		T3	4		T4	3
valid_sources[0x61]	7192	1			T2	9		T3	2		T4	4
valid_sources[0x62]	6550	1			T2	15		T3	5		T4	4
valid_sources[0x63]	8932	1			T2	19		T3	12		T4	3
valid_sources[0x64]	7643	1			T1	10		T3	1		T4	3
valid_sources[0x65]	7505	1			T2	14		T3	1		T4	5
valid_sources[0x66]	8604	1			T2	21		T3	4		T4	3
valid_sources[0x67]	7065	1			T1	2		T2	22		T3	6
valid_sources[0x68]	8022	1			T2	5		T3	10		T4	5
valid_sources[0x69]	6845	1			T2	3		T3	5		T4	7
valid_sources[0x6a]	6941	1			T2	11		T3	5		T4	4
valid_sources[0x6b]	7530	1			T2	2		T3	5		T4	3
valid_sources[0x6c]	8527	1			T2	8		T3	7		T4	3
valid_sources[0x6d]	7073	1			T2	31		T3	6		T4	2
valid_sources[0x6e]	7054	1			T2	15		T3	7		T4	9
valid_sources[0x6f]	8391	1			T2	8		T3	4		T4	8
valid_sources[0x70]	7118	1			T2	20		T3	5		T16	1
valid_sources[0x71]	8082	1			T2	12		T3	4		T4	2
valid_sources[0x72]	8798	1			T2	15		T4	2		T16	1
valid_sources[0x73]	7238	1			T2	15		T3	6		T4	5
valid_sources[0x74]	7237	1			T2	5		T3	12		T18	2
valid_sources[0x75]	7663	1			T2	24		T3	2		T4	5
valid_sources[0x76]	7322	1			T2	16		T3	4		T4	2
valid_sources[0x77]	9259	1			T2	4		T3	16		T4	5
valid_sources[0x78]	7877	1			T1	8		T2	5		T3	4
valid_sources[0x79]	8213	1			T2	2		T3	8		T4	4
valid_sources[0x7a]	7216	1			T2	1		T3	15		T4	9
valid_sources[0x7b]	7326	1			T1	29		T2	20		T3	6
valid_sources[0x7c]	8760	1			T2	6		T3	2		T4	1
valid_sources[0x7d]	6900	1			T2	20		T3	12		T4	10
valid_sources[0x7e]	7231	1			T2	19		T3	4		T4	2
valid_sources[0x7f]	7836	1			T2	14		T4	5		T16	2
valid_sources[0x80]	7820	1			T2	18		T3	1		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28129

1

T1

2

T2

36

T3

22

values[0x0]

all_enables

biggest_size

207583

1

T1

17

T2

328

T3

159

values[0x1]

all_enables

biggest_size

28428

1

T1

3

T2

50

T3

19