Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	331386816	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	331386816	0	0
T1	8107512	199006	0	0
T2	14585256	1482323	0	0
T3	1748320	48880	0	0
T4	23891448	609606	0	0
T13	268184	5015	0	0
T16	9974720	194546	0	0
T17	25544288	667601	0	0
T18	4106088	128305	0	0
T19	2860256	51316	0	0
T20	41212136	569562	0	0
T21	0	144298	0	0
T22	0	10300	0	0
T23	0	196725	0	0
T24	0	166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8107512	8105216	0	0
T2	14585256	14585144	0	0
T3	1748320	1746752	0	0
T4	23891448	23889264	0	0
T13	268184	266056	0	0
T16	9974720	9967440	0	0
T17	25544288	25542664	0	0
T18	4106088	4103344	0	0
T19	2860256	2856392	0	0
T20	41212136	41206984	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8107512	8105216	0	0
T2	14585256	14585144	0	0
T3	1748320	1746752	0	0
T4	23891448	23889264	0	0
T13	268184	266056	0	0
T16	9974720	9967440	0	0
T17	25544288	25542664	0	0
T18	4106088	4103344	0	0
T19	2860256	2856392	0	0
T20	41212136	41206984	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8107512	8105216	0	0
T2	14585256	14585144	0	0
T3	1748320	1746752	0	0
T4	23891448	23889264	0	0
T13	268184	266056	0	0
T16	9974720	9967440	0	0
T17	25544288	25542664	0	0
T18	4106088	4103344	0	0
T19	2860256	2856392	0	0
T20	41212136	41206984	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	119471245	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	119471245	0	0
T1	144777	86729	0	0
T2	260451	257107	0	0
T3	31220	12450	0	0
T4	426633	237941	0	0
T13	4789	2164	0	0
T16	178120	81128	0	0
T17	456148	231646	0	0
T18	73323	70930	0	0
T19	51076	49489	0	0
T20	735931	3462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	88368210	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	88368210	0	0
T1	144777	37492	0	0
T2	260451	110383	0	0
T3	31220	11990	0	0
T4	426633	130706	0	0
T13	4789	689	0	0
T16	178120	29282	0	0
T17	456148	162344	0	0
T18	73323	28514	0	0
T19	51076	675	0	0
T20	735931	281319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1346075	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1346075	0	0
T1	144777	1183	0	0
T2	260451	553	0	0
T3	31220	0	0	0
T4	426633	4387	0	0
T13	4789	32	0	0
T16	178120	3254	0	0
T17	456148	4470	0	0
T18	73323	18	0	0
T19	51076	26	0	0
T20	735931	0	0	0
T21	0	3269	0	0
T22	0	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3330581	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3330581	0	0
T1	144777	1252	0	0
T2	260451	44287	0	0
T3	31220	0	0	0
T4	426633	5129	0	0
T13	4789	11	0	0
T16	178120	1662	0	0
T17	456148	4649	0	0
T18	73323	2346	0	0
T19	51076	5	0	0
T20	735931	0	0	0
T21	0	5672	0	0
T22	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1327796	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1327796	0	0
T1	144777	2217	0	0
T2	260451	478	0	0
T3	31220	0	0	0
T4	426633	5829	0	0
T13	4789	61	0	0
T16	178120	1521	0	0
T17	456148	3192	0	0
T18	73323	0	0	0
T19	51076	8	0	0
T20	735931	0	0	0
T21	0	2106	0	0
T22	0	243	0	0
T23	0	1246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2846286	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2846286	0	0
T1	144777	919	0	0
T2	260451	40817	0	0
T3	31220	0	0	0
T4	426633	6092	0	0
T13	4789	45	0	0
T16	178120	895	0	0
T17	456148	3633	0	0
T18	73323	0	0	0
T19	51076	1	0	0
T20	735931	0	0	0
T21	0	1522	0	0
T22	0	192	0	0
T23	0	108827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1353483	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1353483	0	0
T1	144777	1627	0	0
T2	260451	475	0	0
T3	31220	0	0	0
T4	426633	2546	0	0
T13	4789	76	0	0
T16	178120	1719	0	0
T17	456148	2264	0	0
T18	73323	0	0	0
T19	51076	13	0	0
T20	735931	0	0	0
T21	0	3300	0	0
T22	0	305	0	0
T23	0	1077	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3379722	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3379722	0	0
T1	144777	3028	0	0
T2	260451	36354	0	0
T3	31220	0	0	0
T4	426633	2783	0	0
T13	4789	23	0	0
T16	178120	979	0	0
T17	456148	2248	0	0
T18	73323	0	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	3299	0	0
T22	0	301	0	0
T23	0	85575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1324579	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1324579	0	0
T1	144777	2337	0	0
T2	260451	395	0	0
T3	31220	0	0	0
T4	426633	6571	0	0
T13	4789	20	0	0
T16	178120	1484	0	0
T17	456148	2265	0	0
T18	73323	25	0	0
T19	51076	3	0	0
T20	735931	0	0	0
T21	0	3637	0	0
T22	0	302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3217118	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3217118	0	0
T1	144777	3133	0	0
T2	260451	33133	0	0
T3	31220	0	0	0
T4	426633	6530	0	0
T13	4789	20	0	0
T16	178120	1015	0	0
T17	456148	2194	0	0
T18	73323	1750	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	2752	0	0
T22	0	311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1345809	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1345809	0	0
T1	144777	1898	0	0
T2	260451	438	0	0
T3	31220	4154	0	0
T4	426633	2885	0	0
T13	4789	10	0	0
T16	178120	1380	0	0
T17	456148	3667	0	0
T18	73323	7	0	0
T19	51076	38	0	0
T20	735931	0	0	0
T21	0	2422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3453095	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3453095	0	0
T1	144777	2219	0	0
T2	260451	37262	0	0
T3	31220	3917	0	0
T4	426633	3007	0	0
T13	4789	6	0	0
T16	178120	737	0	0
T17	456148	3926	0	0
T18	73323	1228	0	0
T19	51076	10	0	0
T20	735931	0	0	0
T21	0	2095	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1364951	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1364951	0	0
T1	144777	1021	0	0
T2	260451	456	0	0
T3	31220	0	0	0
T4	426633	9233	0	0
T13	4789	51	0	0
T16	178120	1443	0	0
T17	456148	2100	0	0
T18	73323	20	0	0
T19	51076	18	0	0
T20	735931	0	0	0
T21	0	889	0	0
T22	0	222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2877050	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2877050	0	0
T1	144777	1213	0	0
T2	260451	37952	0	0
T3	31220	0	0	0
T4	426633	9282	0	0
T13	4789	32	0	0
T16	178120	848	0	0
T17	456148	1915	0	0
T18	73323	1793	0	0
T19	51076	5	0	0
T20	735931	0	0	0
T21	0	1631	0	0
T22	0	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1399971	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1399971	0	0
T1	144777	1436	0	0
T2	260451	597	0	0
T3	31220	0	0	0
T4	426633	4141	0	0
T13	4789	72	0	0
T16	178120	1975	0	0
T17	456148	8078	0	0
T18	73323	20	0	0
T19	51076	32	0	0
T20	735931	1113	0	0
T21	0	1793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3370124	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3370124	0	0
T1	144777	765	0	0
T2	260451	48858	0	0
T3	31220	0	0	0
T4	426633	4135	0	0
T13	4789	56	0	0
T16	178120	999	0	0
T17	456148	8537	0	0
T18	73323	1370	0	0
T19	51076	5	0	0
T20	735931	92244	0	0
T21	0	2836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1348824	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1348824	0	0
T1	144777	781	0	0
T2	260451	408	0	0
T3	31220	0	0	0
T4	426633	2943	0	0
T13	4789	69	0	0
T16	178120	1550	0	0
T17	456148	3523	0	0
T18	73323	14	0	0
T19	51076	36	0	0
T20	735931	0	0	0
T21	0	396	0	0
T22	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3575444	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3575444	0	0
T1	144777	760	0	0
T2	260451	36332	0	0
T3	31220	0	0	0
T4	426633	2838	0	0
T13	4789	21	0	0
T16	178120	794	0	0
T17	456148	3623	0	0
T18	73323	2984	0	0
T19	51076	7	0	0
T20	735931	0	0	0
T21	0	713	0	0
T22	0	231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1368759	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1368759	0	0
T1	144777	2528	0	0
T2	260451	501	0	0
T3	31220	0	0	0
T4	426633	6950	0	0
T13	4789	49	0	0
T16	178120	4221	0	0
T17	456148	6487	0	0
T18	73323	9	0	0
T19	51076	8	0	0
T20	735931	0	0	0
T21	0	2148	0	0
T22	0	231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2857762	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2857762	0	0
T1	144777	2190	0	0
T2	260451	41569	0	0
T3	31220	0	0	0
T4	426633	6713	0	0
T13	4789	60	0	0
T16	178120	1777	0	0
T17	456148	6213	0	0
T18	73323	580	0	0
T19	51076	1	0	0
T20	735931	0	0	0
T21	0	1770	0	0
T22	0	283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1329254	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1329254	0	0
T1	144777	975	0	0
T2	260451	560	0	0
T3	31220	0	0	0
T4	426633	7166	0	0
T13	4789	33	0	0
T16	178120	1411	0	0
T17	456148	2255	0	0
T18	73323	17	0	0
T19	51076	9	0	0
T20	735931	0	0	0
T21	0	3945	0	0
T22	0	287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2634949	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2634949	0	0
T1	144777	781	0	0
T2	260451	44374	0	0
T3	31220	0	0	0
T4	426633	6815	0	0
T13	4789	15	0	0
T16	178120	769	0	0
T17	456148	2074	0	0
T18	73323	2115	0	0
T19	51076	4	0	0
T20	735931	0	0	0
T21	0	5991	0	0
T22	0	259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1356150	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1356150	0	0
T1	144777	413	0	0
T2	260451	461	0	0
T3	31220	0	0	0
T4	426633	2826	0	0
T13	4789	21	0	0
T16	178120	1721	0	0
T17	456148	4134	0	0
T18	73323	4	0	0
T19	51076	8	0	0
T20	735931	0	0	0
T21	0	3633	0	0
T22	0	229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2725359	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2725359	0	0
T1	144777	792	0	0
T2	260451	37868	0	0
T3	31220	0	0	0
T4	426633	2851	0	0
T13	4789	1	0	0
T16	178120	947	0	0
T17	456148	3951	0	0
T18	73323	1069	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	5124	0	0
T22	0	253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1324231	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1324231	0	0
T1	144777	1301	0	0
T2	260451	590	0	0
T3	31220	0	0	0
T4	426633	2951	0	0
T13	4789	56	0	0
T16	178120	1580	0	0
T17	456148	4494	0	0
T18	73323	18	0	0
T19	51076	30	0	0
T20	735931	1039	0	0
T21	0	3902	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3689707	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3689707	0	0
T1	144777	1885	0	0
T2	260451	45922	0	0
T3	31220	0	0	0
T4	426633	3131	0	0
T13	4789	12	0	0
T16	178120	735	0	0
T17	456148	4373	0	0
T18	73323	1587	0	0
T19	51076	581	0	0
T20	735931	84405	0	0
T21	0	3039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1345283	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1345283	0	0
T1	144777	1015	0	0
T2	260451	413	0	0
T3	31220	0	0	0
T4	426633	5040	0	0
T13	4789	13	0	0
T16	178120	1678	0	0
T17	456148	8321	0	0
T18	73323	21	0	0
T19	51076	9	0	0
T20	735931	0	0	0
T21	0	2083	0	0
T22	0	291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3640249	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3640249	0	0
T1	144777	1327	0	0
T2	260451	36155	0	0
T3	31220	0	0	0
T4	426633	5156	0	0
T13	4789	25	0	0
T16	178120	793	0	0
T17	456148	8153	0	0
T18	73323	1528	0	0
T19	51076	1	0	0
T20	735931	0	0	0
T21	0	3014	0	0
T22	0	220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1363989	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1363989	0	0
T1	144777	4027	0	0
T2	260451	499	0	0
T3	31220	0	0	0
T4	426633	2789	0	0
T13	4789	33	0	0
T16	178120	2454	0	0
T17	456148	4229	0	0
T18	73323	5	0	0
T19	51076	23	0	0
T20	735931	0	0	0
T21	0	5650	0	0
T22	0	222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2519774	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2519774	0	0
T1	144777	3474	0	0
T2	260451	44847	0	0
T3	31220	0	0	0
T4	426633	2788	0	0
T13	4789	11	0	0
T16	178120	1643	0	0
T17	456148	4086	0	0
T18	73323	410	0	0
T19	51076	4	0	0
T20	735931	0	0	0
T21	0	9167	0	0
T22	0	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1313559	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1313559	0	0
T1	144777	1118	0	0
T2	260451	487	0	0
T3	31220	0	0	0
T4	426633	4889	0	0
T13	4789	84	0	0
T16	178120	3808	0	0
T17	456148	8443	0	0
T18	73323	21	0	0
T19	51076	33	0	0
T20	735931	0	0	0
T21	0	939	0	0
T22	0	298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3240201	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3240201	0	0
T1	144777	1058	0	0
T2	260451	43087	0	0
T3	31220	0	0	0
T4	426633	4704	0	0
T13	4789	26	0	0
T16	178120	1965	0	0
T17	456148	8266	0	0
T18	73323	1347	0	0
T19	51076	6	0	0
T20	735931	0	0	0
T21	0	551	0	0
T22	0	243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1308293	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1308293	0	0
T1	144777	409	0	0
T2	260451	533	0	0
T3	31220	0	0	0
T4	426633	4755	0	0
T13	4789	80	0	0
T16	178120	1679	0	0
T17	456148	7810	0	0
T18	73323	18	0	0
T19	51076	12	0	0
T20	735931	1310	0	0
T21	0	2799	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3439063	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3439063	0	0
T1	144777	916	0	0
T2	260451	42389	0	0
T3	31220	0	0	0
T4	426633	4617	0	0
T13	4789	43	0	0
T16	178120	824	0	0
T17	456148	8007	0	0
T18	73323	1472	0	0
T19	51076	3	0	0
T20	735931	104670	0	0
T21	0	3473	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1414958	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1414958	0	0
T1	144777	1863	0	0
T2	260451	503	0	0
T3	31220	2278	0	0
T4	426633	6141	0	0
T13	4789	33	0	0
T16	178120	1645	0	0
T17	456148	13094	0	0
T18	73323	0	0	0
T19	51076	10	0	0
T20	735931	0	0	0
T21	0	1978	0	0
T22	0	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	4080673	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	4080673	0	0
T1	144777	1025	0	0
T2	260451	34788	0	0
T3	31220	2044	0	0
T4	426633	6212	0	0
T13	4789	8	0	0
T16	178120	927	0	0
T17	456148	12806	0	0
T18	73323	0	0	0
T19	51076	1	0	0
T20	735931	0	0	0
T21	0	1037	0	0
T22	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1315406	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1315406	0	0
T1	144777	1925	0	0
T2	260451	504	0	0
T3	31220	0	0	0
T4	426633	2745	0	0
T13	4789	102	0	0
T16	178120	1446	0	0
T17	456148	10811	0	0
T18	73323	3	0	0
T19	51076	0	0	0
T20	735931	0	0	0
T21	0	1870	0	0
T22	0	201	0	0
T24	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3384504	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3384504	0	0
T1	144777	2880	0	0
T2	260451	44520	0	0
T3	31220	0	0	0
T4	426633	2510	0	0
T13	4789	29	0	0
T16	178120	809	0	0
T17	456148	10947	0	0
T18	73323	212	0	0
T19	51076	0	0	0
T20	735931	0	0	0
T21	0	2569	0	0
T22	0	188	0	0
T24	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1336297	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1336297	0	0
T1	144777	406	0	0
T2	260451	558	0	0
T3	31220	0	0	0
T4	426633	7063	0	0
T13	4789	81	0	0
T16	178120	3006	0	0
T17	456148	3566	0	0
T18	73323	14	0	0
T19	51076	17	0	0
T20	735931	0	0	0
T21	0	4207	0	0
T22	0	288	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3700007	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3700007	0	0
T1	144777	97	0	0
T2	260451	49632	0	0
T3	31220	0	0	0
T4	426633	6925	0	0
T13	4789	30	0	0
T16	178120	1653	0	0
T17	456148	3402	0	0
T18	73323	360	0	0
T19	51076	5	0	0
T20	735931	0	0	0
T21	0	4631	0	0
T22	0	369	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1342584	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1342584	0	0
T1	144777	886	0	0
T2	260451	499	0	0
T3	31220	0	0	0
T4	426633	4270	0	0
T13	4789	92	0	0
T16	178120	1905	0	0
T17	456148	5598	0	0
T18	73323	29	0	0
T19	51076	10	0	0
T20	735931	0	0	0
T21	0	4920	0	0
T22	0	262	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3128502	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3128502	0	0
T1	144777	357	0	0
T2	260451	46679	0	0
T3	31220	0	0	0
T4	426633	4284	0	0
T13	4789	49	0	0
T16	178120	1025	0	0
T17	456148	5349	0	0
T18	73323	966	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	2853	0	0
T22	0	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1324493	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1324493	0	0
T1	144777	1523	0	0
T2	260451	406	0	0
T3	31220	0	0	0
T4	426633	3003	0	0
T13	4789	50	0	0
T16	178120	2957	0	0
T17	456148	4209	0	0
T18	73323	1	0	0
T19	51076	12	0	0
T20	735931	0	0	0
T21	0	2297	0	0
T22	0	302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3455494	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3455494	0	0
T1	144777	2316	0	0
T2	260451	39012	0	0
T3	31220	0	0	0
T4	426633	3140	0	0
T13	4789	15	0	0
T16	178120	1478	0	0
T17	456148	4112	0	0
T18	73323	271	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	1755	0	0
T22	0	218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1335783	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1335783	0	0
T1	144777	370	0	0
T2	260451	411	0	0
T3	31220	3851	0	0
T4	426633	2806	0	0
T13	4789	45	0	0
T16	178120	1437	0	0
T17	456148	5309	0	0
T18	73323	5	0	0
T19	51076	24	0	0
T20	735931	0	0	0
T21	0	2325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3515004	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3515004	0	0
T1	144777	853	0	0
T2	260451	37991	0	0
T3	31220	3824	0	0
T4	426633	2662	0	0
T13	4789	32	0	0
T16	178120	779	0	0
T17	456148	5384	0	0
T18	73323	918	0	0
T19	51076	6	0	0
T20	735931	0	0	0
T21	0	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1356879	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1356879	0	0
T1	144777	1876	0	0
T2	260451	457	0	0
T3	31220	0	0	0
T4	426633	5019	0	0
T13	4789	67	0	0
T16	178120	1773	0	0
T17	456148	3847	0	0
T18	73323	25	0	0
T19	51076	17	0	0
T20	735931	0	0	0
T21	0	2300	0	0
T22	0	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2761004	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2761004	0	0
T1	144777	751	0	0
T2	260451	37579	0	0
T3	31220	0	0	0
T4	426633	5268	0	0
T13	4789	23	0	0
T16	178120	876	0	0
T17	456148	3657	0	0
T18	73323	1059	0	0
T19	51076	4	0	0
T20	735931	0	0	0
T21	0	2707	0	0
T22	0	196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1329752	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1329752	0	0
T1	144777	923	0	0
T2	260451	478	0	0
T3	31220	0	0	0
T4	426633	3007	0	0
T13	4789	46	0	0
T16	178120	3389	0	0
T17	456148	4704	0	0
T18	73323	4	0	0
T19	51076	13	0	0
T20	735931	0	0	0
T21	0	2783	0	0
T22	0	194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3182881	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3182881	0	0
T1	144777	741	0	0
T2	260451	38724	0	0
T3	31220	0	0	0
T4	426633	2997	0	0
T13	4789	25	0	0
T16	178120	1609	0	0
T17	456148	4478	0	0
T18	73323	514	0	0
T19	51076	2	0	0
T20	735931	0	0	0
T21	0	1326	0	0
T22	0	221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1349361	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1349361	0	0
T1	144777	827	0	0
T2	260451	398	0	0
T3	31220	2167	0	0
T4	426633	4247	0	0
T13	4789	38	0	0
T16	178120	1635	0	0
T17	456148	2146	0	0
T18	73323	2	0	0
T19	51076	42	0	0
T20	735931	0	0	0
T21	0	2535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2975351	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2975351	0	0
T1	144777	844	0	0
T2	260451	38386	0	0
T3	31220	2205	0	0
T4	426633	4304	0	0
T13	4789	18	0	0
T16	178120	897	0	0
T17	456148	1964	0	0
T18	73323	205	0	0
T19	51076	8	0	0
T20	735931	0	0	0
T21	0	1819	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1328022	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1328022	0	0
T1	144777	1132	0	0
T2	260451	512	0	0
T3	31220	0	0	0
T4	426633	3263	0	0
T13	4789	30	0	0
T16	178120	1620	0	0
T17	456148	4323	0	0
T18	73323	30	0	0
T19	51076	9	0	0
T20	735931	0	0	0
T21	0	947	0	0
T22	0	204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	3335712	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	3335712	0	0
T1	144777	762	0	0
T2	260451	49752	0	0
T3	31220	0	0	0
T4	426633	3071	0	0
T13	4789	12	0	0
T16	178120	933	0	0
T17	456148	4491	0	0
T18	73323	2185	0	0
T19	51076	3	0	0
T20	735931	0	0	0
T21	0	1045	0	0
T22	0	202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	1314980	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	1314980	0	0
T1	144777	1276	0	0
T2	260451	451	0	0
T3	31220	0	0	0
T4	426633	2807	0	0
T13	4789	129	0	0
T16	178120	1322	0	0
T17	456148	3919	0	0
T18	73323	17	0	0
T19	51076	17	0	0
T20	735931	0	0	0
T21	0	911	0	0
T22	0	312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296689556	2962224	0	0
DepthKnown_A	296689556	296566881	0	0
RvalidKnown_A	296689556	296566881	0	0
WreadyKnown_A	296689556	296566881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	2962224	0	0
T1	144777	1154	0	0
T2	260451	33543	0	0
T3	31220	0	0	0
T4	426633	2743	0	0
T13	4789	41	0	0
T16	178120	755	0	0
T17	456148	3915	0	0
T18	73323	245	0	0
T19	51076	3	0	0
T20	735931	0	0	0
T21	0	659	0	0
T22	0	381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296689556	296566881	0	0
T1	144777	144736	0	0
T2	260451	260449	0	0
T3	31220	31192	0	0
T4	426633	426594	0	0
T13	4789	4751	0	0
T16	178120	177990	0	0
T17	456148	456119	0	0
T18	73323	73274	0	0
T19	51076	51007	0	0
T20	735931	735839	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0