Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1779873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

279750

1

T1

676

T2

39

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	697843	1			T1	1632		T2	188		T3	41
values[0x0]	665500	1			T1	1649		T2	32		T3	27
values[0x1]	696280	1			T1	1753		T2	177		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1379947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

679676

1

T1

1640

T2

153

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7224	1			T1	26		T2	2		T13	3
valid_sources[0x01]	7804	1			T1	21		T2	3		T16	5
valid_sources[0x02]	8884	1			T1	17		T2	1		T12	52
valid_sources[0x03]	7669	1			T1	22		T2	3		T12	34
valid_sources[0x04]	8053	1			T1	21		T2	2		T12	262
valid_sources[0x05]	7837	1			T1	25		T2	2		T12	43
valid_sources[0x06]	7814	1			T1	20		T2	3		T16	15
valid_sources[0x07]	7589	1			T1	23		T2	2		T12	20
valid_sources[0x08]	8214	1			T1	20		T2	2		T12	180
valid_sources[0x09]	7137	1			T1	15		T2	4		T13	1
valid_sources[0x0a]	7237	1			T1	21		T2	1		T15	2
valid_sources[0x0b]	7576	1			T1	20		T13	1		T16	11
valid_sources[0x0c]	8352	1			T1	22		T2	3		T16	27
valid_sources[0x0d]	9574	1			T1	27		T2	3		T12	193
valid_sources[0x0e]	7221	1			T1	21		T2	2		T12	5
valid_sources[0x0f]	8028	1			T1	26		T2	2		T15	1
valid_sources[0x10]	8887	1			T1	27		T2	3		T15	4
valid_sources[0x11]	8063	1			T1	25		T2	2		T4	6
valid_sources[0x12]	7911	1			T1	17		T2	1		T15	2
valid_sources[0x13]	7247	1			T1	13		T13	1		T16	5
valid_sources[0x14]	8088	1			T1	18		T12	12		T16	2
valid_sources[0x15]	7288	1			T1	15		T2	3		T13	1
valid_sources[0x16]	8100	1			T1	24		T2	2		T15	1
valid_sources[0x17]	8062	1			T1	13		T2	4		T15	2
valid_sources[0x18]	7200	1			T1	10		T2	1		T15	3
valid_sources[0x19]	7402	1			T1	23		T2	3		T16	11
valid_sources[0x1a]	8613	1			T1	23		T2	1		T15	1
valid_sources[0x1b]	8302	1			T1	26		T16	71		T18	11
valid_sources[0x1c]	7840	1			T1	37		T2	2		T13	3
valid_sources[0x1d]	8640	1			T1	18		T2	3		T17	8
valid_sources[0x1e]	7156	1			T1	12		T2	2		T16	24
valid_sources[0x1f]	7754	1			T1	17		T2	2		T12	16
valid_sources[0x20]	7550	1			T1	15		T2	1		T16	14
valid_sources[0x21]	7241	1			T1	18		T13	1		T16	15
valid_sources[0x22]	7403	1			T1	24		T12	14		T16	8
valid_sources[0x23]	8674	1			T1	24		T2	5		T12	17
valid_sources[0x24]	7729	1			T1	17		T2	3		T13	1
valid_sources[0x25]	8094	1			T1	11		T2	1		T12	33
valid_sources[0x26]	7233	1			T1	15		T2	3		T13	2
valid_sources[0x27]	8837	1			T1	14		T2	2		T13	1
valid_sources[0x28]	7513	1			T1	15		T2	2		T16	28
valid_sources[0x29]	8054	1			T1	19		T2	2		T4	6
valid_sources[0x2a]	7906	1			T1	31		T2	4		T4	1
valid_sources[0x2b]	7808	1			T1	19		T2	2		T13	1
valid_sources[0x2c]	7874	1			T1	26		T2	1		T13	2
valid_sources[0x2d]	7549	1			T1	20		T13	1		T16	11
valid_sources[0x2e]	7671	1			T1	27		T15	2		T16	15
valid_sources[0x2f]	7934	1			T1	23		T12	21		T13	1
valid_sources[0x30]	8854	1			T1	27		T13	2		T16	2
valid_sources[0x31]	8151	1			T1	15		T2	1		T13	1
valid_sources[0x32]	7623	1			T1	20		T2	1		T12	17
valid_sources[0x33]	7527	1			T1	23		T2	5		T4	3
valid_sources[0x34]	7459	1			T1	12		T16	17		T18	11
valid_sources[0x35]	8248	1			T1	32		T2	1		T13	2
valid_sources[0x36]	8256	1			T1	34		T13	1		T16	19
valid_sources[0x37]	9345	1			T1	14		T13	1		T18	10
valid_sources[0x38]	7972	1			T1	18		T2	1		T13	1
valid_sources[0x39]	8307	1			T1	12		T12	15		T16	1
valid_sources[0x3a]	8030	1			T1	21		T15	1		T16	1
valid_sources[0x3b]	7796	1			T1	13		T2	2		T13	3
valid_sources[0x3c]	8185	1			T1	17		T13	1		T18	13
valid_sources[0x3d]	7760	1			T1	19		T2	1		T12	28
valid_sources[0x3e]	9454	1			T1	24		T12	166		T18	12
valid_sources[0x3f]	7589	1			T1	14		T2	2		T3	54
valid_sources[0x40]	8824	1			T1	12		T2	3		T12	32
valid_sources[0x41]	9021	1			T1	16		T2	2		T13	1
valid_sources[0x42]	7975	1			T1	17		T2	2		T12	9
valid_sources[0x43]	7693	1			T1	24		T2	4		T16	2
valid_sources[0x44]	8373	1			T1	22		T2	2		T15	1
valid_sources[0x45]	8022	1			T1	11		T2	3		T15	1
valid_sources[0x46]	7898	1			T1	19		T2	1		T12	152
valid_sources[0x47]	8262	1			T1	21		T2	1		T16	11
valid_sources[0x48]	7525	1			T1	21		T16	43		T18	10
valid_sources[0x49]	7636	1			T1	17		T17	13		T18	18
valid_sources[0x4a]	8113	1			T1	19		T2	1		T13	3
valid_sources[0x4b]	7970	1			T1	27		T13	3		T16	6
valid_sources[0x4c]	7380	1			T1	20		T2	3		T15	2
valid_sources[0x4d]	7959	1			T1	21		T2	3		T13	1
valid_sources[0x4e]	7600	1			T1	15		T2	1		T13	5
valid_sources[0x4f]	8632	1			T1	25		T2	3		T12	507
valid_sources[0x50]	7983	1			T1	16		T2	2		T12	201
valid_sources[0x51]	8073	1			T1	24		T2	4		T4	8
valid_sources[0x52]	8801	1			T1	14		T2	3		T13	1
valid_sources[0x53]	7317	1			T1	21		T2	2		T12	140
valid_sources[0x54]	7887	1			T1	34		T2	1		T13	2
valid_sources[0x55]	8290	1			T1	30		T2	1		T12	34
valid_sources[0x56]	8157	1			T1	10		T2	2		T12	16
valid_sources[0x57]	7232	1			T1	14		T2	1		T13	1
valid_sources[0x58]	8271	1			T1	14		T13	1		T15	1
valid_sources[0x59]	7730	1			T1	22		T2	2		T12	18
valid_sources[0x5a]	8466	1			T1	26		T2	1		T13	2
valid_sources[0x5b]	7650	1			T1	25		T2	4		T13	1
valid_sources[0x5c]	9347	1			T1	10		T2	1		T12	176
valid_sources[0x5d]	7736	1			T1	14		T2	3		T12	14
valid_sources[0x5e]	7596	1			T1	24		T2	2		T13	1
valid_sources[0x5f]	7432	1			T1	25		T2	1		T12	1
valid_sources[0x60]	7435	1			T1	24		T15	2		T16	1
valid_sources[0x61]	7333	1			T1	18		T2	2		T13	1
valid_sources[0x62]	7865	1			T1	21		T2	1		T13	1
valid_sources[0x63]	7851	1			T1	21		T2	3		T12	20
valid_sources[0x64]	8524	1			T1	14		T2	1		T15	2
valid_sources[0x65]	8605	1			T1	21		T3	55		T16	7
valid_sources[0x66]	8140	1			T1	15		T2	2		T13	1
valid_sources[0x67]	7388	1			T1	28		T12	139		T13	1
valid_sources[0x68]	7342	1			T1	11		T2	2		T12	51
valid_sources[0x69]	8362	1			T1	27		T2	1		T15	9
valid_sources[0x6a]	8075	1			T1	9		T2	2		T12	6
valid_sources[0x6b]	8065	1			T1	19		T2	3		T13	1
valid_sources[0x6c]	9026	1			T1	21		T2	3		T12	19
valid_sources[0x6d]	8138	1			T1	15		T2	4		T12	127
valid_sources[0x6e]	8741	1			T1	26		T2	1		T18	16
valid_sources[0x6f]	8092	1			T1	14		T16	1		T18	9
valid_sources[0x70]	8793	1			T1	17		T2	1		T13	1
valid_sources[0x71]	7542	1			T1	18		T2	2		T13	1
valid_sources[0x72]	8976	1			T1	27		T2	2		T12	496
valid_sources[0x73]	8827	1			T1	23		T2	2		T13	1
valid_sources[0x74]	7492	1			T1	11		T2	2		T15	2
valid_sources[0x75]	8870	1			T1	18		T12	274		T13	1
valid_sources[0x76]	8033	1			T1	30		T2	1		T13	2
valid_sources[0x77]	7548	1			T1	17		T2	2		T13	1
valid_sources[0x78]	8172	1			T1	21		T2	1		T16	5
valid_sources[0x79]	7805	1			T1	28		T2	3		T16	4
valid_sources[0x7a]	8006	1			T1	18		T16	2		T17	24
valid_sources[0x7b]	7996	1			T1	20		T2	1		T13	2
valid_sources[0x7c]	8120	1			T1	14		T12	390		T13	3
valid_sources[0x7d]	8579	1			T1	23		T2	1		T16	1
valid_sources[0x7e]	7822	1			T1	26		T2	6		T13	1
valid_sources[0x7f]	7842	1			T1	21		T2	1		T12	49
valid_sources[0x80]	7252	1			T1	18		T16	3		T17	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29589

1

T1

62

T2

12

T3

1

values[0x0]

all_enables

biggest_size

220579

1

T1

539

T2

15

T3

7

values[0x1]

all_enables

biggest_size

29582

1

T1

75

T2

12

T3

1