Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	342513308	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342513308	0	0
T1	2993152	142624	0	0
T2	1045072	44025	0	0
T3	24696	536	0	0
T4	3561208	62995	0	0
T12	785680	32811	0	0
T13	5885040	141978	0	0
T14	18928	498	0	0
T15	9115176	159024	0	0
T16	1631000	33542	0	0
T17	4168640	61924	0	0
T18	159432	1482	0	0
T19	0	674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5238016	5236000	0	0
T2	1045072	1003016	0	0
T3	24696	23296	0	0
T4	3561208	3559472	0	0
T12	785680	752472	0	0
T13	5885040	5880728	0	0
T14	18928	17808	0	0
T15	9115176	9111256	0	0
T16	1631000	1629544	0	0
T17	4168640	4168024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5238016	5236000	0	0
T2	1045072	1003016	0	0
T3	24696	23296	0	0
T4	3561208	3559472	0	0
T12	785680	752472	0	0
T13	5885040	5880728	0	0
T14	18928	17808	0	0
T15	9115176	9111256	0	0
T16	1631000	1629544	0	0
T17	4168640	4168024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5238016	5236000	0	0
T2	1045072	1003016	0	0
T3	24696	23296	0	0
T4	3561208	3559472	0	0
T12	785680	752472	0	0
T13	5885040	5880728	0	0
T14	18928	17808	0	0
T15	9115176	9111256	0	0
T16	1631000	1629544	0	0
T17	4168640	4168024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	120980547	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	120980547	0	0
T1	93536	40639	0	0
T2	18662	17361	0	0
T3	441	209	0	0
T4	63593	62214	0	0
T12	14030	13078	0	0
T13	105090	56495	0	0
T14	338	192	0	0
T15	162771	68374	0	0
T16	29125	14140	0	0
T17	74440	15113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	91863682	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	91863682	0	0
T1	93536	30673	0	0
T2	18662	9152	0	0
T3	441	109	0	0
T4	63593	130	0	0
T12	14030	7102	0	0
T13	105090	35816	0	0
T14	338	102	0	0
T15	162771	21620	0	0
T16	29125	8912	0	0
T17	74440	15858	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1460824	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1460824	0	0
T2	18662	183	0	0
T3	441	2	0	0
T4	63593	22	0	0
T12	14030	136	0	0
T13	105090	899	0	0
T14	338	4	0	0
T15	162771	3537	0	0
T16	29125	258	0	0
T17	74440	686	0	0
T18	6643	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3698423	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3698423	0	0
T2	18662	183	0	0
T3	441	2	0	0
T4	63593	4	0	0
T12	14030	136	0	0
T13	105090	845	0	0
T14	338	4	0	0
T15	162771	1414	0	0
T16	29125	234	0	0
T17	74440	677	0	0
T18	6643	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1516463	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1516463	0	0
T1	93536	2140	0	0
T2	18662	445	0	0
T3	441	6	0	0
T4	63593	31	0	0
T12	14030	155	0	0
T13	105090	901	0	0
T14	338	5	0	0
T15	162771	725	0	0
T16	29125	95	0	0
T17	74440	508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	4073677	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	4073677	0	0
T1	93536	1507	0	0
T2	18662	445	0	0
T3	441	6	0	0
T4	63593	5	0	0
T12	14030	155	0	0
T13	105090	800	0	0
T14	338	5	0	0
T15	162771	1043	0	0
T16	29125	64	0	0
T17	74440	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1456285	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1456285	0	0
T1	93536	2039	0	0
T2	18662	417	0	0
T3	441	4	0	0
T4	63593	20	0	0
T12	14030	130	0	0
T13	105090	988	0	0
T14	338	2	0	0
T15	162771	3127	0	0
T16	29125	182	0	0
T17	74440	626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3273800	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3273800	0	0
T1	93536	1268	0	0
T2	18662	416	0	0
T3	441	4	0	0
T4	63593	6	0	0
T12	14030	130	0	0
T13	105090	1039	0	0
T14	338	2	0	0
T15	162771	1066	0	0
T16	29125	202	0	0
T17	74440	748	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1425784	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1425784	0	0
T1	93536	4311	0	0
T2	18662	687	0	0
T3	441	4	0	0
T4	63593	19	0	0
T12	14030	167	0	0
T13	105090	715	0	0
T14	338	6	0	0
T15	162771	2620	0	0
T16	29125	252	0	0
T17	74440	518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3549031	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3549031	0	0
T1	93536	3198	0	0
T2	18662	687	0	0
T3	441	4	0	0
T4	63593	4	0	0
T12	14030	167	0	0
T13	105090	854	0	0
T14	338	6	0	0
T15	162771	1196	0	0
T16	29125	174	0	0
T17	74440	659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1449066	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1449066	0	0
T1	93536	2149	0	0
T2	18662	452	0	0
T3	441	3	0	0
T4	63593	27	0	0
T12	14030	402	0	0
T13	105090	796	0	0
T14	338	2	0	0
T15	162771	1281	0	0
T16	29125	252	0	0
T17	74440	649	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3087836	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3087836	0	0
T1	93536	1887	0	0
T2	18662	452	0	0
T3	441	3	0	0
T4	63593	7	0	0
T12	14030	401	0	0
T13	105090	956	0	0
T14	338	2	0	0
T15	162771	689	0	0
T16	29125	201	0	0
T17	74440	641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1408318	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1408318	0	0
T1	93536	3909	0	0
T2	18662	193	0	0
T3	441	5	0	0
T4	63593	18	0	0
T12	14030	303	0	0
T13	105090	800	0	0
T14	338	8	0	0
T15	162771	2313	0	0
T16	29125	235	0	0
T17	74440	514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2500391	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2500391	0	0
T1	93536	3005	0	0
T2	18662	193	0	0
T3	441	5	0	0
T4	63593	3	0	0
T12	14030	302	0	0
T13	105090	835	0	0
T14	338	8	0	0
T15	162771	1904	0	0
T16	29125	198	0	0
T17	74440	548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1411674	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1411674	0	0
T2	18662	475	0	0
T3	441	6	0	0
T4	63593	35	0	0
T12	14030	179	0	0
T13	105090	1001	0	0
T14	338	6	0	0
T15	162771	953	0	0
T16	29125	284	0	0
T17	74440	551	0	0
T18	6643	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3224575	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3224575	0	0
T2	18662	475	0	0
T3	441	6	0	0
T4	63593	8	0	0
T12	14030	178	0	0
T13	105090	1179	0	0
T14	338	6	0	0
T15	162771	4	0	0
T16	29125	195	0	0
T17	74440	736	0	0
T18	6643	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1496244	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1496244	0	0
T1	93536	1894	0	0
T2	18662	713	0	0
T3	441	3	0	0
T4	63593	41	0	0
T12	14030	182	0	0
T13	105090	871	0	0
T14	338	6	0	0
T15	162771	4890	0	0
T16	29125	268	0	0
T17	74440	597	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3892652	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3892652	0	0
T1	93536	1486	0	0
T2	18662	713	0	0
T3	441	3	0	0
T4	63593	10	0	0
T12	14030	182	0	0
T13	105090	942	0	0
T14	338	6	0	0
T15	162771	1784	0	0
T16	29125	222	0	0
T17	74440	672	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1425161	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1425161	0	0
T1	93536	2115	0	0
T2	18662	181	0	0
T3	441	6	0	0
T4	63593	16	0	0
T12	14030	142	0	0
T13	105090	809	0	0
T14	338	1	0	0
T15	162771	1344	0	0
T16	29125	207	0	0
T17	74440	556	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	4122644	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	4122644	0	0
T1	93536	1544	0	0
T2	18662	181	0	0
T3	441	6	0	0
T4	63593	4	0	0
T12	14030	142	0	0
T13	105090	873	0	0
T14	338	1	0	0
T15	162771	1096	0	0
T16	29125	176	0	0
T17	74440	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1400429	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1400429	0	0
T2	18662	187	0	0
T3	441	4	0	0
T4	63593	5	0	0
T12	14030	370	0	0
T13	105090	934	0	0
T14	338	3	0	0
T15	162771	793	0	0
T16	29125	114	0	0
T17	74440	483	0	0
T18	6643	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3605828	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3605828	0	0
T2	18662	187	0	0
T3	441	4	0	0
T4	63593	3	0	0
T12	14030	370	0	0
T13	105090	1129	0	0
T14	338	3	0	0
T15	162771	3	0	0
T16	29125	111	0	0
T17	74440	624	0	0
T18	6643	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1434868	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1434868	0	0
T2	18662	197	0	0
T3	441	2	0	0
T4	63593	3	0	0
T12	14030	134	0	0
T13	105090	808	0	0
T14	338	6	0	0
T15	162771	3670	0	0
T16	29125	106	0	0
T17	74440	580	0	0
T18	6643	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2637010	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2637010	0	0
T2	18662	197	0	0
T3	441	2	0	0
T4	63593	1	0	0
T12	14030	133	0	0
T13	105090	770	0	0
T14	338	6	0	0
T15	162771	705	0	0
T16	29125	143	0	0
T17	74440	610	0	0
T18	6643	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1446646	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1446646	0	0
T1	93536	2437	0	0
T2	18662	224	0	0
T3	441	7	0	0
T4	63593	20	0	0
T12	14030	141	0	0
T13	105090	1009	0	0
T14	338	7	0	0
T15	162771	1387	0	0
T16	29125	142	0	0
T17	74440	511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3312004	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3312004	0	0
T1	93536	1884	0	0
T2	18662	224	0	0
T3	441	7	0	0
T4	63593	6	0	0
T12	14030	141	0	0
T13	105090	1121	0	0
T14	338	7	0	0
T15	162771	305	0	0
T16	29125	107	0	0
T17	74440	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1500865	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1500865	0	0
T2	18662	403	0	0
T3	441	2	0	0
T4	63593	23	0	0
T12	14030	261	0	0
T13	105090	1089	0	0
T14	338	3	0	0
T15	162771	1832	0	0
T16	29125	115	0	0
T17	74440	746	0	0
T18	6643	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3940855	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3940855	0	0
T2	18662	403	0	0
T3	441	2	0	0
T4	63593	10	0	0
T12	14030	260	0	0
T13	105090	1122	0	0
T14	338	3	0	0
T15	162771	896	0	0
T16	29125	95	0	0
T17	74440	650	0	0
T18	6643	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1406323	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1406323	0	0
T2	18662	418	0	0
T3	441	3	0	0
T4	63593	45	0	0
T12	14030	220	0	0
T13	105090	858	0	0
T14	338	2	0	0
T15	162771	1401	0	0
T16	29125	190	0	0
T17	74440	774	0	0
T18	6643	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3255298	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3255298	0	0
T2	18662	418	0	0
T3	441	3	0	0
T4	63593	7	0	0
T12	14030	220	0	0
T13	105090	997	0	0
T14	338	2	0	0
T15	162771	461	0	0
T16	29125	230	0	0
T17	74440	723	0	0
T18	6643	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1485609	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1485609	0	0
T1	93536	1457	0	0
T2	18662	187	0	0
T3	441	6	0	0
T4	63593	23	0	0
T12	14030	357	0	0
T13	105090	1023	0	0
T14	338	1	0	0
T15	162771	1712	0	0
T16	29125	126	0	0
T17	74440	597	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3588823	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3588823	0	0
T1	93536	1432	0	0
T2	18662	187	0	0
T3	441	6	0	0
T4	63593	4	0	0
T12	14030	357	0	0
T13	105090	951	0	0
T14	338	1	0	0
T15	162771	472	0	0
T16	29125	138	0	0
T17	74440	556	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1460074	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1460074	0	0
T2	18662	200	0	0
T3	441	1	0	0
T4	63593	1	0	0
T12	14030	129	0	0
T13	105090	887	0	0
T14	338	4	0	0
T15	162771	1558	0	0
T16	29125	183	0	0
T17	74440	514	0	0
T18	6643	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3210766	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3210766	0	0
T2	18662	200	0	0
T3	441	1	0	0
T4	63593	1	0	0
T12	14030	129	0	0
T13	105090	922	0	0
T14	338	4	0	0
T15	162771	1219	0	0
T16	29125	214	0	0
T17	74440	620	0	0
T18	6643	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1429340	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1429340	0	0
T1	93536	1788	0	0
T2	18662	480	0	0
T3	441	5	0	0
T4	63593	34	0	0
T12	14030	137	0	0
T13	105090	821	0	0
T14	338	4	0	0
T15	162771	272	0	0
T16	29125	199	0	0
T17	74440	576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3331551	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3331551	0	0
T1	93536	1322	0	0
T2	18662	480	0	0
T3	441	5	0	0
T4	63593	7	0	0
T12	14030	137	0	0
T13	105090	851	0	0
T14	338	4	0	0
T15	162771	226	0	0
T16	29125	192	0	0
T17	74440	607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1422792	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1422792	0	0
T2	18662	180	0	0
T3	441	11	0	0
T4	63593	5	0	0
T12	14030	148	0	0
T13	105090	1074	0	0
T14	338	1	0	0
T15	162771	225	0	0
T16	29125	216	0	0
T17	74440	521	0	0
T18	6643	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3913119	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3913119	0	0
T2	18662	180	0	0
T3	441	11	0	0
T4	63593	3	0	0
T12	14030	148	0	0
T13	105090	1064	0	0
T14	338	1	0	0
T15	162771	179	0	0
T16	29125	231	0	0
T17	74440	525	0	0
T18	6643	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1433683	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1433683	0	0
T2	18662	200	0	0
T3	441	2	0	0
T4	63593	21	0	0
T12	14030	287	0	0
T13	105090	1017	0	0
T14	338	0	0	0
T15	162771	2140	0	0
T16	29125	193	0	0
T17	74440	492	0	0
T18	6643	58	0	0
T19	0	342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3901998	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3901998	0	0
T2	18662	200	0	0
T3	441	2	0	0
T4	63593	5	0	0
T12	14030	287	0	0
T13	105090	945	0	0
T14	338	0	0	0
T15	162771	2028	0	0
T16	29125	289	0	0
T17	74440	482	0	0
T18	6643	58	0	0
T19	0	332	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1463008	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1463008	0	0
T2	18662	196	0	0
T3	441	5	0	0
T4	63593	11	0	0
T12	14030	430	0	0
T13	105090	1029	0	0
T14	338	6	0	0
T15	162771	1831	0	0
T16	29125	184	0	0
T17	74440	470	0	0
T18	6643	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3302986	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3302986	0	0
T2	18662	196	0	0
T3	441	5	0	0
T4	63593	4	0	0
T12	14030	430	0	0
T13	105090	1053	0	0
T14	338	6	0	0
T15	162771	418	0	0
T16	29125	123	0	0
T17	74440	523	0	0
T18	6643	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1397425	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1397425	0	0
T1	93536	4818	0	0
T2	18662	221	0	0
T3	441	2	0	0
T4	63593	6	0	0
T12	14030	133	0	0
T13	105090	866	0	0
T14	338	4	0	0
T15	162771	688	0	0
T16	29125	186	0	0
T17	74440	445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2760056	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2760056	0	0
T1	93536	3602	0	0
T2	18662	221	0	0
T3	441	2	0	0
T4	63593	2	0	0
T12	14030	133	0	0
T13	105090	780	0	0
T14	338	4	0	0
T15	162771	1	0	0
T16	29125	137	0	0
T17	74440	530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1482251	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1482251	0	0
T1	93536	1607	0	0
T2	18662	204	0	0
T3	441	2	0	0
T4	63593	11	0	0
T12	14030	471	0	0
T13	105090	959	0	0
T14	338	2	0	0
T15	162771	1704	0	0
T16	29125	279	0	0
T17	74440	645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3251884	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3251884	0	0
T1	93536	1499	0	0
T2	18662	204	0	0
T3	441	2	0	0
T4	63593	3	0	0
T12	14030	471	0	0
T13	105090	1016	0	0
T14	338	2	0	0
T15	162771	326	0	0
T16	29125	345	0	0
T17	74440	593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1457867	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1457867	0	0
T1	93536	5944	0	0
T2	18662	212	0	0
T3	441	7	0	0
T4	63593	10	0	0
T12	14030	145	0	0
T13	105090	780	0	0
T14	338	3	0	0
T15	162771	1592	0	0
T16	29125	186	0	0
T17	74440	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	4053701	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	4053701	0	0
T1	93536	4257	0	0
T2	18662	212	0	0
T3	441	7	0	0
T4	63593	2	0	0
T12	14030	143	0	0
T13	105090	884	0	0
T14	338	3	0	0
T15	162771	535	0	0
T16	29125	215	0	0
T17	74440	548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1459728	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1459728	0	0
T2	18662	200	0	0
T3	441	3	0	0
T4	63593	19	0	0
T12	14030	318	0	0
T13	105090	977	0	0
T14	338	5	0	0
T15	162771	1213	0	0
T16	29125	230	0	0
T17	74440	586	0	0
T18	6643	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2795874	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2795874	0	0
T2	18662	200	0	0
T3	441	3	0	0
T4	63593	6	0	0
T12	14030	317	0	0
T13	105090	963	0	0
T14	338	5	0	0
T15	162771	378	0	0
T16	29125	225	0	0
T17	74440	537	0	0
T18	6643	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1387369	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1387369	0	0
T2	18662	223	0	0
T3	441	2	0	0
T4	63593	31	0	0
T12	14030	123	0	0
T13	105090	904	0	0
T14	338	4	0	0
T15	162771	1602	0	0
T16	29125	306	0	0
T17	74440	535	0	0
T18	6643	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2763488	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2763488	0	0
T2	18662	223	0	0
T3	441	2	0	0
T4	63593	7	0	0
T12	14030	123	0	0
T13	105090	999	0	0
T14	338	4	0	0
T15	162771	1498	0	0
T16	29125	234	0	0
T17	74440	545	0	0
T18	6643	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1444931	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1444931	0	0
T1	93536	1722	0	0
T2	18662	672	0	0
T3	441	3	0	0
T4	63593	17	0	0
T12	14030	145	0	0
T13	105090	663	0	0
T14	338	4	0	0
T15	162771	832	0	0
T16	29125	169	0	0
T17	74440	484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	3157243	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	3157243	0	0
T1	93536	1360	0	0
T2	18662	671	0	0
T3	441	3	0	0
T4	63593	7	0	0
T12	14030	145	0	0
T13	105090	708	0	0
T14	338	4	0	0
T15	162771	657	0	0
T16	29125	168	0	0
T17	74440	458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	1401699	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	1401699	0	0
T1	93536	2309	0	0
T2	18662	407	0	0
T3	441	3	0	0
T4	63593	7	0	0
T12	14030	575	0	0
T13	105090	788	0	0
T14	338	3	0	0
T15	162771	2168	0	0
T16	29125	260	0	0
T17	74440	486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310392620	2498840	0	0
DepthKnown_A	310392620	310253437	0	0
RvalidKnown_A	310392620	310253437	0	0
WreadyKnown_A	310392620	310253437	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	2498840	0	0
T1	93536	1422	0	0
T2	18662	407	0	0
T3	441	3	0	0
T4	63593	1	0	0
T12	14030	574	0	0
T13	105090	803	0	0
T14	338	3	0	0
T15	162771	1117	0	0
T16	29125	210	0	0
T17	74440	403	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310392620	310253437	0	0
T1	93536	93500	0	0
T2	18662	17911	0	0
T3	441	416	0	0
T4	63593	63562	0	0
T12	14030	13437	0	0
T13	105090	105013	0	0
T14	338	318	0	0
T15	162771	162701	0	0
T16	29125	29099	0	0
T17	74440	74429	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0