Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1662850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262215

1

T1

15

T2

78

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	651166	1			T1	32		T2	222		T3	27
values[0x0]	622026	1			T1	36		T2	198		T3	6
values[0x1]	651873	1			T1	32		T2	199		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1288169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

636896

1

T1

35

T2

196

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7354	1			T2	2		T6	8		T15	5
valid_sources[0x01]	7222	1			T1	3		T2	5		T6	9
valid_sources[0x02]	7791	1			T6	9		T15	3		T16	3
valid_sources[0x03]	7575	1			T6	9		T15	1		T16	3
valid_sources[0x04]	8424	1			T2	1		T6	10		T15	3
valid_sources[0x05]	7946	1			T2	1		T3	1		T6	9
valid_sources[0x06]	7439	1			T6	9		T15	4		T16	3
valid_sources[0x07]	6935	1			T2	4		T6	11		T15	6
valid_sources[0x08]	6975	1			T1	1		T2	3		T6	9
valid_sources[0x09]	7502	1			T2	3		T6	8		T15	1
valid_sources[0x0a]	7404	1			T6	10		T15	1		T4	69
valid_sources[0x0b]	7441	1			T2	3		T6	10		T15	3
valid_sources[0x0c]	7497	1			T6	9		T15	2		T16	3
valid_sources[0x0d]	7516	1			T2	2		T6	8		T15	4
valid_sources[0x0e]	7059	1			T2	1		T6	9		T15	3
valid_sources[0x0f]	6973	1			T2	3		T6	9		T15	3
valid_sources[0x10]	6901	1			T1	1		T2	2		T3	1
valid_sources[0x11]	6728	1			T6	11		T15	5		T16	3
valid_sources[0x12]	8545	1			T2	4		T6	11		T15	3
valid_sources[0x13]	7786	1			T3	3		T6	8		T16	4
valid_sources[0x14]	7585	1			T2	2		T3	1		T6	8
valid_sources[0x15]	7034	1			T2	4		T6	11		T15	1
valid_sources[0x16]	7863	1			T2	1		T6	10		T15	2
valid_sources[0x17]	7509	1			T2	2		T6	9		T15	2
valid_sources[0x18]	7613	1			T2	2		T6	8		T15	3
valid_sources[0x19]	6969	1			T2	3		T6	10		T15	1
valid_sources[0x1a]	8450	1			T2	3		T3	1		T6	9
valid_sources[0x1b]	8740	1			T1	3		T2	3		T6	9
valid_sources[0x1c]	6996	1			T2	1		T6	8		T16	3
valid_sources[0x1d]	7901	1			T2	3		T6	9		T15	1
valid_sources[0x1e]	7698	1			T2	2		T3	1		T6	8
valid_sources[0x1f]	7053	1			T2	2		T6	9		T15	1
valid_sources[0x20]	8033	1			T2	2		T6	10		T15	3
valid_sources[0x21]	7496	1			T2	4		T6	9		T15	2
valid_sources[0x22]	7370	1			T6	9		T15	4		T16	3
valid_sources[0x23]	7310	1			T2	4		T6	10		T15	1
valid_sources[0x24]	7595	1			T1	3		T2	1		T6	10
valid_sources[0x25]	8232	1			T2	2		T6	8		T15	6
valid_sources[0x26]	7147	1			T2	2		T6	8		T15	2
valid_sources[0x27]	6637	1			T2	4		T6	9		T15	7
valid_sources[0x28]	8845	1			T2	2		T6	9		T15	1
valid_sources[0x29]	7382	1			T2	3		T6	9		T15	4
valid_sources[0x2a]	7946	1			T6	9		T15	4		T16	3
valid_sources[0x2b]	8609	1			T2	3		T3	4		T6	9
valid_sources[0x2c]	7233	1			T2	5		T6	8		T16	3
valid_sources[0x2d]	7616	1			T2	4		T6	10		T15	1
valid_sources[0x2e]	7349	1			T1	3		T2	5		T6	9
valid_sources[0x2f]	7770	1			T2	2		T3	1		T6	8
valid_sources[0x30]	7605	1			T2	1		T6	9		T15	4
valid_sources[0x31]	7789	1			T2	5		T6	10		T15	1
valid_sources[0x32]	7759	1			T1	3		T2	2		T6	9
valid_sources[0x33]	7171	1			T2	2		T6	9		T15	5
valid_sources[0x34]	7706	1			T2	4		T6	9		T15	2
valid_sources[0x35]	7819	1			T2	4		T6	9		T15	3
valid_sources[0x36]	6538	1			T2	4		T6	8		T15	2
valid_sources[0x37]	7688	1			T1	9		T2	4		T3	1
valid_sources[0x38]	7506	1			T2	2		T6	10		T15	6
valid_sources[0x39]	7951	1			T2	1		T6	8		T15	6
valid_sources[0x3a]	7479	1			T2	3		T6	8		T15	2
valid_sources[0x3b]	7369	1			T2	2		T3	2		T6	9
valid_sources[0x3c]	6432	1			T2	3		T6	9		T15	1
valid_sources[0x3d]	6820	1			T2	1		T6	8		T16	2
valid_sources[0x3e]	8396	1			T2	5		T6	9		T15	4
valid_sources[0x3f]	7409	1			T6	9		T15	2		T16	3
valid_sources[0x40]	7688	1			T2	1		T3	1		T6	9
valid_sources[0x41]	7128	1			T2	4		T6	11		T15	1
valid_sources[0x42]	6791	1			T2	3		T6	9		T15	4
valid_sources[0x43]	8447	1			T2	1		T6	10		T15	3
valid_sources[0x44]	7328	1			T1	2		T2	3		T6	9
valid_sources[0x45]	7084	1			T6	8		T15	6		T16	3
valid_sources[0x46]	8188	1			T6	8		T15	2		T16	3
valid_sources[0x47]	6917	1			T2	4		T6	9		T15	1
valid_sources[0x48]	7151	1			T6	9		T15	2		T16	3
valid_sources[0x49]	7624	1			T2	1		T6	10		T15	3
valid_sources[0x4a]	8982	1			T2	1		T6	11		T15	6
valid_sources[0x4b]	7016	1			T1	2		T6	9		T16	3
valid_sources[0x4c]	6988	1			T2	1		T6	9		T15	2
valid_sources[0x4d]	7459	1			T2	4		T6	9		T16	2
valid_sources[0x4e]	7681	1			T2	2		T6	9		T15	1
valid_sources[0x4f]	7145	1			T2	1		T3	1		T6	10
valid_sources[0x50]	7087	1			T2	4		T3	1		T6	9
valid_sources[0x51]	7417	1			T2	5		T6	10		T16	3
valid_sources[0x52]	7297	1			T2	1		T6	10		T15	3
valid_sources[0x53]	8186	1			T2	2		T6	8		T15	5
valid_sources[0x54]	6741	1			T2	3		T6	8		T15	4
valid_sources[0x55]	6884	1			T1	6		T2	3		T6	9
valid_sources[0x56]	7413	1			T2	1		T6	8		T15	2
valid_sources[0x57]	6961	1			T2	5		T6	10		T15	2
valid_sources[0x58]	7405	1			T2	4		T6	9		T15	2
valid_sources[0x59]	8107	1			T3	2		T6	9		T15	4
valid_sources[0x5a]	7041	1			T2	1		T6	10		T15	2
valid_sources[0x5b]	7505	1			T2	2		T6	8		T4	165
valid_sources[0x5c]	7237	1			T2	2		T6	8		T15	6
valid_sources[0x5d]	8012	1			T2	5		T6	9		T15	1
valid_sources[0x5e]	8113	1			T6	10		T15	4		T4	45
valid_sources[0x5f]	8174	1			T2	2		T6	9		T15	1
valid_sources[0x60]	6913	1			T2	2		T6	9		T15	3
valid_sources[0x61]	8259	1			T2	2		T6	9		T15	4
valid_sources[0x62]	7511	1			T2	2		T6	9		T15	5
valid_sources[0x63]	8477	1			T6	9		T15	3		T16	3
valid_sources[0x64]	7022	1			T2	2		T6	8		T15	3
valid_sources[0x65]	7139	1			T2	4		T6	9		T15	1
valid_sources[0x66]	8959	1			T1	2		T2	1		T6	11
valid_sources[0x67]	7607	1			T2	4		T3	1		T6	11
valid_sources[0x68]	7512	1			T6	9		T15	5		T16	2
valid_sources[0x69]	7319	1			T2	3		T6	9		T15	5
valid_sources[0x6a]	8176	1			T2	3		T6	8		T15	2
valid_sources[0x6b]	7369	1			T2	4		T6	8		T15	4
valid_sources[0x6c]	7629	1			T2	4		T6	9		T15	5
valid_sources[0x6d]	8112	1			T2	2		T6	10		T16	3
valid_sources[0x6e]	7174	1			T2	2		T6	10		T15	5
valid_sources[0x6f]	7702	1			T2	2		T6	9		T15	3
valid_sources[0x70]	6870	1			T1	6		T2	4		T6	10
valid_sources[0x71]	7400	1			T2	3		T3	1		T6	8
valid_sources[0x72]	7484	1			T2	3		T6	9		T15	1
valid_sources[0x73]	8072	1			T2	1		T6	10		T15	8
valid_sources[0x74]	7710	1			T2	2		T6	10		T15	7
valid_sources[0x75]	7054	1			T2	2		T6	9		T15	1
valid_sources[0x76]	7365	1			T2	3		T6	9		T15	5
valid_sources[0x77]	7207	1			T1	1		T2	8		T6	9
valid_sources[0x78]	7605	1			T2	3		T6	9		T16	3
valid_sources[0x79]	7141	1			T1	2		T2	5		T6	9
valid_sources[0x7a]	7737	1			T2	2		T6	9		T15	2
valid_sources[0x7b]	7919	1			T2	5		T6	10		T15	5
valid_sources[0x7c]	7375	1			T2	3		T6	8		T15	4
valid_sources[0x7d]	7533	1			T2	1		T6	8		T15	3
valid_sources[0x7e]	6420	1			T2	5		T6	9		T15	5
valid_sources[0x7f]	7434	1			T2	4		T6	9		T15	4
valid_sources[0x80]	7091	1			T2	1		T6	9		T15	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27654

1

T1

2

T2

8

T3

2

values[0x0]

all_enables

biggest_size

207078

1

T1

13

T2

58

T3

1

values[0x1]

all_enables

biggest_size

27483

1

T2

12

T3

1

T6

36