Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	338379922	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338379922	0	0
T1	6878682	181352	0	0
T2	33845448	1052754	0	0
T3	157248	5174	0	0
T4	337736	13937	0	0
T5	238168	8034	0	0
T6	12416656	1717988	0	0
T14	0	440600	0	0
T15	831208	23250	0	0
T16	36604736	560144	0	0
T17	44633008	592328	0	0
T18	2654512	56700	0	0
T19	291554	62852	0	0
T20	0	23885	0	0
T21	0	660284	0	0
T22	0	70756	0	0
T23	0	4694	0	0
T24	0	954	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7133448	7132104	0	0
T2	33845448	33842424	0	0
T3	157248	156408	0	0
T4	337736	332976	0	0
T5	238168	236880	0	0
T6	12416656	12416376	0	0
T15	831208	829472	0	0
T16	36604736	36601208	0	0
T17	44633008	44631720	0	0
T18	2654512	2651096	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7133448	7132104	0	0
T2	33845448	33842424	0	0
T3	157248	156408	0	0
T4	337736	332976	0	0
T5	238168	236880	0	0
T6	12416656	12416376	0	0
T15	831208	829472	0	0
T16	36604736	36601208	0	0
T17	44633008	44631720	0	0
T18	2654512	2651096	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7133448	7132104	0	0
T2	33845448	33842424	0	0
T3	157248	156408	0	0
T4	337736	332976	0	0
T5	238168	236880	0	0
T6	12416656	12416376	0	0
T15	831208	829472	0	0
T16	36604736	36601208	0	0
T17	44633008	44631720	0	0
T18	2654512	2651096	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	127751877	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	127751877	0	0
T1	127383	76853	0	0
T2	604383	597504	0	0
T3	2808	1434	0	0
T4	6031	5425	0	0
T5	4253	4008	0	0
T6	221726	10735	0	0
T15	14843	5546	0	0
T16	653656	3474	0	0
T17	797018	3597	0	0
T18	47402	18472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	83288774	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	83288774	0	0
T1	127383	34589	0	0
T2	604383	226567	0	0
T3	2808	1296	0	0
T4	6031	2838	0	0
T5	4253	2054	0	0
T6	221726	848259	0	0
T15	14843	6079	0	0
T16	653656	276598	0	0
T17	797018	292568	0	0
T18	47402	9879	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1644802	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1644802	0	0
T1	127383	2038	0	0
T2	604383	50	0	0
T3	2808	38	0	0
T4	6031	104	0	0
T5	4253	39	0	0
T6	221726	0	0	0
T14	0	9395	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	22	0	0
T20	0	2493	0	0
T21	0	287	0	0
T22	0	5768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2880265	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2880265	0	0
T1	127383	1047	0	0
T2	604383	5386	0	0
T3	2808	38	0	0
T4	6031	104	0	0
T5	4253	39	0	0
T6	221726	0	0	0
T14	0	8904	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	1903	0	0
T20	0	1707	0	0
T21	0	22841	0	0
T22	0	3908	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1683922	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1683922	0	0
T1	127383	2155	0	0
T2	604383	131	0	0
T3	2808	46	0	0
T4	6031	110	0	0
T5	4253	40	0	0
T6	221726	0	0	0
T14	0	12009	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1199	0	0
T19	0	34	0	0
T21	0	310	0	0
T22	0	3248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2814617	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2814617	0	0
T1	127383	3881	0	0
T2	604383	9231	0	0
T3	2808	46	0	0
T4	6031	110	0	0
T5	4253	40	0	0
T6	221726	0	0	0
T14	0	10041	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	914	0	0
T19	0	2376	0	0
T21	0	20200	0	0
T22	0	2771	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1737578	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1737578	0	0
T1	127383	522	0	0
T2	604383	128	0	0
T3	2808	54	0	0
T4	6031	108	0	0
T5	4253	36	0	0
T6	221726	0	0	0
T14	0	10033	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	11	0	0
T21	0	273	0	0
T22	0	2633	0	0
T23	0	2375	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3536256	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3536256	0	0
T1	127383	925	0	0
T2	604383	9665	0	0
T3	2808	54	0	0
T4	6031	108	0	0
T5	4253	36	0	0
T6	221726	0	0	0
T14	0	9139	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	215	0	0
T21	0	23742	0	0
T22	0	1531	0	0
T23	0	2319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1682065	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1682065	0	0
T1	127383	469	0	0
T2	604383	97	0	0
T3	2808	54	0	0
T4	6031	108	0	0
T5	4253	36	0	0
T6	221726	0	0	0
T14	0	9326	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	26	0	0
T21	0	309	0	0
T22	0	897	0	0
T24	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2755569	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2755569	0	0
T1	127383	1019	0	0
T2	604383	7843	0	0
T3	2808	54	0	0
T4	6031	108	0	0
T5	4253	36	0	0
T6	221726	0	0	0
T14	0	8395	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2609	0	0
T21	0	23872	0	0
T22	0	460	0	0
T24	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1640887	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1640887	0	0
T1	127383	1429	0	0
T2	604383	88	0	0
T3	2808	27	0	0
T4	6031	96	0	0
T5	4253	41	0	0
T6	221726	0	0	0
T14	0	9653	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1414	0	0
T19	0	30	0	0
T20	0	1704	0	0
T21	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2864157	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2864157	0	0
T1	127383	1890	0	0
T2	604383	8416	0	0
T3	2808	27	0	0
T4	6031	96	0	0
T5	4253	41	0	0
T6	221726	0	0	0
T14	0	8740	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	977	0	0
T19	0	1583	0	0
T20	0	1529	0	0
T21	0	18130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1708991	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1708991	0	0
T1	127383	2626	0	0
T2	604383	35	0	0
T3	2808	43	0	0
T4	6031	133	0	0
T5	4253	29	0	0
T6	221726	0	0	0
T14	0	9424	0	0
T15	14843	1522	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	16	0	0
T21	0	235	0	0
T22	0	867	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2690279	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2690279	0	0
T1	127383	3557	0	0
T2	604383	4653	0	0
T3	2808	43	0	0
T4	6031	133	0	0
T5	4253	29	0	0
T6	221726	0	0	0
T14	0	8423	0	0
T15	14843	1979	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2740	0	0
T21	0	21657	0	0
T22	0	539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1694748	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1694748	0	0
T1	127383	316	0	0
T2	604383	88	0	0
T3	2808	49	0	0
T4	6031	96	0	0
T5	4253	43	0	0
T6	221726	0	0	0
T14	0	11437	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	13	0	0
T21	0	314	0	0
T22	0	1061	0	0
T24	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3239440	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3239440	0	0
T1	127383	792	0	0
T2	604383	9435	0	0
T3	2808	49	0	0
T4	6031	96	0	0
T5	4253	43	0	0
T6	221726	0	0	0
T14	0	10496	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2431	0	0
T21	0	27188	0	0
T22	0	670	0	0
T24	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1644483	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1644483	0	0
T1	127383	1536	0	0
T2	604383	131	0	0
T3	2808	47	0	0
T4	6031	90	0	0
T5	4253	32	0	0
T6	221726	0	0	0
T14	0	8239	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	42	0	0
T20	0	1721	0	0
T21	0	223	0	0
T22	0	809	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2707074	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2707074	0	0
T1	127383	532	0	0
T2	604383	10903	0	0
T3	2808	47	0	0
T4	6031	90	0	0
T5	4253	32	0	0
T6	221726	0	0	0
T14	0	7553	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2752	0	0
T20	0	1371	0	0
T21	0	18380	0	0
T22	0	425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1591780	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1591780	0	0
T1	127383	466	0	0
T2	604383	108	0	0
T3	2808	50	0	0
T4	6031	104	0	0
T5	4253	32	0	0
T6	221726	0	0	0
T14	0	9189	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	43	0	0
T21	0	235	0	0
T22	0	5418	0	0
T24	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3123896	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3123896	0	0
T1	127383	83	0	0
T2	604383	8218	0	0
T3	2808	50	0	0
T4	6031	104	0	0
T5	4253	32	0	0
T6	221726	0	0	0
T14	0	8903	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	3370	0	0
T21	0	22537	0	0
T22	0	2573	0	0
T24	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1645676	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1645676	0	0
T1	127383	1048	0	0
T2	604383	124	0	0
T3	2808	46	0	0
T4	6031	116	0	0
T5	4253	33	0	0
T6	221726	0	0	0
T14	0	9413	0	0
T15	14843	2109	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	12	0	0
T21	0	307	0	0
T22	0	3324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2400157	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2400157	0	0
T1	127383	273	0	0
T2	604383	10551	0	0
T3	2808	46	0	0
T4	6031	116	0	0
T5	4253	33	0	0
T6	221726	0	0	0
T14	0	8671	0	0
T15	14843	2034	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	739	0	0
T21	0	23934	0	0
T22	0	1586	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1638238	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1638238	0	0
T1	127383	2710	0	0
T2	604383	154	0	0
T3	2808	41	0	0
T4	6031	89	0	0
T5	4253	33	0	0
T6	221726	0	0	0
T14	0	7529	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	4483	0	0
T19	0	26	0	0
T21	0	303	0	0
T22	0	3432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3028144	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3028144	0	0
T1	127383	2706	0	0
T2	604383	9597	0	0
T3	2808	41	0	0
T4	6031	89	0	0
T5	4253	33	0	0
T6	221726	0	0	0
T14	0	6986	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	2219	0	0
T19	0	1435	0	0
T21	0	28867	0	0
T22	0	1669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1672420	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1672420	0	0
T1	127383	1809	0	0
T2	604383	72	0	0
T3	2808	41	0	0
T4	6031	132	0	0
T5	4253	30	0	0
T6	221726	0	0	0
T14	0	5724	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	39	0	0
T21	0	258	0	0
T22	0	1008	0	0
T24	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2939700	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2939700	0	0
T1	127383	1197	0	0
T2	604383	9564	0	0
T3	2808	41	0	0
T4	6031	132	0	0
T5	4253	30	0	0
T6	221726	0	0	0
T14	0	5011	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	1946	0	0
T21	0	20480	0	0
T22	0	584	0	0
T24	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1645671	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1645671	0	0
T2	604383	81	0	0
T3	2808	48	0	0
T4	6031	112	0	0
T5	4253	35	0	0
T6	221726	1179	0	0
T14	0	5757	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	145777	27	0	0
T21	0	354	0	0
T22	0	844	0	0
T24	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2855699	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2855699	0	0
T2	604383	6814	0	0
T3	2808	48	0	0
T4	6031	112	0	0
T5	4253	35	0	0
T6	221726	93573	0	0
T14	0	5418	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	145777	1821	0	0
T21	0	26309	0	0
T22	0	486	0	0
T24	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1669378	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1669378	0	0
T1	127383	893	0	0
T2	604383	175	0	0
T3	2808	37	0	0
T4	6031	96	0	0
T5	4253	54	0	0
T6	221726	1014	0	0
T14	0	5338	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1723	0	0
T19	0	29	0	0
T21	0	372	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2144891	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2144891	0	0
T1	127383	636	0	0
T2	604383	13130	0	0
T3	2808	37	0	0
T4	6031	96	0	0
T5	4253	54	0	0
T6	221726	81831	0	0
T14	0	5002	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	785	0	0
T19	0	2261	0	0
T21	0	31821	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1618272	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1618272	0	0
T1	127383	779	0	0
T2	604383	95	0	0
T3	2808	46	0	0
T4	6031	116	0	0
T5	4253	29	0	0
T6	221726	2625	0	0
T14	0	6123	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	4074	0	0
T19	0	46	0	0
T21	0	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3198333	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3198333	0	0
T1	127383	981	0	0
T2	604383	6512	0	0
T3	2808	46	0	0
T4	6031	116	0	0
T5	4253	29	0	0
T6	221726	203640	0	0
T14	0	4898	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1948	0	0
T19	0	4429	0	0
T21	0	19963	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1679883	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1679883	0	0
T1	127383	821	0	0
T2	604383	91	0	0
T3	2808	45	0	0
T4	6031	109	0	0
T5	4253	35	0	0
T6	221726	0	0	0
T15	14843	0	0	0
T16	653656	1229	0	0
T17	797018	1130	0	0
T18	47402	1983	0	0
T19	0	28	0	0
T21	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3645770	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3645770	0	0
T1	127383	1483	0	0
T2	604383	6039	0	0
T3	2808	45	0	0
T4	6031	109	0	0
T5	4253	35	0	0
T6	221726	0	0	0
T15	14843	0	0	0
T16	653656	99816	0	0
T17	797018	89611	0	0
T18	47402	868	0	0
T19	0	2572	0	0
T21	0	21020	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1645242	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1645242	0	0
T1	127383	181	0	0
T2	604383	93	0	0
T3	2808	56	0	0
T4	6031	94	0	0
T5	4253	37	0	0
T6	221726	0	0	0
T14	0	13510	0	0
T15	14843	1915	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	15	0	0
T21	0	269	0	0
T22	0	3123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2779438	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2779438	0	0
T1	127383	761	0	0
T2	604383	7785	0	0
T3	2808	56	0	0
T4	6031	94	0	0
T5	4253	37	0	0
T6	221726	0	0	0
T14	0	11389	0	0
T15	14843	2066	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	1652	0	0
T21	0	25399	0	0
T22	0	1554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1642198	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1642198	0	0
T1	127383	1079	0	0
T2	604383	67	0	0
T3	2808	49	0	0
T4	6031	96	0	0
T5	4253	24	0	0
T6	221726	1229	0	0
T14	0	11300	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	2207	0	0
T19	0	81	0	0
T21	0	352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2931155	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2931155	0	0
T1	127383	1070	0	0
T2	604383	5732	0	0
T3	2808	49	0	0
T4	6031	96	0	0
T5	4253	24	0	0
T6	221726	94346	0	0
T14	0	10172	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1096	0	0
T19	0	4112	0	0
T21	0	26284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1695104	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1695104	0	0
T1	127383	2099	0	0
T2	604383	96	0	0
T3	2808	41	0	0
T4	6031	94	0	0
T5	4253	31	0	0
T6	221726	1215	0	0
T14	0	7390	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	17	0	0
T21	0	270	0	0
T22	0	2246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3290220	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3290220	0	0
T1	127383	1184	0	0
T2	604383	7465	0	0
T3	2808	41	0	0
T4	6031	94	0	0
T5	4253	31	0	0
T6	221726	95877	0	0
T14	0	6619	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2535	0	0
T21	0	29513	0	0
T22	0	1659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1701529	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1701529	0	0
T1	127383	614	0	0
T2	604383	135	0	0
T3	2808	49	0	0
T4	6031	104	0	0
T5	4253	47	0	0
T6	221726	0	0	0
T14	0	5838	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1388	0	0
T19	0	12	0	0
T20	0	1540	0	0
T21	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3237766	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3237766	0	0
T1	127383	120	0	0
T2	604383	8456	0	0
T3	2808	49	0	0
T4	6031	104	0	0
T5	4253	47	0	0
T6	221726	0	0	0
T14	0	5224	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	1071	0	0
T19	0	1944	0	0
T20	0	1800	0	0
T21	0	24525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1730981	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1730981	0	0
T1	127383	1145	0	0
T2	604383	109	0	0
T3	2808	36	0	0
T4	6031	107	0	0
T5	4253	43	0	0
T6	221726	0	0	0
T14	0	15860	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	1307	0	0
T18	47402	0	0	0
T19	0	31	0	0
T21	0	254	0	0
T22	0	1004	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2948089	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2948089	0	0
T1	127383	714	0	0
T2	604383	9391	0	0
T3	2808	36	0	0
T4	6031	107	0	0
T5	4253	43	0	0
T6	221726	0	0	0
T14	0	13179	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	105525	0	0
T18	47402	0	0	0
T19	0	1326	0	0
T21	0	23044	0	0
T22	0	572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1628779	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1628779	0	0
T1	127383	1489	0	0
T2	604383	123	0	0
T3	2808	39	0	0
T4	6031	116	0	0
T5	4253	35	0	0
T6	221726	2454	0	0
T14	0	8129	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	22	0	0
T21	0	319	0	0
T22	0	855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	2907838	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	2907838	0	0
T1	127383	1770	0	0
T2	604383	8905	0	0
T3	2808	39	0	0
T4	6031	116	0	0
T5	4253	35	0	0
T6	221726	192529	0	0
T14	0	7410	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	1396	0	0
T21	0	29307	0	0
T22	0	542	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1672134	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1672134	0	0
T1	127383	2619	0	0
T2	604383	103	0	0
T3	2808	51	0	0
T4	6031	106	0	0
T5	4253	34	0	0
T6	221726	0	0	0
T14	0	9845	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	29	0	0
T21	0	253	0	0
T22	0	2669	0	0
T24	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3540185	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3540185	0	0
T1	127383	3375	0	0
T2	604383	10147	0	0
T3	2808	51	0	0
T4	6031	106	0	0
T5	4253	34	0	0
T6	221726	0	0	0
T14	0	9111	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	3042	0	0
T21	0	22597	0	0
T22	0	1750	0	0
T24	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1693971	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1693971	0	0
T1	127383	782	0	0
T2	604383	83	0	0
T3	2808	46	0	0
T4	6031	97	0	0
T5	4253	40	0	0
T6	221726	0	0	0
T14	0	8989	0	0
T15	14843	0	0	0
T16	653656	1021	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	41	0	0
T21	0	264	0	0
T22	0	938	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3011830	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3011830	0	0
T1	127383	1520	0	0
T2	604383	7623	0	0
T3	2808	46	0	0
T4	6031	97	0	0
T5	4253	40	0	0
T6	221726	0	0	0
T14	0	7732	0	0
T15	14843	0	0	0
T16	653656	82551	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	3750	0	0
T21	0	20725	0	0
T22	0	521	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1688514	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1688514	0	0
T1	127383	2788	0	0
T2	604383	75	0	0
T3	2808	45	0	0
T4	6031	106	0	0
T5	4253	41	0	0
T6	221726	1019	0	0
T14	0	7419	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	21	0	0
T20	0	3271	0	0
T21	0	343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3934510	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3934510	0	0
T1	127383	639	0	0
T2	604383	7896	0	0
T3	2808	45	0	0
T4	6031	106	0	0
T5	4253	41	0	0
T6	221726	86463	0	0
T14	0	7018	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	2661	0	0
T20	0	3564	0	0
T21	0	32659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1679716	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1679716	0	0
T1	127383	1553	0	0
T2	604383	100	0	0
T3	2808	45	0	0
T4	6031	108	0	0
T5	4253	38	0	0
T6	221726	0	0	0
T14	0	7364	0	0
T15	14843	0	0	0
T16	653656	1224	0	0
T17	797018	1159	0	0
T18	47402	0	0	0
T19	0	45	0	0
T21	0	255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3303070	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3303070	0	0
T1	127383	1202	0	0
T2	604383	8131	0	0
T3	2808	45	0	0
T4	6031	108	0	0
T5	4253	38	0	0
T6	221726	0	0	0
T14	0	6779	0	0
T15	14843	0	0	0
T16	653656	94231	0	0
T17	797018	97431	0	0
T18	47402	0	0	0
T19	0	3120	0	0
T21	0	23113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	1674566	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	1674566	0	0
T1	127383	1355	0	0
T2	604383	82	0	0
T3	2808	53	0	0
T4	6031	90	0	0
T5	4253	39	0	0
T6	221726	0	0	0
T14	0	8215	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	25	0	0
T20	0	1670	0	0
T21	0	255	0	0
T22	0	4663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309350413	3579395	0	0
DepthKnown_A	309350413	309231880	0	0
RvalidKnown_A	309350413	309231880	0	0
WreadyKnown_A	309350413	309231880	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	3579395	0	0
T1	127383	1232	0	0
T2	604383	8481	0	0
T3	2808	53	0	0
T4	6031	90	0	0
T5	4253	39	0	0
T6	221726	0	0	0
T14	0	6939	0	0
T15	14843	0	0	0
T16	653656	0	0	0
T17	797018	0	0	0
T18	47402	0	0	0
T19	0	1349	0	0
T20	0	1515	0	0
T21	0	24426	0	0
T22	0	2149	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309350413	309231880	0	0
T1	127383	127359	0	0
T2	604383	604329	0	0
T3	2808	2793	0	0
T4	6031	5946	0	0
T5	4253	4230	0	0
T6	221726	221721	0	0
T15	14843	14812	0	0
T16	653656	653593	0	0
T17	797018	796995	0	0
T18	47402	47341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0