Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1579393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248366

1

T1

189

T2

38

T3

118

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619231	1			T1	452		T2	100		T3	479
values[0x0]	590276	1			T1	446		T2	96		T3	90
values[0x1]	618252	1			T1	457		T2	90		T3	503

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1223550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

604209

1

T1

476

T2

93

T3

415

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6873	1			T2	2		T4	2		T14	10
valid_sources[0x01]	6482	1			T2	3		T3	5		T4	5
valid_sources[0x02]	6948	1			T3	2		T4	7		T14	5
valid_sources[0x03]	7982	1			T3	5		T4	6		T14	9
valid_sources[0x04]	8727	1			T1	12		T3	7		T4	4
valid_sources[0x05]	6596	1			T2	1		T3	5		T4	1
valid_sources[0x06]	7282	1			T1	12		T2	2		T3	5
valid_sources[0x07]	6447	1			T2	1		T3	3		T4	4
valid_sources[0x08]	7081	1			T1	6		T2	1		T3	4
valid_sources[0x09]	7506	1			T2	1		T3	3		T4	11
valid_sources[0x0a]	6480	1			T1	20		T2	3		T3	8
valid_sources[0x0b]	7488	1			T1	19		T3	4		T13	2
valid_sources[0x0c]	6595	1			T2	2		T3	2		T4	4
valid_sources[0x0d]	6873	1			T1	19		T2	2		T3	10
valid_sources[0x0e]	7280	1			T2	2		T3	6		T4	3
valid_sources[0x0f]	7045	1			T2	1		T3	10		T13	1
valid_sources[0x10]	8392	1			T1	9		T2	2		T3	2
valid_sources[0x11]	6394	1			T1	11		T2	2		T3	3
valid_sources[0x12]	6145	1			T2	1		T3	7		T4	4
valid_sources[0x13]	6860	1			T2	2		T3	6		T4	8
valid_sources[0x14]	6829	1			T1	17		T2	2		T3	4
valid_sources[0x15]	7431	1			T2	1		T3	3		T14	8
valid_sources[0x16]	8054	1			T2	3		T3	5		T4	4
valid_sources[0x17]	6789	1			T2	5		T14	8		T16	8
valid_sources[0x18]	6592	1			T1	19		T3	3		T4	4
valid_sources[0x19]	6348	1			T2	2		T3	3		T4	2
valid_sources[0x1a]	6951	1			T2	3		T3	5		T14	11
valid_sources[0x1b]	6594	1			T1	18		T3	5		T4	2
valid_sources[0x1c]	6943	1			T1	6		T2	1		T3	5
valid_sources[0x1d]	6533	1			T2	1		T3	1		T4	1
valid_sources[0x1e]	6586	1			T1	16		T2	2		T3	9
valid_sources[0x1f]	8118	1			T3	6		T14	6		T16	10
valid_sources[0x20]	6934	1			T3	1		T4	1		T14	15
valid_sources[0x21]	7442	1			T2	1		T3	2		T4	7
valid_sources[0x22]	7028	1			T2	1		T3	10		T13	1
valid_sources[0x23]	9346	1			T1	10		T2	3		T3	3
valid_sources[0x24]	6953	1			T2	2		T3	3		T14	13
valid_sources[0x25]	6630	1			T3	4		T14	10		T16	10
valid_sources[0x26]	8094	1			T2	1		T3	6		T4	1
valid_sources[0x27]	6509	1			T1	8		T3	3		T13	1
valid_sources[0x28]	7898	1			T1	14		T2	1		T3	6
valid_sources[0x29]	7338	1			T1	14		T2	1		T3	4
valid_sources[0x2a]	7374	1			T2	2		T3	4		T4	6
valid_sources[0x2b]	6597	1			T3	2		T4	1		T14	13
valid_sources[0x2c]	6220	1			T2	1		T3	4		T14	4
valid_sources[0x2d]	6420	1			T2	1		T3	3		T13	2
valid_sources[0x2e]	6622	1			T2	1		T3	5		T13	2
valid_sources[0x2f]	6780	1			T3	5		T4	12		T14	13
valid_sources[0x30]	6669	1			T1	9		T3	2		T4	5
valid_sources[0x31]	6814	1			T1	18		T3	8		T14	7
valid_sources[0x32]	6913	1			T1	17		T2	2		T3	5
valid_sources[0x33]	6920	1			T1	8		T2	2		T3	6
valid_sources[0x34]	7482	1			T2	1		T3	1		T13	2
valid_sources[0x35]	6928	1			T2	1		T3	5		T13	1
valid_sources[0x36]	9216	1			T1	12		T2	1		T3	5
valid_sources[0x37]	6502	1			T3	8		T4	1		T14	8
valid_sources[0x38]	6868	1			T3	3		T14	8		T16	7
valid_sources[0x39]	6557	1			T3	7		T4	18		T14	12
valid_sources[0x3a]	6880	1			T2	2		T3	4		T4	7
valid_sources[0x3b]	6465	1			T2	3		T3	2		T4	8
valid_sources[0x3c]	7111	1			T1	34		T2	2		T3	7
valid_sources[0x3d]	7430	1			T3	10		T4	7		T13	1
valid_sources[0x3e]	6935	1			T1	67		T3	1		T14	5
valid_sources[0x3f]	6254	1			T1	7		T3	3		T14	11
valid_sources[0x40]	6374	1			T1	22		T2	2		T3	4
valid_sources[0x41]	7722	1			T3	1		T13	1		T14	8
valid_sources[0x42]	7258	1			T2	1		T3	3		T4	3
valid_sources[0x43]	7855	1			T3	3		T13	1		T14	7
valid_sources[0x44]	8200	1			T2	1		T3	2		T13	1
valid_sources[0x45]	6752	1			T1	8		T2	2		T3	10
valid_sources[0x46]	7315	1			T3	3		T4	3		T14	14
valid_sources[0x47]	8905	1			T2	2		T3	7		T4	2
valid_sources[0x48]	6826	1			T1	6		T3	6		T4	2
valid_sources[0x49]	7034	1			T2	4		T3	4		T4	1
valid_sources[0x4a]	6747	1			T2	2		T3	5		T4	13
valid_sources[0x4b]	7167	1			T2	1		T3	6		T14	8
valid_sources[0x4c]	7538	1			T1	8		T2	4		T3	7
valid_sources[0x4d]	6641	1			T3	2		T4	1		T13	2
valid_sources[0x4e]	6706	1			T1	6		T3	4		T13	1
valid_sources[0x4f]	7714	1			T3	3		T13	1		T14	10
valid_sources[0x50]	6507	1			T2	1		T3	4		T14	9
valid_sources[0x51]	6230	1			T1	28		T2	2		T3	2
valid_sources[0x52]	7197	1			T1	4		T2	2		T3	2
valid_sources[0x53]	7083	1			T2	1		T3	2		T14	9
valid_sources[0x54]	6409	1			T1	9		T3	1		T4	7
valid_sources[0x55]	6535	1			T1	15		T2	1		T3	7
valid_sources[0x56]	6795	1			T2	5		T3	5		T14	11
valid_sources[0x57]	7623	1			T2	4		T3	1		T4	11
valid_sources[0x58]	7453	1			T3	7		T4	4		T14	9
valid_sources[0x59]	6487	1			T3	4		T4	7		T14	7
valid_sources[0x5a]	7270	1			T1	7		T3	3		T4	3
valid_sources[0x5b]	6799	1			T2	1		T3	6		T4	2
valid_sources[0x5c]	9691	1			T1	5		T3	4		T14	12
valid_sources[0x5d]	7603	1			T3	2		T4	1		T14	5
valid_sources[0x5e]	7037	1			T1	6		T2	1		T3	1
valid_sources[0x5f]	7500	1			T2	1		T3	5		T14	6
valid_sources[0x60]	8058	1			T3	2		T4	2		T14	14
valid_sources[0x61]	6454	1			T1	19		T3	7		T4	5
valid_sources[0x62]	8987	1			T1	12		T2	3		T3	3
valid_sources[0x63]	6361	1			T3	6		T13	1		T14	7
valid_sources[0x64]	7736	1			T1	7		T2	1		T3	6
valid_sources[0x65]	7157	1			T1	15		T3	8		T4	13
valid_sources[0x66]	6624	1			T1	5		T3	4		T4	1
valid_sources[0x67]	6911	1			T2	2		T3	4		T4	1
valid_sources[0x68]	8875	1			T1	45		T2	3		T3	7
valid_sources[0x69]	6798	1			T3	3		T14	5		T16	10
valid_sources[0x6a]	6157	1			T2	2		T3	3		T14	7
valid_sources[0x6b]	7314	1			T2	1		T3	3		T4	5
valid_sources[0x6c]	6868	1			T2	1		T3	3		T4	2
valid_sources[0x6d]	7005	1			T3	2		T13	1		T14	11
valid_sources[0x6e]	7210	1			T3	3		T4	5		T14	9
valid_sources[0x6f]	6616	1			T1	14		T3	7		T4	2
valid_sources[0x70]	6712	1			T1	5		T2	2		T3	7
valid_sources[0x71]	6595	1			T2	4		T3	3		T4	1
valid_sources[0x72]	6630	1			T3	5		T4	7		T14	6
valid_sources[0x73]	7717	1			T2	1		T3	5		T4	3
valid_sources[0x74]	7236	1			T2	1		T3	3		T14	8
valid_sources[0x75]	7235	1			T2	1		T3	4		T4	3
valid_sources[0x76]	7598	1			T3	1		T4	3		T14	8
valid_sources[0x77]	7538	1			T2	1		T3	9		T4	11
valid_sources[0x78]	6550	1			T2	1		T3	3		T4	2
valid_sources[0x79]	6901	1			T1	35		T2	3		T3	5
valid_sources[0x7a]	7311	1			T2	1		T3	6		T4	10
valid_sources[0x7b]	9510	1			T2	1		T3	2		T14	10
valid_sources[0x7c]	7405	1			T1	15		T2	1		T3	4
valid_sources[0x7d]	6798	1			T1	17		T2	1		T3	7
valid_sources[0x7e]	6559	1			T2	1		T3	3		T14	12
valid_sources[0x7f]	6771	1			T1	12		T2	2		T3	7
valid_sources[0x80]	8224	1			T1	13		T3	3		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26027

1

T1

26

T2

2

T3

38

values[0x0]

all_enables

biggest_size

195759

1

T1

143

T2

33

T3

40

values[0x1]

all_enables

biggest_size

26580

1

T1

20

T2

3

T3

40