Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	345185554	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345185554	0	0
T1	2877056	42256	0	0
T2	14372624	461809	0	0
T3	34507536	857883	0	0
T4	111888	3227	0	0
T13	1643376	24904	0	0
T14	12664568	1379093	0	0
T15	0	4473	0	0
T16	2937088	68415	0	0
T17	14666624	1194321	0	0
T18	227864	9665	0	0
T19	596344	22645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2877056	2873472	0	0
T2	14372624	14370832	0	0
T3	34507536	34451312	0	0
T4	111888	108584	0	0
T13	1643376	1639512	0	0
T14	12664568	12664064	0	0
T16	2937088	2934960	0	0
T17	14666624	14666176	0	0
T18	227864	225400	0	0
T19	596344	594048	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2877056	2873472	0	0
T2	14372624	14370832	0	0
T3	34507536	34451312	0	0
T4	111888	108584	0	0
T13	1643376	1639512	0	0
T14	12664568	12664064	0	0
T16	2937088	2934960	0	0
T17	14666624	14666176	0	0
T18	227864	225400	0	0
T19	596344	594048	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2877056	2873472	0	0
T2	14372624	14370832	0	0
T3	34507536	34451312	0	0
T4	111888	108584	0	0
T13	1643376	1639512	0	0
T14	12664568	12664064	0	0
T16	2937088	2934960	0	0
T17	14666624	14666176	0	0
T18	227864	225400	0	0
T19	596344	594048	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	132823341	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	132823341	0	0
T1	51376	10317	0	0
T2	256654	253044	0	0
T3	616206	330278	0	0
T4	1998	1587	0	0
T13	29346	11390	0	0
T14	226153	111228	0	0
T16	52448	26179	0	0
T17	261904	13460	0	0
T18	4069	3749	0	0
T19	10649	9882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	84490578	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	84490578	0	0
T1	51376	10818	0	0
T2	256654	103729	0	0
T3	616206	193794	0	0
T4	1998	812	0	0
T13	29346	3791	0	0
T14	226153	264499	0	0
T16	52448	22024	0	0
T17	261904	106127	0	0
T18	4069	1972	0	0
T19	10649	5277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1646728	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1646728	0	0
T1	51376	360	0	0
T2	256654	47	0	0
T3	616206	9210	0	0
T4	1998	15	0	0
T13	29346	262	0	0
T14	226153	27536	0	0
T15	0	68	0	0
T16	52448	300	0	0
T17	261904	0	0	0
T18	4069	72	0	0
T19	10649	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2416579	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2416579	0	0
T1	51376	310	0	0
T2	256654	4584	0	0
T3	616206	8951	0	0
T4	1998	15	0	0
T13	29346	124	0	0
T14	226153	11277	0	0
T15	0	68	0	0
T16	52448	299	0	0
T17	261904	0	0	0
T18	4069	72	0	0
T19	10649	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1608984	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1608984	0	0
T1	51376	419	0	0
T2	256654	34	0	0
T3	616206	6739	0	0
T4	1998	11	0	0
T13	29346	174	0	0
T14	226153	28858	0	0
T15	0	54	0	0
T16	52448	274	0	0
T17	261904	0	0	0
T18	4069	70	0	0
T19	10649	377	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3406290	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3406290	0	0
T1	51376	468	0	0
T2	256654	2350	0	0
T3	616206	7011	0	0
T4	1998	11	0	0
T13	29346	98	0	0
T14	226153	7148	0	0
T15	0	54	0	0
T16	52448	278	0	0
T17	261904	0	0	0
T18	4069	70	0	0
T19	10649	377	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1646241	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1646241	0	0
T1	51376	342	0	0
T2	256654	69	0	0
T3	616206	7923	0	0
T4	1998	25	0	0
T13	29346	269	0	0
T14	226153	26182	0	0
T16	52448	336	0	0
T17	261904	1283	0	0
T18	4069	61	0	0
T19	10649	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2948959	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2948959	0	0
T1	51376	375	0	0
T2	256654	5837	0	0
T3	616206	7979	0	0
T4	1998	25	0	0
T13	29346	100	0	0
T14	226153	9140	0	0
T16	52448	366	0	0
T17	261904	104139	0	0
T18	4069	61	0	0
T19	10649	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1699087	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1699087	0	0
T1	51376	511	0	0
T2	256654	31	0	0
T3	616206	5257	0	0
T4	1998	18	0	0
T13	29346	361	0	0
T14	226153	37722	0	0
T15	0	67	0	0
T16	52448	367	0	0
T17	261904	0	0	0
T18	4069	78	0	0
T19	10649	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2646986	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2646986	0	0
T1	51376	483	0	0
T2	256654	2444	0	0
T3	616206	5945	0	0
T4	1998	18	0	0
T13	29346	170	0	0
T14	226153	12272	0	0
T15	0	67	0	0
T16	52448	428	0	0
T17	261904	0	0	0
T18	4069	78	0	0
T19	10649	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1676200	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1676200	0	0
T1	51376	282	0	0
T2	256654	63	0	0
T3	616206	3522	0	0
T4	1998	23	0	0
T13	29346	290	0	0
T14	226153	24634	0	0
T15	0	54	0	0
T16	52448	626	0	0
T17	261904	0	0	0
T18	4069	77	0	0
T19	10649	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2715547	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2715547	0	0
T1	51376	419	0	0
T2	256654	4741	0	0
T3	616206	3754	0	0
T4	1998	23	0	0
T13	29346	111	0	0
T14	226153	12609	0	0
T15	0	54	0	0
T16	52448	590	0	0
T17	261904	0	0	0
T18	4069	77	0	0
T19	10649	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1598354	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1598354	0	0
T1	51376	348	0	0
T2	256654	29	0	0
T3	616206	5043	0	0
T4	1998	16	0	0
T13	29346	201	0	0
T14	226153	29230	0	0
T16	52448	347	0	0
T17	261904	1240	0	0
T18	4069	84	0	0
T19	10649	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3975910	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3975910	0	0
T1	51376	369	0	0
T2	256654	2312	0	0
T3	616206	5286	0	0
T4	1998	16	0	0
T13	29346	79	0	0
T14	226153	14976	0	0
T16	52448	241	0	0
T17	261904	97636	0	0
T18	4069	84	0	0
T19	10649	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1689058	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1689058	0	0
T1	51376	430	0	0
T2	256654	32	0	0
T3	616206	5016	0	0
T4	1998	20	0	0
T13	29346	213	0	0
T14	226153	30312	0	0
T16	52448	426	0	0
T17	261904	1058	0	0
T18	4069	75	0	0
T19	10649	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3354002	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3354002	0	0
T1	51376	440	0	0
T2	256654	4253	0	0
T3	616206	5952	0	0
T4	1998	20	0	0
T13	29346	120	0	0
T14	226153	10746	0	0
T16	52448	343	0	0
T17	261904	86121	0	0
T18	4069	75	0	0
T19	10649	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1693313	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1693313	0	0
T1	51376	354	0	0
T2	256654	27	0	0
T3	616206	2975	0	0
T4	1998	12	0	0
T13	29346	164	0	0
T14	226153	27224	0	0
T16	52448	340	0	0
T17	261904	1285	0	0
T18	4069	71	0	0
T19	10649	120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2743324	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2743324	0	0
T1	51376	462	0	0
T2	256654	3015	0	0
T3	616206	2995	0	0
T4	1998	12	0	0
T13	29346	91	0	0
T14	226153	11037	0	0
T16	52448	355	0	0
T17	261904	101281	0	0
T18	4069	71	0	0
T19	10649	120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1651357	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1651357	0	0
T1	51376	346	0	0
T2	256654	37	0	0
T3	616206	6129	0	0
T4	1998	12	0	0
T13	29346	364	0	0
T14	226153	26127	0	0
T15	0	45	0	0
T16	52448	394	0	0
T17	261904	0	0	0
T18	4069	70	0	0
T19	10649	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3094776	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3094776	0	0
T1	51376	300	0	0
T2	256654	3192	0	0
T3	616206	6265	0	0
T4	1998	12	0	0
T13	29346	124	0	0
T14	226153	6858	0	0
T15	0	45	0	0
T16	52448	287	0	0
T17	261904	0	0	0
T18	4069	70	0	0
T19	10649	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1650397	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1650397	0	0
T1	51376	360	0	0
T2	256654	86	0	0
T3	616206	4642	0	0
T4	1998	15	0	0
T13	29346	216	0	0
T14	226153	23371	0	0
T15	0	54	0	0
T16	52448	432	0	0
T17	261904	0	0	0
T18	4069	78	0	0
T19	10649	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3162853	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3162853	0	0
T1	51376	346	0	0
T2	256654	6966	0	0
T3	616206	5197	0	0
T4	1998	15	0	0
T13	29346	107	0	0
T14	226153	7526	0	0
T15	0	54	0	0
T16	52448	376	0	0
T17	261904	0	0	0
T18	4069	78	0	0
T19	10649	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1659708	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1659708	0	0
T1	51376	456	0	0
T2	256654	47	0	0
T3	616206	3332	0	0
T4	1998	16	0	0
T13	29346	218	0	0
T14	226153	23660	0	0
T16	52448	370	0	0
T17	261904	1271	0	0
T18	4069	78	0	0
T19	10649	336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2976010	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2976010	0	0
T1	51376	453	0	0
T2	256654	2984	0	0
T3	616206	3553	0	0
T4	1998	16	0	0
T13	29346	92	0	0
T14	226153	9216	0	0
T16	52448	360	0	0
T17	261904	96036	0	0
T18	4069	78	0	0
T19	10649	336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1572924	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1572924	0	0
T1	51376	456	0	0
T2	256654	62	0	0
T3	616206	9234	0	0
T4	1998	14	0	0
T13	29346	194	0	0
T14	226153	28732	0	0
T15	0	317	0	0
T16	52448	402	0	0
T17	261904	0	0	0
T18	4069	75	0	0
T19	10649	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2407141	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2407141	0	0
T1	51376	526	0	0
T2	256654	4197	0	0
T3	616206	9947	0	0
T4	1998	14	0	0
T13	29346	119	0	0
T14	226153	8827	0	0
T15	0	317	0	0
T16	52448	368	0	0
T17	261904	0	0	0
T18	4069	75	0	0
T19	10649	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1603329	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1603329	0	0
T1	51376	448	0	0
T2	256654	30	0	0
T3	616206	7483	0	0
T4	1998	15	0	0
T13	29346	264	0	0
T14	226153	23858	0	0
T16	52448	362	0	0
T17	261904	1120	0	0
T18	4069	73	0	0
T19	10649	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3415695	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3415695	0	0
T1	51376	451	0	0
T2	256654	2383	0	0
T3	616206	7340	0	0
T4	1998	15	0	0
T13	29346	92	0	0
T14	226153	9972	0	0
T16	52448	424	0	0
T17	261904	92606	0	0
T18	4069	73	0	0
T19	10649	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1561539	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1561539	0	0
T1	51376	304	0	0
T2	256654	73	0	0
T3	616206	8629	0	0
T4	1998	15	0	0
T13	29346	150	0	0
T14	226153	29508	0	0
T15	0	68	0	0
T16	52448	381	0	0
T17	261904	0	0	0
T18	4069	68	0	0
T19	10649	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2772511	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2772511	0	0
T1	51376	350	0	0
T2	256654	5834	0	0
T3	616206	8956	0	0
T4	1998	15	0	0
T13	29346	66	0	0
T14	226153	7576	0	0
T15	0	68	0	0
T16	52448	308	0	0
T17	261904	0	0	0
T18	4069	68	0	0
T19	10649	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1622481	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1622481	0	0
T1	51376	275	0	0
T2	256654	43	0	0
T3	616206	6546	0	0
T4	1998	11	0	0
T13	29346	220	0	0
T14	226153	21577	0	0
T15	0	469	0	0
T16	52448	362	0	0
T17	261904	0	0	0
T18	4069	64	0	0
T19	10649	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2810760	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2810760	0	0
T1	51376	365	0	0
T2	256654	4507	0	0
T3	616206	7082	0	0
T4	1998	11	0	0
T13	29346	96	0	0
T14	226153	9185	0	0
T15	0	469	0	0
T16	52448	403	0	0
T17	261904	0	0	0
T18	4069	64	0	0
T19	10649	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1655683	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1655683	0	0
T1	51376	381	0	0
T2	256654	110	0	0
T3	616206	5251	0	0
T4	1998	13	0	0
T13	29346	237	0	0
T14	226153	30177	0	0
T15	0	63	0	0
T16	52448	390	0	0
T17	261904	0	0	0
T18	4069	61	0	0
T19	10649	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2749647	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2749647	0	0
T1	51376	475	0	0
T2	256654	5311	0	0
T3	616206	5255	0	0
T4	1998	13	0	0
T13	29346	111	0	0
T14	226153	13830	0	0
T15	0	63	0	0
T16	52448	335	0	0
T17	261904	0	0	0
T18	4069	61	0	0
T19	10649	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1684493	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1684493	0	0
T1	51376	278	0	0
T2	256654	23	0	0
T3	616206	5340	0	0
T4	1998	19	0	0
T13	29346	310	0	0
T14	226153	27540	0	0
T15	0	114	0	0
T16	52448	295	0	0
T17	261904	0	0	0
T18	4069	95	0	0
T19	10649	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3309179	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3309179	0	0
T1	51376	258	0	0
T2	256654	2480	0	0
T3	616206	5431	0	0
T4	1998	19	0	0
T13	29346	143	0	0
T14	226153	6535	0	0
T15	0	113	0	0
T16	52448	377	0	0
T17	261904	0	0	0
T18	4069	95	0	0
T19	10649	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1603428	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1603428	0	0
T1	51376	356	0	0
T2	256654	32	0	0
T3	616206	7268	0	0
T4	1998	13	0	0
T13	29346	274	0	0
T14	226153	24862	0	0
T15	0	53	0	0
T16	52448	411	0	0
T17	261904	0	0	0
T18	4069	65	0	0
T19	10649	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3214630	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3214630	0	0
T1	51376	383	0	0
T2	256654	1043	0	0
T3	616206	7770	0	0
T4	1998	13	0	0
T13	29346	99	0	0
T14	226153	9149	0	0
T15	0	53	0	0
T16	52448	351	0	0
T17	261904	0	0	0
T18	4069	65	0	0
T19	10649	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1646278	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1646278	0	0
T1	51376	438	0	0
T2	256654	55	0	0
T3	616206	6733	0	0
T4	1998	13	0	0
T13	29346	230	0	0
T14	226153	29363	0	0
T15	0	60	0	0
T16	52448	458	0	0
T17	261904	0	0	0
T18	4069	72	0	0
T19	10649	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3982632	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3982632	0	0
T1	51376	461	0	0
T2	256654	3669	0	0
T3	616206	7054	0	0
T4	1998	13	0	0
T13	29346	141	0	0
T14	226153	8963	0	0
T15	0	60	0	0
T16	52448	385	0	0
T17	261904	0	0	0
T18	4069	72	0	0
T19	10649	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1596960	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1596960	0	0
T1	51376	472	0	0
T2	256654	82	0	0
T3	616206	4955	0	0
T4	1998	15	0	0
T13	29346	256	0	0
T14	226153	27128	0	0
T16	52448	439	0	0
T17	261904	2577	0	0
T18	4069	85	0	0
T19	10649	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3236998	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3236998	0	0
T1	51376	403	0	0
T2	256654	4189	0	0
T3	616206	5151	0	0
T4	1998	15	0	0
T13	29346	60	0	0
T14	226153	10279	0	0
T16	52448	380	0	0
T17	261904	204935	0	0
T18	4069	85	0	0
T19	10649	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1673562	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1673562	0	0
T1	51376	438	0	0
T2	256654	47	0	0
T3	616206	9299	0	0
T4	1998	25	0	0
T13	29346	267	0	0
T14	226153	29669	0	0
T16	52448	367	0	0
T17	261904	974	0	0
T18	4069	64	0	0
T19	10649	138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2729704	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2729704	0	0
T1	51376	422	0	0
T2	256654	2859	0	0
T3	616206	9860	0	0
T4	1998	25	0	0
T13	29346	62	0	0
T14	226153	9869	0	0
T16	52448	353	0	0
T17	261904	76787	0	0
T18	4069	64	0	0
T19	10649	138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1619180	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1619180	0	0
T1	51376	363	0	0
T2	256654	46	0	0
T3	616206	3301	0	0
T4	1998	12	0	0
T13	29346	178	0	0
T14	226153	29389	0	0
T16	52448	379	0	0
T17	261904	1262	0	0
T18	4069	56	0	0
T19	10649	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3821353	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3821353	0	0
T1	51376	376	0	0
T2	256654	3568	0	0
T3	616206	3577	0	0
T4	1998	12	0	0
T13	29346	79	0	0
T14	226153	10223	0	0
T16	52448	322	0	0
T17	261904	100207	0	0
T18	4069	56	0	0
T19	10649	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1664365	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1664365	0	0
T1	51376	418	0	0
T2	256654	19	0	0
T3	616206	6205	0	0
T4	1998	17	0	0
T13	29346	303	0	0
T14	226153	32161	0	0
T15	0	322	0	0
T16	52448	383	0	0
T17	261904	0	0	0
T18	4069	73	0	0
T19	10649	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3144762	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3144762	0	0
T1	51376	425	0	0
T2	256654	3696	0	0
T3	616206	5703	0	0
T4	1998	17	0	0
T13	29346	112	0	0
T14	226153	10519	0	0
T15	0	322	0	0
T16	52448	364	0	0
T17	261904	0	0	0
T18	4069	73	0	0
T19	10649	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1651691	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1651691	0	0
T1	51376	318	0	0
T2	256654	56	0	0
T3	616206	3177	0	0
T4	1998	11	0	0
T13	29346	273	0	0
T14	226153	28471	0	0
T16	52448	430	0	0
T17	261904	1390	0	0
T18	4069	63	0	0
T19	10649	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2741946	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2741946	0	0
T1	51376	374	0	0
T2	256654	5523	0	0
T3	616206	3467	0	0
T4	1998	11	0	0
T13	29346	93	0	0
T14	226153	11137	0	0
T16	52448	347	0	0
T17	261904	101526	0	0
T18	4069	63	0	0
T19	10649	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1616319	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1616319	0	0
T1	51376	319	0	0
T2	256654	47	0	0
T3	616206	7917	0	0
T4	1998	10	0	0
T13	29346	373	0	0
T14	226153	25130	0	0
T15	0	275	0	0
T16	52448	379	0	0
T17	261904	0	0	0
T18	4069	65	0	0
T19	10649	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	2548727	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	2548727	0	0
T1	51376	273	0	0
T2	256654	5206	0	0
T3	616206	8060	0	0
T4	1998	10	0	0
T13	29346	184	0	0
T14	226153	10601	0	0
T15	0	275	0	0
T16	52448	457	0	0
T17	261904	0	0	0
T18	4069	65	0	0
T19	10649	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1715107	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1715107	0	0
T1	51376	462	0	0
T2	256654	51	0	0
T3	616206	4896	0	0
T4	1998	12	0	0
T13	29346	292	0	0
T14	226153	20947	0	0
T15	0	81	0	0
T16	52448	449	0	0
T17	261904	0	0	0
T18	4069	88	0	0
T19	10649	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3584941	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3584941	0	0
T1	51376	480	0	0
T2	256654	3473	0	0
T3	616206	5414	0	0
T4	1998	12	0	0
T13	29346	133	0	0
T14	226153	7131	0	0
T15	0	81	0	0
T16	52448	434	0	0
T17	261904	0	0	0
T18	4069	88	0	0
T19	10649	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	1700940	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	1700940	0	0
T1	51376	376	0	0
T2	256654	29	0	0
T3	616206	7342	0	0
T4	1998	16	0	0
T13	29346	236	0	0
T14	226153	25500	0	0
T15	0	73	0	0
T16	52448	245	0	0
T17	261904	0	0	0
T18	4069	91	0	0
T19	10649	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306424096	3552067	0	0
DepthKnown_A	306424096	306309188	0	0
RvalidKnown_A	306424096	306309188	0	0
WreadyKnown_A	306424096	306309188	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	3552067	0	0
T1	51376	364	0	0
T2	256654	3113	0	0
T3	616206	7492	0	0
T4	1998	16	0	0
T13	29346	128	0	0
T14	226153	7897	0	0
T15	0	73	0	0
T16	52448	337	0	0
T17	261904	0	0	0
T18	4069	91	0	0
T19	10649	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306424096	306309188	0	0
T1	51376	51312	0	0
T2	256654	256622	0	0
T3	616206	615202	0	0
T4	1998	1939	0	0
T13	29346	29277	0	0
T14	226153	226144	0	0
T16	52448	52410	0	0
T17	261904	261896	0	0
T18	4069	4025	0	0
T19	10649	10608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0