Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1700113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

267276

1

T1

25

T2

2

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	663469	1			T1	31		T2	23		T3	33
values[0x0]	637059	1			T1	50		T2	3		T3	39
values[0x1]	666861	1			T1	42		T2	28		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1316799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

650590

1

T1

42

T2

20

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7202	1			T17	1		T18	20		T19	2
valid_sources[0x01]	7920	1			T1	1		T18	20		T15	1
valid_sources[0x02]	7834	1			T2	2		T3	1		T17	1
valid_sources[0x03]	7945	1			T16	1		T17	1		T18	47
valid_sources[0x04]	7940	1			T17	1		T18	51		T15	2
valid_sources[0x05]	7811	1			T3	3		T18	9		T19	4
valid_sources[0x06]	7724	1			T16	2		T17	2		T18	6
valid_sources[0x07]	6976	1			T18	49		T19	2		T21	2
valid_sources[0x08]	7676	1			T3	2		T17	1		T18	19
valid_sources[0x09]	7466	1			T1	1		T16	1		T17	1
valid_sources[0x0a]	7734	1			T1	1		T3	5		T18	30
valid_sources[0x0b]	7368	1			T18	25		T19	2		T26	1
valid_sources[0x0c]	7832	1			T18	16		T19	4		T23	154
valid_sources[0x0d]	7434	1			T16	3		T17	1		T18	66
valid_sources[0x0e]	7473	1			T18	23		T19	10		T26	1
valid_sources[0x0f]	7513	1			T18	54		T19	5		T26	1
valid_sources[0x10]	7098	1			T1	2		T17	1		T18	7
valid_sources[0x11]	7639	1			T17	1		T18	13		T19	12
valid_sources[0x12]	6643	1			T3	1		T18	5		T26	3
valid_sources[0x13]	7241	1			T17	1		T18	47		T26	1
valid_sources[0x14]	7252	1			T3	1		T16	1		T18	25
valid_sources[0x15]	7355	1			T16	1		T17	2		T18	30
valid_sources[0x16]	7161	1			T1	5		T16	1		T17	2
valid_sources[0x17]	8142	1			T1	2		T3	1		T17	2
valid_sources[0x18]	8017	1			T3	1		T18	8		T15	1
valid_sources[0x19]	8106	1			T17	2		T18	16		T19	8
valid_sources[0x1a]	7910	1			T16	1		T17	5		T18	27
valid_sources[0x1b]	8100	1			T17	1		T18	23		T19	5
valid_sources[0x1c]	7697	1			T1	3		T3	1		T17	1
valid_sources[0x1d]	7846	1			T3	1		T16	1		T18	12
valid_sources[0x1e]	7356	1			T2	1		T3	2		T17	3
valid_sources[0x1f]	7122	1			T17	1		T18	14		T15	1
valid_sources[0x20]	7708	1			T18	15		T19	1		T23	159
valid_sources[0x21]	7357	1			T18	8		T15	2		T19	3
valid_sources[0x22]	7800	1			T2	1		T17	2		T18	7
valid_sources[0x23]	8213	1			T1	2		T18	17		T19	4
valid_sources[0x24]	7054	1			T1	1		T17	2		T18	21
valid_sources[0x25]	7488	1			T18	15		T15	2		T19	6
valid_sources[0x26]	7367	1			T17	2		T18	37		T26	3
valid_sources[0x27]	7627	1			T2	2		T18	7		T15	1
valid_sources[0x28]	7502	1			T16	1		T17	1		T18	9
valid_sources[0x29]	7921	1			T1	1		T3	2		T16	1
valid_sources[0x2a]	7830	1			T2	1		T3	1		T17	1
valid_sources[0x2b]	7382	1			T1	2		T18	23		T20	1
valid_sources[0x2c]	7409	1			T3	4		T17	2		T18	3
valid_sources[0x2d]	7669	1			T16	1		T18	12		T15	3
valid_sources[0x2e]	7809	1			T17	2		T18	17		T19	7
valid_sources[0x2f]	7685	1			T1	1		T2	1		T18	12
valid_sources[0x30]	7579	1			T1	2		T3	2		T18	12
valid_sources[0x31]	7163	1			T17	3		T18	15		T15	2
valid_sources[0x32]	7652	1			T1	1		T18	55		T19	7
valid_sources[0x33]	7304	1			T3	2		T17	2		T18	13
valid_sources[0x34]	7518	1			T18	51		T15	1		T19	2
valid_sources[0x35]	7660	1			T1	2		T16	1		T17	1
valid_sources[0x36]	7747	1			T18	24		T19	2		T21	1
valid_sources[0x37]	7511	1			T1	1		T3	2		T17	1
valid_sources[0x38]	7865	1			T1	1		T18	21		T19	2
valid_sources[0x39]	7298	1			T1	1		T18	33		T19	1
valid_sources[0x3a]	7640	1			T1	1		T18	11		T19	3
valid_sources[0x3b]	7521	1			T18	13		T19	10		T26	4
valid_sources[0x3c]	7263	1			T17	1		T18	21		T15	1
valid_sources[0x3d]	7886	1			T3	2		T18	5		T19	7
valid_sources[0x3e]	7788	1			T1	1		T17	1		T18	4
valid_sources[0x3f]	7411	1			T1	1		T3	1		T18	33
valid_sources[0x40]	7927	1			T17	1		T18	52		T19	1
valid_sources[0x41]	7324	1			T2	1		T18	6		T19	8
valid_sources[0x42]	7319	1			T1	1		T3	3		T16	2
valid_sources[0x43]	7827	1			T17	1		T18	44		T19	8
valid_sources[0x44]	8066	1			T3	1		T18	24		T15	1
valid_sources[0x45]	7852	1			T1	2		T2	1		T18	14
valid_sources[0x46]	7445	1			T16	1		T17	1		T18	34
valid_sources[0x47]	8114	1			T1	2		T18	10		T15	1
valid_sources[0x48]	7799	1			T17	1		T18	11		T15	3
valid_sources[0x49]	8649	1			T16	1		T17	3		T18	39
valid_sources[0x4a]	8533	1			T17	1		T18	78		T19	5
valid_sources[0x4b]	8456	1			T16	1		T17	2		T18	9
valid_sources[0x4c]	7955	1			T2	1		T16	1		T17	1
valid_sources[0x4d]	8196	1			T2	1		T3	1		T18	6
valid_sources[0x4e]	7726	1			T17	2		T18	10		T15	1
valid_sources[0x4f]	8074	1			T17	5		T18	16		T15	2
valid_sources[0x50]	7553	1			T1	1		T3	2		T16	1
valid_sources[0x51]	7385	1			T18	8		T15	3		T19	5
valid_sources[0x52]	8371	1			T18	23		T15	3		T19	4
valid_sources[0x53]	7449	1			T1	1		T17	1		T18	29
valid_sources[0x54]	6794	1			T1	1		T2	1		T3	3
valid_sources[0x55]	7751	1			T2	1		T16	2		T17	2
valid_sources[0x56]	7508	1			T1	1		T18	30		T23	203
valid_sources[0x57]	7369	1			T1	1		T17	3		T18	9
valid_sources[0x58]	6889	1			T1	3		T2	1		T3	2
valid_sources[0x59]	7408	1			T18	67		T19	5		T26	2
valid_sources[0x5a]	7971	1			T18	17		T19	5		T22	26
valid_sources[0x5b]	8132	1			T16	1		T18	29		T19	8
valid_sources[0x5c]	7444	1			T17	3		T18	10		T15	2
valid_sources[0x5d]	7621	1			T2	2		T17	2		T18	34
valid_sources[0x5e]	7397	1			T18	33		T19	7		T26	1
valid_sources[0x5f]	7331	1			T18	27		T19	1		T26	3
valid_sources[0x60]	7583	1			T1	2		T18	2		T15	1
valid_sources[0x61]	7005	1			T17	4		T18	11		T19	6
valid_sources[0x62]	7277	1			T1	1		T3	1		T17	2
valid_sources[0x63]	7908	1			T1	1		T3	2		T18	13
valid_sources[0x64]	7615	1			T17	2		T18	23		T19	4
valid_sources[0x65]	8273	1			T1	1		T18	52		T19	5
valid_sources[0x66]	7439	1			T18	22		T19	10		T26	1
valid_sources[0x67]	7266	1			T18	29		T19	9		T23	126
valid_sources[0x68]	8804	1			T17	1		T18	13		T15	1
valid_sources[0x69]	7249	1			T1	2		T18	47		T19	4
valid_sources[0x6a]	7001	1			T18	25		T15	2		T19	7
valid_sources[0x6b]	7127	1			T1	1		T16	1		T18	30
valid_sources[0x6c]	7950	1			T1	1		T17	1		T18	13
valid_sources[0x6d]	7254	1			T2	1		T18	31		T15	2
valid_sources[0x6e]	6660	1			T3	4		T17	3		T18	32
valid_sources[0x6f]	8480	1			T1	1		T17	1		T18	4
valid_sources[0x70]	7302	1			T17	1		T18	39		T19	18
valid_sources[0x71]	8112	1			T1	1		T3	1		T16	1
valid_sources[0x72]	7550	1			T18	10		T19	2		T22	15
valid_sources[0x73]	7590	1			T2	1		T18	12		T15	1
valid_sources[0x74]	8142	1			T1	1		T17	1		T18	37
valid_sources[0x75]	6913	1			T2	1		T18	18		T19	5
valid_sources[0x76]	8717	1			T1	3		T3	1		T17	1
valid_sources[0x77]	7648	1			T18	19		T15	1		T19	13
valid_sources[0x78]	7704	1			T3	3		T17	1		T18	17
valid_sources[0x79]	8197	1			T16	1		T17	2		T18	13
valid_sources[0x7a]	7654	1			T17	1		T18	32		T15	1
valid_sources[0x7b]	7303	1			T18	28		T19	2		T23	165
valid_sources[0x7c]	7736	1			T3	1		T18	11		T19	2
valid_sources[0x7d]	7479	1			T17	1		T18	5		T19	4
valid_sources[0x7e]	8880	1			T16	2		T17	1		T18	9
valid_sources[0x7f]	7399	1			T3	1		T16	1		T18	51
valid_sources[0x80]	7744	1			T2	1		T3	2		T18	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27818

1

T3

1

T16

1

T17

5

values[0x0]

all_enables

biggest_size

211187

1

T1

20

T2

2

T3

8

values[0x1]

all_enables

biggest_size

28271

1

T1

5

T3

2

T17

3