Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	333668323	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333668323	0	0
T1	3380272	60100	0	0
T2	1759688	33683	0	0
T3	5721352	180347	0	0
T15	241080	4881	0	0
T16	1295616	29514	0	0
T17	6256656	152486	0	0
T18	596792	24283	0	0
T19	146608	5803	0	0
T20	958552	18234	0	0
T21	198688	3689	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3380272	3379488	0	0
T2	1759688	1759184	0	0
T3	5721352	5718720	0	0
T15	241080	239288	0	0
T16	1295616	1293656	0	0
T17	6256656	6252624	0	0
T18	596792	595056	0	0
T19	146608	143976	0	0
T20	958552	957712	0	0
T21	198688	196616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3380272	3379488	0	0
T2	1759688	1759184	0	0
T3	5721352	5718720	0	0
T15	241080	239288	0	0
T16	1295616	1293656	0	0
T17	6256656	6252624	0	0
T18	596792	595056	0	0
T19	146608	143976	0	0
T20	958552	957712	0	0
T21	198688	196616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3380272	3379488	0	0
T2	1759688	1759184	0	0
T3	5721352	5718720	0	0
T15	241080	239288	0	0
T16	1295616	1293656	0	0
T17	6256656	6252624	0	0
T18	596792	595056	0	0
T19	146608	143976	0	0
T20	958552	957712	0	0
T21	198688	196616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	122738105	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	122738105	0	0
T1	60362	58828	0	0
T2	31423	14712	0	0
T3	102167	99975	0	0
T15	4305	2259	0	0
T16	23136	11150	0	0
T17	111726	60336	0	0
T18	10657	9982	0	0
T19	2618	2257	0	0
T20	17117	7952	0	0
T21	3548	1636	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	86944458	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	86944458	0	0
T1	60362	346	0	0
T2	31423	4591	0	0
T3	102167	39927	0	0
T15	4305	563	0	0
T16	23136	9878	0	0
T17	111726	30792	0	0
T18	10657	5519	0	0
T19	2618	1182	0	0
T20	17117	2510	0	0
T21	3548	489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1446074	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1446074	0	0
T1	60362	16	0	0
T2	31423	375	0	0
T3	102167	27	0	0
T15	4305	53	0	0
T16	23136	155	0	0
T17	111726	847	0	0
T18	10657	56	0	0
T19	2618	52	0	0
T20	17117	170	0	0
T21	3548	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2513195	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2513195	0	0
T1	60362	3	0	0
T2	31423	217	0	0
T3	102167	1870	0	0
T15	4305	28	0	0
T16	23136	169	0	0
T17	111726	880	0	0
T18	10657	56	0	0
T19	2618	52	0	0
T20	17117	81	0	0
T21	3548	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1434606	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1434606	0	0
T1	60362	17	0	0
T2	31423	209	0	0
T3	102167	25	0	0
T15	4305	61	0	0
T16	23136	155	0	0
T17	111726	888	0	0
T18	10657	52	0	0
T19	2618	47	0	0
T20	17117	158	0	0
T21	3548	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3893212	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3893212	0	0
T1	60362	4	0	0
T2	31423	148	0	0
T3	102167	2293	0	0
T15	4305	32	0	0
T16	23136	167	0	0
T17	111726	939	0	0
T18	10657	52	0	0
T19	2618	47	0	0
T20	17117	108	0	0
T21	3548	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1379130	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1379130	0	0
T1	60362	23	0	0
T2	31423	353	0	0
T3	102167	54	0	0
T15	4305	39	0	0
T16	23136	199	0	0
T17	111726	703	0	0
T18	10657	532	0	0
T19	2618	46	0	0
T20	17117	160	0	0
T21	3548	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3133994	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3133994	0	0
T1	60362	5	0	0
T2	31423	148	0	0
T3	102167	3144	0	0
T15	4305	31	0	0
T16	23136	144	0	0
T17	111726	746	0	0
T18	10657	532	0	0
T19	2618	46	0	0
T20	17117	50	0	0
T21	3548	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1413729	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1413729	0	0
T1	60362	12	0	0
T2	31423	378	0	0
T3	102167	19	0	0
T15	4305	27	0	0
T16	23136	134	0	0
T17	111726	828	0	0
T18	10657	330	0	0
T19	2618	49	0	0
T20	17117	189	0	0
T21	3548	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3752862	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3752862	0	0
T1	60362	2	0	0
T2	31423	198	0	0
T3	102167	1883	0	0
T15	4305	10	0	0
T16	23136	108	0	0
T17	111726	703	0	0
T18	10657	330	0	0
T19	2618	49	0	0
T20	17117	81	0	0
T21	3548	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1445772	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1445772	0	0
T1	60362	25	0	0
T2	31423	416	0	0
T3	102167	20	0	0
T15	4305	33	0	0
T16	23136	150	0	0
T17	111726	664	0	0
T18	10657	273	0	0
T19	2618	51	0	0
T20	17117	138	0	0
T21	3548	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3526582	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3526582	0	0
T1	60362	7	0	0
T2	31423	184	0	0
T3	102167	1067	0	0
T15	4305	18	0	0
T16	23136	123	0	0
T17	111726	722	0	0
T18	10657	273	0	0
T19	2618	51	0	0
T20	17117	99	0	0
T21	3548	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1371783	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1371783	0	0
T1	60362	40	0	0
T2	31423	292	0	0
T3	102167	4	0	0
T15	4305	45	0	0
T16	23136	105	0	0
T17	111726	796	0	0
T18	10657	60	0	0
T19	2618	43	0	0
T20	17117	162	0	0
T21	3548	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3052009	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3052009	0	0
T1	60362	7	0	0
T2	31423	107	0	0
T3	102167	88	0	0
T15	4305	30	0	0
T16	23136	143	0	0
T17	111726	817	0	0
T18	10657	60	0	0
T19	2618	43	0	0
T20	17117	151	0	0
T21	3548	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1399568	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1399568	0	0
T1	60362	34	0	0
T2	31423	282	0	0
T3	102167	25	0	0
T15	4305	58	0	0
T16	23136	325	0	0
T17	111726	819	0	0
T18	10657	60	0	0
T19	2618	42	0	0
T20	17117	184	0	0
T21	3548	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3694358	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3694358	0	0
T1	60362	8	0	0
T2	31423	107	0	0
T3	102167	1643	0	0
T15	4305	26	0	0
T16	23136	230	0	0
T17	111726	848	0	0
T18	10657	60	0	0
T19	2618	42	0	0
T20	17117	55	0	0
T21	3548	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1423449	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1423449	0	0
T1	60362	13	0	0
T2	31423	460	0	0
T3	102167	20	0	0
T15	4305	97	0	0
T16	23136	152	0	0
T17	111726	2750	0	0
T18	10657	594	0	0
T19	2618	40	0	0
T20	17117	267	0	0
T21	3548	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2934003	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2934003	0	0
T1	60362	2	0	0
T2	31423	220	0	0
T3	102167	2674	0	0
T15	4305	29	0	0
T16	23136	166	0	0
T17	111726	2656	0	0
T18	10657	594	0	0
T19	2618	40	0	0
T20	17117	133	0	0
T21	3548	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1388652	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1388652	0	0
T1	60362	8	0	0
T2	31423	257	0	0
T3	102167	13	0	0
T15	4305	80	0	0
T16	23136	163	0	0
T17	111726	696	0	0
T18	10657	52	0	0
T19	2618	54	0	0
T20	17117	176	0	0
T21	3548	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2868086	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2868086	0	0
T1	60362	3	0	0
T2	31423	129	0	0
T3	102167	617	0	0
T15	4305	24	0	0
T16	23136	169	0	0
T17	111726	751	0	0
T18	10657	52	0	0
T19	2618	54	0	0
T20	17117	78	0	0
T21	3548	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1337361	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1337361	0	0
T1	60362	9	0	0
T2	31423	341	0	0
T3	102167	12	0	0
T15	4305	18	0	0
T16	23136	85	0	0
T17	111726	2492	0	0
T18	10657	78	0	0
T19	2618	36	0	0
T20	17117	231	0	0
T21	3548	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2237941	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2237941	0	0
T1	60362	2	0	0
T2	31423	203	0	0
T3	102167	480	0	0
T15	4305	10	0	0
T16	23136	109	0	0
T17	111726	2641	0	0
T18	10657	78	0	0
T19	2618	36	0	0
T20	17117	113	0	0
T21	3548	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1423796	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1423796	0	0
T1	60362	27	0	0
T2	31423	386	0	0
T3	102167	43	0	0
T15	4305	47	0	0
T16	23136	171	0	0
T17	111726	688	0	0
T18	10657	45	0	0
T19	2618	46	0	0
T20	17117	63	0	0
T21	3548	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2545131	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2545131	0	0
T1	60362	4	0	0
T2	31423	145	0	0
T3	102167	2451	0	0
T15	4305	17	0	0
T16	23136	114	0	0
T17	111726	721	0	0
T18	10657	45	0	0
T19	2618	46	0	0
T20	17117	56	0	0
T21	3548	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1449665	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1449665	0	0
T1	60362	16	0	0
T2	31423	453	0	0
T3	102167	17	0	0
T15	4305	29	0	0
T16	23136	156	0	0
T17	111726	836	0	0
T18	10657	568	0	0
T19	2618	32	0	0
T20	17117	170	0	0
T21	3548	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3047160	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3047160	0	0
T1	60362	5	0	0
T2	31423	161	0	0
T3	102167	1801	0	0
T15	4305	10	0	0
T16	23136	144	0	0
T17	111726	875	0	0
T18	10657	568	0	0
T19	2618	32	0	0
T20	17117	80	0	0
T21	3548	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1405634	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1405634	0	0
T1	60362	15	0	0
T2	31423	315	0	0
T3	102167	10	0	0
T15	4305	55	0	0
T16	23136	141	0	0
T17	111726	664	0	0
T18	10657	68	0	0
T19	2618	43	0	0
T20	17117	185	0	0
T21	3548	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3039102	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3039102	0	0
T1	60362	3	0	0
T2	31423	163	0	0
T3	102167	1514	0	0
T15	4305	13	0	0
T16	23136	108	0	0
T17	111726	654	0	0
T18	10657	68	0	0
T19	2618	43	0	0
T20	17117	83	0	0
T21	3548	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1413968	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1413968	0	0
T1	60362	30	0	0
T2	31423	298	0	0
T3	102167	24	0	0
T15	4305	43	0	0
T16	23136	143	0	0
T17	111726	2518	0	0
T18	10657	252	0	0
T19	2618	47	0	0
T20	17117	240	0	0
T21	3548	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3210108	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3210108	0	0
T1	60362	6	0	0
T2	31423	123	0	0
T3	102167	1314	0	0
T15	4305	6	0	0
T16	23136	122	0	0
T17	111726	2530	0	0
T18	10657	252	0	0
T19	2618	47	0	0
T20	17117	93	0	0
T21	3548	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1407242	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1407242	0	0
T1	60362	19	0	0
T2	31423	451	0	0
T3	102167	38	0	0
T15	4305	25	0	0
T16	23136	156	0	0
T17	111726	2966	0	0
T18	10657	54	0	0
T19	2618	38	0	0
T20	17117	230	0	0
T21	3548	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3667123	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3667123	0	0
T1	60362	4	0	0
T2	31423	228	0	0
T3	102167	2339	0	0
T15	4305	8	0	0
T16	23136	162	0	0
T17	111726	2809	0	0
T18	10657	54	0	0
T19	2618	38	0	0
T20	17117	61	0	0
T21	3548	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1431298	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1431298	0	0
T1	60362	33	0	0
T2	31423	287	0	0
T3	102167	16	0	0
T15	4305	127	0	0
T16	23136	138	0	0
T17	111726	734	0	0
T18	10657	68	0	0
T19	2618	38	0	0
T20	17117	229	0	0
T21	3548	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3083350	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3083350	0	0
T1	60362	9	0	0
T2	31423	178	0	0
T3	102167	1330	0	0
T15	4305	28	0	0
T16	23136	96	0	0
T17	111726	680	0	0
T18	10657	68	0	0
T19	2618	38	0	0
T20	17117	99	0	0
T21	3548	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1458421	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1458421	0	0
T1	60362	20	0	0
T2	31423	333	0	0
T3	102167	11	0	0
T15	4305	33	0	0
T16	23136	157	0	0
T17	111726	717	0	0
T18	10657	59	0	0
T19	2618	41	0	0
T20	17117	272	0	0
T21	3548	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3746482	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3746482	0	0
T1	60362	4	0	0
T2	31423	162	0	0
T3	102167	1102	0	0
T15	4305	19	0	0
T16	23136	164	0	0
T17	111726	709	0	0
T18	10657	59	0	0
T19	2618	41	0	0
T20	17117	171	0	0
T21	3548	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1446473	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1446473	0	0
T1	60362	19	0	0
T2	31423	397	0	0
T3	102167	7	0	0
T15	4305	59	0	0
T16	23136	195	0	0
T17	111726	770	0	0
T18	10657	60	0	0
T19	2618	36	0	0
T20	17117	199	0	0
T21	3548	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2977101	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2977101	0	0
T1	60362	5	0	0
T2	31423	206	0	0
T3	102167	562	0	0
T15	4305	26	0	0
T16	23136	198	0	0
T17	111726	732	0	0
T18	10657	60	0	0
T19	2618	36	0	0
T20	17117	108	0	0
T21	3548	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1396204	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1396204	0	0
T1	60362	23	0	0
T2	31423	356	0	0
T3	102167	8	0	0
T15	4305	72	0	0
T16	23136	233	0	0
T17	111726	727	0	0
T18	10657	71	0	0
T19	2618	48	0	0
T20	17117	164	0	0
T21	3548	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3452801	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3452801	0	0
T1	60362	3	0	0
T2	31423	161	0	0
T3	102167	331	0	0
T15	4305	17	0	0
T16	23136	167	0	0
T17	111726	645	0	0
T18	10657	71	0	0
T19	2618	48	0	0
T20	17117	71	0	0
T21	3548	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1382231	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1382231	0	0
T1	60362	39	0	0
T2	31423	434	0	0
T3	102167	13	0	0
T15	4305	79	0	0
T16	23136	180	0	0
T17	111726	3300	0	0
T18	10657	69	0	0
T19	2618	49	0	0
T20	17117	214	0	0
T21	3548	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3633582	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3633582	0	0
T1	60362	230	0	0
T2	31423	199	0	0
T3	102167	2081	0	0
T15	4305	45	0	0
T16	23136	164	0	0
T17	111726	3275	0	0
T18	10657	69	0	0
T19	2618	49	0	0
T20	17117	99	0	0
T21	3548	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1367004	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1367004	0	0
T1	60362	11	0	0
T2	31423	408	0	0
T3	102167	26	0	0
T15	4305	70	0	0
T16	23136	112	0	0
T17	111726	690	0	0
T18	10657	60	0	0
T19	2618	42	0	0
T20	17117	278	0	0
T21	3548	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3178706	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3178706	0	0
T1	60362	2	0	0
T2	31423	193	0	0
T3	102167	2506	0	0
T15	4305	24	0	0
T16	23136	256	0	0
T17	111726	803	0	0
T18	10657	60	0	0
T19	2618	42	0	0
T20	17117	87	0	0
T21	3548	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1452719	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1452719	0	0
T1	60362	51	0	0
T2	31423	401	0	0
T3	102167	4	0	0
T15	4305	75	0	0
T16	23136	142	0	0
T17	111726	817	0	0
T18	10657	357	0	0
T19	2618	48	0	0
T20	17117	159	0	0
T21	3548	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3880308	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3880308	0	0
T1	60362	9	0	0
T2	31423	124	0	0
T3	102167	614	0	0
T15	4305	26	0	0
T16	23136	113	0	0
T17	111726	852	0	0
T18	10657	357	0	0
T19	2618	48	0	0
T20	17117	86	0	0
T21	3548	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1380770	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1380770	0	0
T1	60362	37	0	0
T2	31423	421	0	0
T3	102167	14	0	0
T15	4305	55	0	0
T16	23136	151	0	0
T17	111726	829	0	0
T18	10657	327	0	0
T19	2618	48	0	0
T20	17117	240	0	0
T21	3548	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2275328	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2275328	0	0
T1	60362	7	0	0
T2	31423	166	0	0
T3	102167	1205	0	0
T15	4305	12	0	0
T16	23136	174	0	0
T17	111726	873	0	0
T18	10657	327	0	0
T19	2618	48	0	0
T20	17117	91	0	0
T21	3548	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1369614	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1369614	0	0
T1	60362	8	0	0
T2	31423	317	0	0
T3	102167	17	0	0
T15	4305	42	0	0
T16	23136	65	0	0
T17	111726	834	0	0
T18	10657	67	0	0
T19	2618	48	0	0
T20	17117	142	0	0
T21	3548	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	2430905	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	2430905	0	0
T1	60362	1	0	0
T2	31423	166	0	0
T3	102167	706	0	0
T15	4305	8	0	0
T16	23136	87	0	0
T17	111726	773	0	0
T18	10657	67	0	0
T19	2618	48	0	0
T20	17117	81	0	0
T21	3548	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1423339	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1423339	0	0
T1	60362	2	0	0
T2	31423	353	0	0
T3	102167	19	0	0
T15	4305	46	0	0
T16	23136	148	0	0
T17	111726	708	0	0
T18	10657	51	0	0
T19	2618	39	0	0
T20	17117	235	0	0
T21	3548	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3497797	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3497797	0	0
T1	60362	1	0	0
T2	31423	243	0	0
T3	102167	485	0	0
T15	4305	16	0	0
T16	23136	123	0	0
T17	111726	626	0	0
T18	10657	51	0	0
T19	2618	39	0	0
T20	17117	118	0	0
T21	3548	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1361979	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1361979	0	0
T1	60362	15	0	0
T2	31423	436	0	0
T3	102167	13	0	0
T15	4305	76	0	0
T16	23136	128	0	0
T17	111726	736	0	0
T18	10657	62	0	0
T19	2618	38	0	0
T20	17117	146	0	0
T21	3548	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3125424	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3125424	0	0
T1	60362	3	0	0
T2	31423	183	0	0
T3	102167	1987	0	0
T15	4305	18	0	0
T16	23136	162	0	0
T17	111726	721	0	0
T18	10657	62	0	0
T19	2618	38	0	0
T20	17117	63	0	0
T21	3548	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	1405697	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	1405697	0	0
T1	60362	18	0	0
T2	31423	380	0	0
T3	102167	19	0	0
T15	4305	52	0	0
T16	23136	272	0	0
T17	111726	654	0	0
T18	10657	66	0	0
T19	2618	41	0	0
T20	17117	261	0	0
T21	3548	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297932336	3572932	0	0
DepthKnown_A	297932336	297812735	0	0
RvalidKnown_A	297932336	297812735	0	0
WreadyKnown_A	297932336	297812735	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	3572932	0	0
T1	60362	7	0	0
T2	31423	129	0	0
T3	102167	1840	0	0
T15	4305	32	0	0
T16	23136	293	0	0
T17	111726	706	0	0
T18	10657	66	0	0
T19	2618	41	0	0
T20	17117	114	0	0
T21	3548	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297932336	297812735	0	0
T1	60362	60348	0	0
T2	31423	31414	0	0
T3	102167	102120	0	0
T15	4305	4273	0	0
T16	23136	23101	0	0
T17	111726	111654	0	0
T18	10657	10626	0	0
T19	2618	2571	0	0
T20	17117	17102	0	0
T21	3548	3511	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0