Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1752237	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

275410

1

T1

551

T2

31

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	685761	1			T1	1273		T2	55		T3	56
values[0x0]	656490	1			T1	1289		T2	60		T3	55
values[0x1]	685396	1			T1	1263		T2	63		T3	83

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1357496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

670151

1

T1

1289

T2

60

T3

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8019	1			T1	16		T2	1		T3	4
valid_sources[0x01]	7294	1			T1	16		T3	2		T4	1
valid_sources[0x02]	7951	1			T1	15		T3	4		T16	9
valid_sources[0x03]	7692	1			T1	15		T16	9		T5	1
valid_sources[0x04]	9545	1			T1	15		T2	1		T4	2
valid_sources[0x05]	7360	1			T1	14		T3	1		T16	11
valid_sources[0x06]	7735	1			T1	14		T2	2		T16	15
valid_sources[0x07]	7748	1			T1	15		T16	11		T17	7
valid_sources[0x08]	8468	1			T1	17		T3	3		T16	12
valid_sources[0x09]	7876	1			T1	17		T2	2		T16	15
valid_sources[0x0a]	8145	1			T1	14		T3	1		T16	6
valid_sources[0x0b]	7926	1			T1	16		T16	6		T17	18
valid_sources[0x0c]	8109	1			T1	16		T16	5		T17	10
valid_sources[0x0d]	7375	1			T1	14		T2	1		T16	13
valid_sources[0x0e]	7330	1			T1	16		T2	1		T16	6
valid_sources[0x0f]	9554	1			T1	14		T3	7		T4	1
valid_sources[0x10]	7955	1			T1	14		T2	2		T4	1
valid_sources[0x11]	7206	1			T1	16		T3	5		T16	13
valid_sources[0x12]	8118	1			T1	15		T16	9		T17	6
valid_sources[0x13]	8281	1			T1	14		T3	2		T16	8
valid_sources[0x14]	8347	1			T1	14		T3	1		T16	7
valid_sources[0x15]	9762	1			T1	14		T4	1		T16	7
valid_sources[0x16]	9122	1			T1	18		T4	2		T16	8
valid_sources[0x17]	8912	1			T1	15		T3	3		T16	12
valid_sources[0x18]	7630	1			T1	16		T4	1		T16	7
valid_sources[0x19]	7512	1			T1	14		T16	16		T5	1
valid_sources[0x1a]	7131	1			T1	16		T2	2		T16	10
valid_sources[0x1b]	7291	1			T1	17		T16	10		T17	20
valid_sources[0x1c]	8161	1			T1	16		T4	1		T16	17
valid_sources[0x1d]	7658	1			T1	16		T16	8		T17	11
valid_sources[0x1e]	7998	1			T1	14		T3	1		T16	12
valid_sources[0x1f]	7832	1			T1	15		T16	12		T17	21
valid_sources[0x20]	7774	1			T1	17		T3	1		T16	17
valid_sources[0x21]	8113	1			T1	15		T16	9		T17	16
valid_sources[0x22]	7274	1			T1	15		T16	4		T17	16
valid_sources[0x23]	8474	1			T1	14		T2	2		T16	9
valid_sources[0x24]	7655	1			T1	15		T4	3		T16	13
valid_sources[0x25]	7961	1			T1	15		T4	4		T16	11
valid_sources[0x26]	7394	1			T1	15		T16	14		T17	15
valid_sources[0x27]	7393	1			T1	14		T2	4		T3	3
valid_sources[0x28]	7742	1			T1	15		T2	1		T4	1
valid_sources[0x29]	7876	1			T1	15		T2	4		T3	2
valid_sources[0x2a]	7558	1			T1	15		T2	1		T16	12
valid_sources[0x2b]	7491	1			T1	14		T3	2		T16	12
valid_sources[0x2c]	7833	1			T1	15		T2	1		T16	17
valid_sources[0x2d]	7687	1			T1	14		T3	5		T4	1
valid_sources[0x2e]	8328	1			T1	13		T3	1		T16	16
valid_sources[0x2f]	8500	1			T1	15		T3	2		T16	6
valid_sources[0x30]	10757	1			T1	13		T16	7		T17	21
valid_sources[0x31]	9019	1			T1	14		T3	3		T16	10
valid_sources[0x32]	7910	1			T1	15		T16	13		T17	7
valid_sources[0x33]	8300	1			T1	16		T2	1		T16	11
valid_sources[0x34]	8156	1			T1	14		T4	1		T16	20
valid_sources[0x35]	7697	1			T1	14		T16	10		T17	19
valid_sources[0x36]	7909	1			T1	13		T4	1		T16	9
valid_sources[0x37]	8572	1			T1	15		T3	1		T4	3
valid_sources[0x38]	7923	1			T1	14		T2	3		T3	3
valid_sources[0x39]	7479	1			T1	15		T2	1		T16	10
valid_sources[0x3a]	7958	1			T1	15		T4	2		T16	4
valid_sources[0x3b]	7775	1			T1	14		T16	19		T17	19
valid_sources[0x3c]	7664	1			T1	16		T2	4		T3	5
valid_sources[0x3d]	8584	1			T1	15		T4	2		T16	8
valid_sources[0x3e]	7823	1			T1	14		T2	3		T4	1
valid_sources[0x3f]	7733	1			T1	16		T16	16		T5	1
valid_sources[0x40]	7798	1			T1	15		T16	20		T17	8
valid_sources[0x41]	8430	1			T1	15		T4	7		T16	9
valid_sources[0x42]	7621	1			T1	14		T4	7		T16	9
valid_sources[0x43]	7363	1			T1	17		T16	8		T17	11
valid_sources[0x44]	7921	1			T1	15		T16	8		T17	21
valid_sources[0x45]	7625	1			T1	14		T2	1		T3	1
valid_sources[0x46]	8927	1			T1	13		T16	10		T17	17
valid_sources[0x47]	8012	1			T1	13		T3	1		T16	11
valid_sources[0x48]	7435	1			T1	15		T3	1		T16	14
valid_sources[0x49]	8209	1			T1	16		T3	1		T16	14
valid_sources[0x4a]	8392	1			T1	14		T2	1		T16	10
valid_sources[0x4b]	7600	1			T1	15		T2	1		T16	11
valid_sources[0x4c]	7001	1			T1	13		T2	2		T4	1
valid_sources[0x4d]	7407	1			T1	14		T2	3		T4	2
valid_sources[0x4e]	7578	1			T1	14		T4	1		T16	12
valid_sources[0x4f]	7480	1			T1	14		T2	2		T16	8
valid_sources[0x50]	8052	1			T1	16		T2	5		T3	2
valid_sources[0x51]	7083	1			T1	14		T2	3		T3	1
valid_sources[0x52]	8625	1			T1	15		T2	1		T16	11
valid_sources[0x53]	7232	1			T1	19		T16	12		T5	1
valid_sources[0x54]	7708	1			T1	14		T16	12		T5	3
valid_sources[0x55]	7767	1			T1	14		T16	21		T5	1
valid_sources[0x56]	7503	1			T1	16		T3	3		T16	6
valid_sources[0x57]	8111	1			T1	13		T2	1		T16	8
valid_sources[0x58]	7663	1			T1	15		T2	1		T16	14
valid_sources[0x59]	8405	1			T1	17		T2	1		T4	2
valid_sources[0x5a]	7581	1			T1	16		T16	7		T5	1
valid_sources[0x5b]	9662	1			T1	14		T3	3		T16	11
valid_sources[0x5c]	8118	1			T1	15		T16	7		T17	18
valid_sources[0x5d]	7475	1			T1	16		T2	4		T4	2
valid_sources[0x5e]	7621	1			T1	14		T16	8		T17	6
valid_sources[0x5f]	8235	1			T1	13		T2	2		T16	8
valid_sources[0x60]	7328	1			T1	15		T2	2		T16	7
valid_sources[0x61]	7712	1			T1	16		T2	3		T4	2
valid_sources[0x62]	7875	1			T1	14		T2	5		T4	6
valid_sources[0x63]	7783	1			T1	16		T16	19		T17	5
valid_sources[0x64]	7815	1			T1	15		T16	16		T17	10
valid_sources[0x65]	8485	1			T1	15		T16	9		T17	11
valid_sources[0x66]	9237	1			T1	15		T16	18		T17	11
valid_sources[0x67]	8308	1			T1	16		T16	18		T5	1
valid_sources[0x68]	7862	1			T1	16		T16	9		T5	1
valid_sources[0x69]	7100	1			T1	15		T3	1		T16	13
valid_sources[0x6a]	8424	1			T1	15		T2	1		T4	6
valid_sources[0x6b]	7499	1			T1	16		T2	2		T16	8
valid_sources[0x6c]	7602	1			T1	15		T4	1		T16	15
valid_sources[0x6d]	7818	1			T1	15		T3	1		T16	9
valid_sources[0x6e]	8591	1			T1	15		T16	16		T17	12
valid_sources[0x6f]	7851	1			T1	17		T16	10		T17	10
valid_sources[0x70]	8547	1			T1	15		T16	8		T5	2
valid_sources[0x71]	7167	1			T1	13		T16	12		T5	1
valid_sources[0x72]	8400	1			T1	14		T16	12		T17	15
valid_sources[0x73]	7717	1			T1	16		T3	4		T16	13
valid_sources[0x74]	8246	1			T1	15		T2	4		T3	2
valid_sources[0x75]	7881	1			T1	14		T3	2		T16	11
valid_sources[0x76]	7341	1			T1	15		T2	1		T16	11
valid_sources[0x77]	8699	1			T1	18		T4	3		T16	9
valid_sources[0x78]	8025	1			T1	13		T4	1		T16	9
valid_sources[0x79]	7248	1			T1	18		T16	16		T17	7
valid_sources[0x7a]	7689	1			T1	15		T16	6		T17	8
valid_sources[0x7b]	8079	1			T1	16		T2	1		T3	4
valid_sources[0x7c]	7569	1			T1	14		T16	16		T17	4
valid_sources[0x7d]	7604	1			T1	15		T3	2		T16	16
valid_sources[0x7e]	8523	1			T1	17		T16	13		T17	13
valid_sources[0x7f]	7196	1			T1	16		T2	1		T16	8
valid_sources[0x80]	7377	1			T1	17		T16	7		T17	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28953

1

T1

48

T2

1

T3

2

values[0x0]

all_enables

biggest_size

217546

1

T1

443

T2

25

T3

19

values[0x1]

all_enables

biggest_size

28911

1

T1

60

T2

5

T3

5