Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	326333529	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	326333529	0	0
T1	7936632	1551951	0	0
T2	13104224	341639	0	0
T3	5412904	96646	0	0
T4	20216	728	0	0
T5	1295896	26818	0	0
T6	61656	1216	0	0
T16	3068184	66398	0	0
T17	20439888	2534881	0	0
T18	1638784	35152	0	0
T19	8014272	95556	0	0
T22	10866352	200810	0	0
T23	0	568	0	0
T24	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18518808	18518360	0	0
T2	13104224	13102600	0	0
T3	5412904	5411000	0	0
T4	20216	19712	0	0
T5	1295896	1293656	0	0
T6	61656	60032	0	0
T16	3068184	3064320	0	0
T17	20439888	20439720	0	0
T18	1638784	1635592	0	0
T22	10866352	10862264	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18518808	18518360	0	0
T2	13104224	13102600	0	0
T3	5412904	5411000	0	0
T4	20216	19712	0	0
T5	1295896	1293656	0	0
T6	61656	60032	0	0
T16	3068184	3064320	0	0
T17	20439888	20439720	0	0
T18	1638784	1635592	0	0
T22	10866352	10862264	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18518808	18518360	0	0
T2	13104224	13102600	0	0
T3	5412904	5411000	0	0
T4	20216	19712	0	0
T5	1295896	1293656	0	0
T6	61656	60032	0	0
T16	3068184	3064320	0	0
T17	20439888	20439720	0	0
T18	1638784	1635592	0	0
T22	10866352	10862264	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	123533367	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	123533367	0	0
T1	330693	17690	0	0
T2	234004	147087	0	0
T3	96659	94647	0	0
T4	361	281	0	0
T5	23141	12425	0	0
T6	1101	535	0	0
T16	54789	21687	0	0
T17	364998	178172	0	0
T18	29264	15299	0	0
T22	194042	96988	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	80775301	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	80775301	0	0
T1	330693	137870	0	0
T2	234004	68897	0	0
T3	96659	558	0	0
T4	361	149	0	0
T5	23141	3252	0	0
T6	1101	197	0	0
T16	54789	11512	0	0
T17	364998	697982	0	0
T18	29264	6212	0	0
T22	194042	20121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1528720	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1528720	0	0
T2	234004	2333	0	0
T3	96659	29	0	0
T4	361	7	0	0
T5	23141	279	0	0
T6	1101	8	0	0
T16	54789	0	0	0
T17	364998	34001	0	0
T18	29264	305	0	0
T19	250446	3891	0	0
T22	194042	3451	0	0
T23	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2860836	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2860836	0	0
T2	234004	3089	0	0
T3	96659	10	0	0
T4	361	7	0	0
T5	23141	121	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	24972	0	0
T18	29264	213	0	0
T19	250446	1774	0	0
T22	194042	1468	0	0
T23	0	16	0	0
T24	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1518153	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1518153	0	0
T2	234004	1475	0	0
T3	96659	50	0	0
T4	361	6	0	0
T5	23141	258	0	0
T6	1101	11	0	0
T16	54789	0	0	0
T17	364998	33414	0	0
T18	29264	360	0	0
T19	250446	1811	0	0
T22	194042	2123	0	0
T23	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3186441	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3186441	0	0
T2	234004	2353	0	0
T3	96659	12	0	0
T4	361	6	0	0
T5	23141	106	0	0
T6	1101	6	0	0
T16	54789	0	0	0
T17	364998	23034	0	0
T18	29264	302	0	0
T19	250446	924	0	0
T22	194042	1207	0	0
T23	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1528811	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1528811	0	0
T1	330693	2257	0	0
T2	234004	2708	0	0
T3	96659	44	0	0
T4	361	5	0	0
T5	23141	273	0	0
T6	1101	0	0	0
T16	54789	2029	0	0
T17	364998	35791	0	0
T18	29264	276	0	0
T19	0	6037	0	0
T22	194042	1685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2999743	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2999743	0	0
T1	330693	171412	0	0
T2	234004	4227	0	0
T3	96659	8	0	0
T4	361	5	0	0
T5	23141	95	0	0
T6	1101	0	0	0
T16	54789	921	0	0
T17	364998	28149	0	0
T18	29264	196	0	0
T19	0	2719	0	0
T22	194042	634	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1593376	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1593376	0	0
T2	234004	3808	0	0
T3	96659	59	0	0
T4	361	5	0	0
T5	23141	228	0	0
T6	1101	14	0	0
T16	54789	3387	0	0
T17	364998	32684	0	0
T18	29264	130	0	0
T19	250446	1508	0	0
T22	194042	3546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3038488	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3038488	0	0
T2	234004	5235	0	0
T3	96659	10	0	0
T4	361	5	0	0
T5	23141	103	0	0
T6	1101	2	0	0
T16	54789	1642	0	0
T17	364998	19731	0	0
T18	29264	169	0	0
T19	250446	729	0	0
T22	194042	1453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1580116	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1580116	0	0
T1	330693	2504	0	0
T2	234004	2412	0	0
T3	96659	25	0	0
T4	361	4	0	0
T5	23141	348	0	0
T6	1101	32	0	0
T16	54789	0	0	0
T17	364998	38374	0	0
T18	29264	315	0	0
T19	0	1795	0	0
T22	194042	1477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3314743	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3314743	0	0
T1	330693	197485	0	0
T2	234004	3622	0	0
T3	96659	6	0	0
T4	361	4	0	0
T5	23141	128	0	0
T6	1101	14	0	0
T16	54789	0	0	0
T17	364998	25140	0	0
T18	29264	256	0	0
T19	0	859	0	0
T22	194042	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1607883	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1607883	0	0
T1	330693	1315	0	0
T2	234004	1424	0	0
T3	96659	45	0	0
T4	361	2	0	0
T5	23141	213	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	31347	0	0
T18	29264	242	0	0
T19	0	1557	0	0
T22	194042	1253	0	0
T23	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3141737	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3141737	0	0
T1	330693	105138	0	0
T2	234004	1088	0	0
T3	96659	8	0	0
T4	361	2	0	0
T5	23141	86	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	22445	0	0
T18	29264	216	0	0
T19	0	737	0	0
T22	194042	25	0	0
T23	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1577248	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1577248	0	0
T1	330693	1101	0	0
T2	234004	2472	0	0
T3	96659	28	0	0
T4	361	4	0	0
T5	23141	268	0	0
T6	1101	19	0	0
T16	54789	0	0	0
T17	364998	35553	0	0
T18	29264	263	0	0
T19	0	1723	0	0
T22	194042	2321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3245332	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3245332	0	0
T1	330693	82389	0	0
T2	234004	3068	0	0
T3	96659	368	0	0
T4	361	4	0	0
T5	23141	89	0	0
T6	1101	17	0	0
T16	54789	0	0	0
T17	364998	24993	0	0
T18	29264	337	0	0
T19	0	836	0	0
T22	194042	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1541012	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1541012	0	0
T2	234004	919	0	0
T3	96659	29	0	0
T4	361	6	0	0
T5	23141	297	0	0
T6	1101	4	0	0
T16	54789	2112	0	0
T17	364998	30809	0	0
T18	29264	359	0	0
T19	250446	1863	0	0
T22	194042	1599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2727818	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2727818	0	0
T2	234004	1967	0	0
T3	96659	6	0	0
T4	361	6	0	0
T5	23141	138	0	0
T6	1101	7	0	0
T16	54789	1012	0	0
T17	364998	24971	0	0
T18	29264	350	0	0
T19	250446	763	0	0
T22	194042	1243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1560394	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1560394	0	0
T2	234004	1695	0	0
T3	96659	19	0	0
T4	361	3	0	0
T5	23141	405	0	0
T6	1101	0	0	0
T16	54789	2504	0	0
T17	364998	24520	0	0
T18	29264	343	0	0
T19	250446	3378	0	0
T22	194042	2774	0	0
T23	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2684865	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2684865	0	0
T2	234004	2020	0	0
T3	96659	5	0	0
T4	361	3	0	0
T5	23141	163	0	0
T6	1101	0	0	0
T16	54789	1203	0	0
T17	364998	22107	0	0
T18	29264	240	0	0
T19	250446	1345	0	0
T22	194042	517	0	0
T23	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1558438	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1558438	0	0
T1	330693	874	0	0
T2	234004	772	0	0
T3	96659	37	0	0
T4	361	7	0	0
T5	23141	287	0	0
T6	1101	25	0	0
T16	54789	1439	0	0
T17	364998	39934	0	0
T18	29264	196	0	0
T22	194042	4556	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2692322	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2692322	0	0
T1	330693	71793	0	0
T2	234004	1733	0	0
T3	96659	10	0	0
T4	361	7	0	0
T5	23141	106	0	0
T6	1101	25	0	0
T16	54789	1003	0	0
T17	364998	29410	0	0
T18	29264	219	0	0
T22	194042	1380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1604715	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1604715	0	0
T2	234004	1392	0	0
T3	96659	18	0	0
T4	361	7	0	0
T5	23141	284	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	44057	0	0
T18	29264	368	0	0
T19	250446	1693	0	0
T22	194042	1977	0	0
T23	0	22	0	0
T24	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3379411	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3379411	0	0
T2	234004	2889	0	0
T3	96659	5	0	0
T4	361	7	0	0
T5	23141	137	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	30067	0	0
T18	29264	316	0	0
T19	250446	740	0	0
T22	194042	506	0	0
T23	0	22	0	0
T24	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1555720	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1555720	0	0
T2	234004	2574	0	0
T3	96659	22	0	0
T4	361	3	0	0
T5	23141	228	0	0
T6	1101	4	0	0
T16	54789	0	0	0
T17	364998	39663	0	0
T18	29264	246	0	0
T19	250446	1800	0	0
T22	194042	1909	0	0
T23	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3124249	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3124249	0	0
T2	234004	2144	0	0
T3	96659	3	0	0
T4	361	3	0	0
T5	23141	78	0	0
T6	1101	6	0	0
T16	54789	0	0	0
T17	364998	26793	0	0
T18	29264	168	0	0
T19	250446	780	0	0
T22	194042	807	0	0
T23	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1580921	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1580921	0	0
T2	234004	2205	0	0
T3	96659	20	0	0
T4	361	11	0	0
T5	23141	358	0	0
T6	1101	30	0	0
T16	54789	2227	0	0
T17	364998	44782	0	0
T18	29264	233	0	0
T19	250446	1395	0	0
T22	194042	455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2606774	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2606774	0	0
T2	234004	3623	0	0
T3	96659	4	0	0
T4	361	11	0	0
T5	23141	155	0	0
T6	1101	6	0	0
T16	54789	1084	0	0
T17	364998	28968	0	0
T18	29264	129	0	0
T19	250446	749	0	0
T22	194042	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1545347	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1545347	0	0
T2	234004	2282	0	0
T3	96659	36	0	0
T4	361	5	0	0
T5	23141	340	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	40919	0	0
T18	29264	336	0	0
T19	250446	5785	0	0
T22	194042	3961	0	0
T23	0	23	0	0
T24	0	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2625073	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2625073	0	0
T2	234004	1452	0	0
T3	96659	8	0	0
T4	361	5	0	0
T5	23141	115	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	34707	0	0
T18	29264	302	0	0
T19	250446	2525	0	0
T22	194042	2350	0	0
T23	0	23	0	0
T24	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1502439	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1502439	0	0
T1	330693	2253	0	0
T2	234004	2877	0	0
T3	96659	54	0	0
T4	361	4	0	0
T5	23141	252	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	30129	0	0
T18	29264	305	0	0
T19	0	1581	0	0
T22	194042	2107	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3382029	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3382029	0	0
T1	330693	180532	0	0
T2	234004	2745	0	0
T3	96659	10	0	0
T4	361	4	0	0
T5	23141	139	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	25703	0	0
T18	29264	210	0	0
T19	0	661	0	0
T22	194042	391	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1527631	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1527631	0	0
T1	330693	1376	0	0
T2	234004	2151	0	0
T3	96659	35	0	0
T4	361	5	0	0
T5	23141	287	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	32113	0	0
T18	29264	154	0	0
T19	0	5786	0	0
T22	194042	2390	0	0
T23	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3541771	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3541771	0	0
T1	330693	104244	0	0
T2	234004	3232	0	0
T3	96659	9	0	0
T4	361	5	0	0
T5	23141	155	0	0
T6	1101	0	0	0
T16	54789	0	0	0
T17	364998	22106	0	0
T18	29264	152	0	0
T19	0	2692	0	0
T22	194042	414	0	0
T23	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1547661	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1547661	0	0
T2	234004	3571	0	0
T3	96659	43	0	0
T4	361	7	0	0
T5	23141	210	0	0
T6	1101	35	0	0
T16	54789	0	0	0
T17	364998	34403	0	0
T18	29264	291	0	0
T19	250446	3493	0	0
T22	194042	2494	0	0
T23	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3080578	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3080578	0	0
T2	234004	3107	0	0
T3	96659	6	0	0
T4	361	7	0	0
T5	23141	94	0	0
T6	1101	11	0	0
T16	54789	0	0	0
T17	364998	25002	0	0
T18	29264	236	0	0
T19	250446	1681	0	0
T22	194042	1072	0	0
T23	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1562708	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1562708	0	0
T2	234004	3135	0	0
T3	96659	23	0	0
T4	361	5	0	0
T5	23141	388	0	0
T6	1101	15	0	0
T16	54789	1311	0	0
T17	364998	34863	0	0
T18	29264	265	0	0
T19	250446	1598	0	0
T22	194042	2348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2743969	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2743969	0	0
T2	234004	2648	0	0
T3	96659	6	0	0
T4	361	5	0	0
T5	23141	141	0	0
T6	1101	10	0	0
T16	54789	1040	0	0
T17	364998	22892	0	0
T18	29264	217	0	0
T19	250446	870	0	0
T22	194042	630	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1597392	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1597392	0	0
T2	234004	2293	0	0
T3	96659	48	0	0
T4	361	2	0	0
T5	23141	307	0	0
T6	1101	12	0	0
T16	54789	0	0	0
T17	364998	26448	0	0
T18	29264	205	0	0
T19	250446	1632	0	0
T22	194042	1188	0	0
T23	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2837874	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2837874	0	0
T2	234004	3117	0	0
T3	96659	11	0	0
T4	361	2	0	0
T5	23141	152	0	0
T6	1101	7	0	0
T16	54789	0	0	0
T17	364998	19417	0	0
T18	29264	166	0	0
T19	250446	866	0	0
T22	194042	553	0	0
T23	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1571229	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1571229	0	0
T1	330693	1140	0	0
T2	234004	2347	0	0
T3	96659	29	0	0
T4	361	4	0	0
T5	23141	295	0	0
T6	1101	7	0	0
T16	54789	1162	0	0
T17	364998	38324	0	0
T18	29264	215	0	0
T22	194042	3572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3117345	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3117345	0	0
T1	330693	89109	0	0
T2	234004	2972	0	0
T3	96659	9	0	0
T4	361	4	0	0
T5	23141	105	0	0
T6	1101	21	0	0
T16	54789	1010	0	0
T17	364998	28867	0	0
T18	29264	194	0	0
T22	194042	1928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1606258	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1606258	0	0
T2	234004	2964	0	0
T3	96659	18	0	0
T4	361	9	0	0
T5	23141	294	0	0
T6	1101	9	0	0
T16	54789	0	0	0
T17	364998	29235	0	0
T18	29264	371	0	0
T19	250446	1503	0	0
T22	194042	2112	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2696478	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2696478	0	0
T2	234004	1222	0	0
T3	96659	6	0	0
T4	361	9	0	0
T5	23141	121	0	0
T6	1101	12	0	0
T16	54789	0	0	0
T17	364998	29636	0	0
T18	29264	273	0	0
T19	250446	690	0	0
T22	194042	8	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1533903	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1533903	0	0
T1	330693	1166	0	0
T2	234004	93	0	0
T3	96659	37	0	0
T4	361	10	0	0
T5	23141	246	0	0
T6	1101	0	0	0
T16	54789	2065	0	0
T17	364998	39755	0	0
T18	29264	319	0	0
T19	0	5551	0	0
T22	194042	1739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3236982	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3236982	0	0
T1	330693	90417	0	0
T2	234004	509	0	0
T3	96659	11	0	0
T4	361	10	0	0
T5	23141	73	0	0
T6	1101	0	0	0
T16	54789	1029	0	0
T17	364998	29167	0	0
T18	29264	318	0	0
T19	0	2649	0	0
T22	194042	881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1541329	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1541329	0	0
T2	234004	1836	0	0
T3	96659	6	0	0
T4	361	7	0	0
T5	23141	276	0	0
T6	1101	31	0	0
T16	54789	1830	0	0
T17	364998	40477	0	0
T18	29264	200	0	0
T19	250446	3256	0	0
T22	194042	611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2745754	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2745754	0	0
T2	234004	1942	0	0
T3	96659	1	0	0
T4	361	7	0	0
T5	23141	171	0	0
T6	1101	9	0	0
T16	54789	745	0	0
T17	364998	26161	0	0
T18	29264	180	0	0
T19	250446	1513	0	0
T22	194042	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1520028	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1520028	0	0
T2	234004	892	0	0
T3	96659	46	0	0
T4	361	9	0	0
T5	23141	380	0	0
T6	1101	17	0	0
T16	54789	0	0	0
T17	364998	36091	0	0
T18	29264	230	0	0
T19	250446	1354	0	0
T22	194042	1174	0	0
T23	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2143569	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2143569	0	0
T2	234004	1583	0	0
T3	96659	9	0	0
T4	361	9	0	0
T5	23141	137	0	0
T6	1101	18	0	0
T16	54789	0	0	0
T17	364998	23908	0	0
T18	29264	189	0	0
T19	250446	710	0	0
T22	194042	539	0	0
T23	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1596177	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1596177	0	0
T1	330693	2755	0	0
T2	234004	2347	0	0
T3	96659	47	0	0
T4	361	4	0	0
T5	23141	269	0	0
T6	1101	0	0	0
T16	54789	1621	0	0
T17	364998	34743	0	0
T18	29264	437	0	0
T19	0	2023	0	0
T22	194042	1671	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2717363	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2717363	0	0
T1	330693	210295	0	0
T2	234004	2836	0	0
T3	96659	12	0	0
T4	361	4	0	0
T5	23141	80	0	0
T6	1101	0	0	0
T16	54789	823	0	0
T17	364998	25883	0	0
T18	29264	323	0	0
T19	0	925	0	0
T22	194042	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1606503	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1606503	0	0
T1	330693	949	0	0
T2	234004	1626	0	0
T3	96659	36	0	0
T4	361	3	0	0
T5	23141	321	0	0
T6	1101	9	0	0
T16	54789	0	0	0
T17	364998	40384	0	0
T18	29264	216	0	0
T19	0	1768	0	0
T22	194042	5685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	3310149	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	3310149	0	0
T1	330693	75887	0	0
T2	234004	2730	0	0
T3	96659	5	0	0
T4	361	3	0	0
T5	23141	121	0	0
T6	1101	16	0	0
T16	54789	0	0	0
T17	364998	27503	0	0
T18	29264	189	0	0
T19	0	767	0	0
T22	194042	1017	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	1601577	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	1601577	0	0
T2	234004	2155	0	0
T3	96659	0	0	0
T4	361	5	0	0
T5	23141	298	0	0
T6	1101	5	0	0
T16	54789	0	0	0
T17	364998	37932	0	0
T18	29264	250	0	0
T19	250446	1531	0	0
T22	194042	3403	0	0
T23	0	17	0	0
T24	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293196456	2647479	0	0
DepthKnown_A	293196456	293059618	0	0
RvalidKnown_A	293196456	293059618	0	0
WreadyKnown_A	293196456	293059618	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	2647479	0	0
T2	234004	1744	0	0
T3	96659	0	0	0
T4	361	5	0	0
T5	23141	143	0	0
T6	1101	10	0	0
T16	54789	0	0	0
T17	364998	26250	0	0
T18	29264	151	0	0
T19	250446	740	0	0
T22	194042	728	0	0
T23	0	17	0	0
T24	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293196456	293059618	0	0
T1	330693	330685	0	0
T2	234004	233975	0	0
T3	96659	96625	0	0
T4	361	352	0	0
T5	23141	23101	0	0
T6	1101	1072	0	0
T16	54789	54720	0	0
T17	364998	364995	0	0
T18	29264	29207	0	0
T22	194042	193969	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0