Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1686479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264787

1

T1

1

T2

379

T3

159

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	661206	1			T1	3		T2	890		T3	764
values[0x0]	630616	1			T2	913		T3	126		T5	6862
values[0x1]	659444	1			T1	8		T2	969		T3	686

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1306572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644694

1

T1

3

T2

890

T3

611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8169	1			T2	13		T3	5		T5	29
valid_sources[0x01]	7164	1			T1	1		T2	4		T3	4
valid_sources[0x02]	7257	1			T2	16		T3	4		T5	70
valid_sources[0x03]	7106	1			T2	6		T3	6		T5	74
valid_sources[0x04]	7617	1			T2	8		T3	8		T5	32
valid_sources[0x05]	7290	1			T2	13		T3	5		T5	87
valid_sources[0x06]	7717	1			T2	4		T3	5		T5	78
valid_sources[0x07]	6726	1			T2	19		T3	6		T5	89
valid_sources[0x08]	7046	1			T2	14		T3	9		T5	97
valid_sources[0x09]	7837	1			T2	9		T3	8		T5	63
valid_sources[0x0a]	7798	1			T2	4		T3	3		T5	56
valid_sources[0x0b]	8366	1			T2	17		T3	4		T5	129
valid_sources[0x0c]	7424	1			T2	6		T3	4		T5	47
valid_sources[0x0d]	7383	1			T2	13		T3	1		T5	60
valid_sources[0x0e]	7848	1			T2	11		T3	6		T5	39
valid_sources[0x0f]	6665	1			T2	11		T3	3		T5	44
valid_sources[0x10]	8157	1			T2	11		T3	8		T5	97
valid_sources[0x11]	8066	1			T2	22		T3	5		T5	136
valid_sources[0x12]	8071	1			T2	5		T3	5		T5	32
valid_sources[0x13]	7455	1			T2	12		T3	4		T5	31
valid_sources[0x14]	6707	1			T2	11		T3	9		T5	73
valid_sources[0x15]	8610	1			T2	18		T3	9		T5	130
valid_sources[0x16]	7502	1			T2	11		T3	2		T5	13
valid_sources[0x17]	8131	1			T2	3		T3	3		T5	96
valid_sources[0x18]	7371	1			T2	12		T3	7		T5	70
valid_sources[0x19]	7822	1			T2	4		T3	6		T5	100
valid_sources[0x1a]	7784	1			T2	8		T3	1		T5	41
valid_sources[0x1b]	6982	1			T2	4		T3	4		T5	28
valid_sources[0x1c]	7662	1			T2	7		T3	10		T5	120
valid_sources[0x1d]	7913	1			T2	14		T3	2		T5	49
valid_sources[0x1e]	7211	1			T2	18		T3	8		T5	66
valid_sources[0x1f]	7243	1			T2	11		T3	9		T5	137
valid_sources[0x20]	7547	1			T2	11		T3	4		T5	56
valid_sources[0x21]	7168	1			T2	22		T3	7		T5	139
valid_sources[0x22]	7556	1			T2	8		T3	8		T5	32
valid_sources[0x23]	7392	1			T2	9		T3	3		T5	50
valid_sources[0x24]	7227	1			T2	8		T3	6		T5	121
valid_sources[0x25]	7067	1			T1	1		T2	15		T3	5
valid_sources[0x26]	7908	1			T2	13		T3	8		T5	115
valid_sources[0x27]	7501	1			T2	17		T3	5		T5	71
valid_sources[0x28]	7673	1			T2	10		T3	7		T5	109
valid_sources[0x29]	7452	1			T2	8		T3	5		T5	48
valid_sources[0x2a]	7654	1			T2	14		T3	5		T5	117
valid_sources[0x2b]	6729	1			T2	6		T3	7		T5	88
valid_sources[0x2c]	7555	1			T2	7		T3	9		T5	152
valid_sources[0x2d]	7668	1			T2	10		T3	11		T5	174
valid_sources[0x2e]	8118	1			T2	8		T3	9		T5	41
valid_sources[0x2f]	7890	1			T2	6		T3	5		T5	65
valid_sources[0x30]	7043	1			T2	6		T3	4		T5	78
valid_sources[0x31]	8371	1			T2	7		T3	2		T5	48
valid_sources[0x32]	7685	1			T2	13		T3	3		T5	18
valid_sources[0x33]	7495	1			T2	19		T3	5		T5	162
valid_sources[0x34]	8236	1			T2	7		T3	4		T5	81
valid_sources[0x35]	7521	1			T2	10		T3	3		T5	87
valid_sources[0x36]	7034	1			T2	13		T3	4		T5	31
valid_sources[0x37]	8215	1			T2	9		T3	7		T5	66
valid_sources[0x38]	7586	1			T2	9		T3	12		T5	59
valid_sources[0x39]	7350	1			T2	20		T3	4		T5	45
valid_sources[0x3a]	7246	1			T2	18		T3	5		T5	53
valid_sources[0x3b]	9948	1			T2	6		T3	9		T5	99
valid_sources[0x3c]	6933	1			T2	15		T3	2		T5	42
valid_sources[0x3d]	7500	1			T2	7		T3	4		T5	118
valid_sources[0x3e]	7445	1			T2	11		T3	13		T5	110
valid_sources[0x3f]	7406	1			T2	6		T3	9		T5	108
valid_sources[0x40]	7304	1			T2	12		T3	6		T5	59
valid_sources[0x41]	7447	1			T2	7		T3	4		T5	93
valid_sources[0x42]	7671	1			T2	12		T3	8		T5	96
valid_sources[0x43]	7621	1			T1	1		T2	5		T3	12
valid_sources[0x44]	7704	1			T2	13		T3	4		T5	32
valid_sources[0x45]	7607	1			T2	15		T3	9		T5	60
valid_sources[0x46]	7910	1			T2	5		T3	3		T5	151
valid_sources[0x47]	7574	1			T2	18		T3	7		T5	68
valid_sources[0x48]	8198	1			T2	5		T3	13		T5	89
valid_sources[0x49]	7504	1			T2	5		T3	7		T5	86
valid_sources[0x4a]	7937	1			T2	10		T3	5		T5	26
valid_sources[0x4b]	7632	1			T2	19		T3	13		T5	37
valid_sources[0x4c]	7384	1			T2	5		T3	11		T5	144
valid_sources[0x4d]	8400	1			T2	12		T3	7		T5	86
valid_sources[0x4e]	7260	1			T2	4		T3	4		T5	18
valid_sources[0x4f]	7800	1			T2	15		T3	5		T5	144
valid_sources[0x50]	7277	1			T2	13		T3	4		T5	120
valid_sources[0x51]	7845	1			T2	13		T3	8		T5	80
valid_sources[0x52]	7385	1			T2	8		T3	4		T5	37
valid_sources[0x53]	7370	1			T2	11		T3	6		T5	100
valid_sources[0x54]	8127	1			T2	11		T3	6		T5	51
valid_sources[0x55]	7784	1			T2	15		T3	9		T5	57
valid_sources[0x56]	7144	1			T2	19		T3	6		T5	82
valid_sources[0x57]	7804	1			T2	18		T3	4		T5	71
valid_sources[0x58]	7151	1			T2	16		T3	5		T5	32
valid_sources[0x59]	8150	1			T2	12		T3	4		T5	27
valid_sources[0x5a]	7249	1			T2	11		T5	96		T19	82
valid_sources[0x5b]	6999	1			T2	11		T3	6		T5	83
valid_sources[0x5c]	8052	1			T2	15		T3	6		T5	65
valid_sources[0x5d]	6994	1			T2	7		T3	5		T5	85
valid_sources[0x5e]	7181	1			T2	5		T3	4		T5	12
valid_sources[0x5f]	9629	1			T2	14		T3	9		T5	33
valid_sources[0x60]	7899	1			T2	7		T3	9		T5	82
valid_sources[0x61]	8664	1			T2	5		T3	7		T5	35
valid_sources[0x62]	7006	1			T2	3		T3	4		T5	190
valid_sources[0x63]	7768	1			T2	9		T3	9		T5	126
valid_sources[0x64]	8400	1			T2	7		T3	16		T5	57
valid_sources[0x65]	7861	1			T2	14		T3	4		T5	88
valid_sources[0x66]	7708	1			T2	15		T3	6		T5	54
valid_sources[0x67]	6848	1			T2	11		T3	9		T5	119
valid_sources[0x68]	7925	1			T2	10		T3	6		T5	90
valid_sources[0x69]	7572	1			T2	13		T3	8		T5	68
valid_sources[0x6a]	7745	1			T2	11		T3	13		T5	51
valid_sources[0x6b]	7381	1			T2	12		T3	6		T5	79
valid_sources[0x6c]	7885	1			T2	13		T3	4		T5	58
valid_sources[0x6d]	7155	1			T2	10		T3	5		T5	62
valid_sources[0x6e]	7440	1			T2	21		T3	9		T5	67
valid_sources[0x6f]	8998	1			T2	4		T3	5		T5	107
valid_sources[0x70]	7782	1			T2	15		T3	5		T5	92
valid_sources[0x71]	8935	1			T2	8		T3	4		T5	68
valid_sources[0x72]	6820	1			T1	2		T2	8		T3	8
valid_sources[0x73]	7416	1			T2	7		T3	9		T5	112
valid_sources[0x74]	7540	1			T2	14		T3	11		T5	26
valid_sources[0x75]	8045	1			T2	8		T3	5		T5	102
valid_sources[0x76]	7210	1			T2	12		T3	5		T5	85
valid_sources[0x77]	8232	1			T2	9		T3	11		T5	61
valid_sources[0x78]	7262	1			T2	14		T3	2		T5	71
valid_sources[0x79]	7981	1			T2	4		T3	4		T5	51
valid_sources[0x7a]	7039	1			T2	10		T3	9		T5	57
valid_sources[0x7b]	7221	1			T2	14		T3	8		T5	86
valid_sources[0x7c]	8146	1			T1	1		T2	7		T3	2
valid_sources[0x7d]	7267	1			T2	9		T3	3		T5	136
valid_sources[0x7e]	7238	1			T2	11		T3	9		T5	104
valid_sources[0x7f]	6966	1			T2	10		T3	1		T5	50
valid_sources[0x80]	8362	1			T2	10		T3	1		T5	154

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27841

1

T2

41

T3

55

T5

295

values[0x0]

all_enables

biggest_size

209220

1

T2

303

T3

53

T5

2262

values[0x1]

all_enables

biggest_size

27726

1

T1

1

T2

35

T3

51