Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	361017789	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	361017789	0	0
T1	143950	1987	0	0
T2	316456	13610	0	0
T3	45289440	894849	0	0
T4	6033944	126056	0	0
T5	2428216	95605	0	0
T16	3910592	69513	0	0
T17	35896	576	0	0
T18	3768688	80562	0	0
T19	42528528	957286	0	0
T20	7642152	1843867	0	0
T21	347328	2689	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161224	159096	0	0
T2	316456	313432	0	0
T3	45289440	45151064	0	0
T4	6033944	6032488	0	0
T5	2428216	2322152	0	0
T16	3910592	3906728	0	0
T17	35896	32704	0	0
T18	3768688	3765048	0	0
T19	42528528	42471632	0	0
T20	7642152	7642096	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161224	159096	0	0
T2	316456	313432	0	0
T3	45289440	45151064	0	0
T4	6033944	6032488	0	0
T5	2428216	2322152	0	0
T16	3910592	3906728	0	0
T17	35896	32704	0	0
T18	3768688	3765048	0	0
T19	42528528	42471632	0	0
T20	7642152	7642096	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161224	159096	0	0
T2	316456	313432	0	0
T3	45289440	45151064	0	0
T4	6033944	6032488	0	0
T5	2428216	2322152	0	0
T16	3910592	3906728	0	0
T17	35896	32704	0	0
T18	3768688	3765048	0	0
T19	42528528	42471632	0	0
T20	7642152	7642096	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	130564443	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	130564443	0	0
T1	2879	826	0	0
T2	5651	5300	0	0
T3	808740	362216	0	0
T4	107749	58610	0	0
T5	43361	37024	0	0
T16	69832	68177	0	0
T17	641	144	0	0
T18	67298	36282	0	0
T19	759438	359063	0	0
T20	136467	743562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	94460176	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	94460176	0	0
T1	2879	343	0	0
T2	5651	2772	0	0
T3	808740	138558	0	0
T4	107749	12892	0	0
T5	43361	21072	0	0
T16	69832	339	0	0
T17	641	144	0	0
T18	67298	10491	0	0
T19	759438	211618	0	0
T20	136467	363196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1604603	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1604603	0	0
T1	2879	13	0	0
T2	5651	108	0	0
T3	808740	10353	0	0
T4	107749	2536	0	0
T5	43361	854	0	0
T16	69832	12	0	0
T17	641	8	0	0
T18	67298	775	0	0
T19	759438	7069	0	0
T20	136467	15731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	4605620	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	4605620	0	0
T1	2879	2	0	0
T2	5651	108	0	0
T3	808740	5324	0	0
T4	107749	1963	0	0
T5	43361	854	0	0
T16	69832	3	0	0
T17	641	8	0	0
T18	67298	357	0	0
T19	759438	6688	0	0
T20	136467	17413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1560822	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1560822	0	0
T1	2879	26	0	0
T2	5651	118	0	0
T3	808740	8413	0	0
T4	107749	1166	0	0
T5	43361	851	0	0
T16	69832	15	0	0
T17	641	4	0	0
T18	67298	819	0	0
T19	759438	6011	0	0
T20	136467	13710	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3004801	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3004801	0	0
T1	2879	16	0	0
T2	5651	118	0	0
T3	808740	4409	0	0
T4	107749	415	0	0
T5	43361	849	0	0
T16	69832	4	0	0
T17	641	4	0	0
T18	67298	432	0	0
T19	759438	6445	0	0
T20	136467	11993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1571242	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1571242	0	0
T1	2879	11	0	0
T2	5651	93	0	0
T3	808740	9714	0	0
T4	107749	1370	0	0
T5	43361	519	0	0
T16	69832	51	0	0
T17	641	2	0	0
T18	67298	761	0	0
T19	759438	9136	0	0
T20	136467	11795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	2852437	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	2852437	0	0
T1	2879	1	0	0
T2	5651	93	0	0
T3	808740	5051	0	0
T4	107749	183	0	0
T5	43361	519	0	0
T16	69832	9	0	0
T17	641	2	0	0
T18	67298	341	0	0
T19	759438	9874	0	0
T20	136467	13319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1593562	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1593562	0	0
T1	2879	49	0	0
T2	5651	108	0	0
T3	808740	16671	0	0
T4	107749	160	0	0
T5	43361	739	0	0
T16	69832	27	0	0
T17	641	2	0	0
T18	67298	716	0	0
T19	759438	10818	0	0
T20	136467	12592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	2822936	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	2822936	0	0
T1	2879	18	0	0
T2	5651	108	0	0
T3	808740	7977	0	0
T4	107749	1	0	0
T5	43361	739	0	0
T16	69832	6	0	0
T17	641	2	0	0
T18	67298	408	0	0
T19	759438	10683	0	0
T20	136467	14463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1546233	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1546233	0	0
T1	2879	24	0	0
T2	5651	126	0	0
T3	808740	10837	0	0
T4	107749	2802	0	0
T5	43361	740	0	0
T16	69832	15	0	0
T17	641	7	0	0
T18	67298	855	0	0
T19	759438	11319	0	0
T20	136467	11804	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3553649	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3553649	0	0
T1	2879	2	0	0
T2	5651	126	0	0
T3	808740	5267	0	0
T4	107749	1011	0	0
T5	43361	740	0	0
T16	69832	3	0	0
T17	641	7	0	0
T18	67298	356	0	0
T19	759438	11532	0	0
T20	136467	11027	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1551441	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1551441	0	0
T2	5651	103	0	0
T3	808740	8151	0	0
T4	107749	2032	0	0
T5	43361	516	0	0
T16	69832	12	0	0
T17	641	5	0	0
T18	67298	855	0	0
T19	759438	4379	0	0
T20	136467	18240	0	0
T21	57888	678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3150575	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3150575	0	0
T2	5651	103	0	0
T3	808740	4060	0	0
T4	107749	50	0	0
T5	43361	516	0	0
T16	69832	3	0	0
T17	641	5	0	0
T18	67298	439	0	0
T19	759438	4270	0	0
T20	136467	17292	0	0
T21	57888	243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1563064	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1563064	0	0
T1	2879	1	0	0
T2	5651	130	0	0
T3	808740	7526	0	0
T4	107749	1195	0	0
T5	43361	516	0	0
T16	69832	32	0	0
T17	641	7	0	0
T18	67298	1060	0	0
T19	759438	8318	0	0
T20	136467	12273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	4144129	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	4144129	0	0
T1	2879	2	0	0
T2	5651	130	0	0
T3	808740	4160	0	0
T4	107749	363	0	0
T5	43361	516	0	0
T16	69832	6	0	0
T17	641	7	0	0
T18	67298	432	0	0
T19	759438	8479	0	0
T20	136467	12212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1566966	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1566966	0	0
T1	2879	29	0	0
T2	5651	88	0	0
T3	808740	7950	0	0
T4	107749	367	0	0
T5	43361	735	0	0
T16	69832	18	0	0
T17	641	4	0	0
T18	67298	917	0	0
T19	759438	5886	0	0
T20	136467	12776	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3361341	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3361341	0	0
T1	2879	47	0	0
T2	5651	88	0	0
T3	808740	4947	0	0
T4	107749	405	0	0
T5	43361	735	0	0
T16	69832	202	0	0
T17	641	4	0	0
T18	67298	379	0	0
T19	759438	6016	0	0
T20	136467	12782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1576479	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1576479	0	0
T1	2879	76	0	0
T2	5651	97	0	0
T3	808740	12712	0	0
T4	107749	3168	0	0
T5	43361	868	0	0
T16	69832	21	0	0
T17	641	7	0	0
T18	67298	848	0	0
T19	759438	6456	0	0
T20	136467	14246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3629590	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3629590	0	0
T1	2879	28	0	0
T2	5651	97	0	0
T3	808740	6174	0	0
T4	107749	794	0	0
T5	43361	868	0	0
T16	69832	5	0	0
T17	641	7	0	0
T18	67298	419	0	0
T19	759438	6591	0	0
T20	136467	14953	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1621308	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1621308	0	0
T1	2879	7	0	0
T2	5651	97	0	0
T3	808740	6976	0	0
T4	107749	429	0	0
T5	43361	559	0	0
T16	69832	33	0	0
T17	641	8	0	0
T18	67298	920	0	0
T19	759438	5635	0	0
T20	136467	14332	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3816055	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3816055	0	0
T1	2879	1	0	0
T2	5651	97	0	0
T3	808740	3541	0	0
T4	107749	1	0	0
T5	43361	559	0	0
T16	69832	6	0	0
T17	641	8	0	0
T18	67298	359	0	0
T19	759438	5864	0	0
T20	136467	15054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1497909	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1497909	0	0
T1	2879	30	0	0
T2	5651	97	0	0
T3	808740	8086	0	0
T4	107749	2028	0	0
T5	43361	1068	0	0
T16	69832	5	0	0
T17	641	8	0	0
T18	67298	948	0	0
T19	759438	6257	0	0
T20	136467	10305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3535588	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3535588	0	0
T1	2879	21	0	0
T2	5651	97	0	0
T3	808740	4287	0	0
T4	107749	109	0	0
T5	43361	1068	0	0
T16	69832	1	0	0
T17	641	8	0	0
T18	67298	385	0	0
T19	759438	6347	0	0
T20	136467	9202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1606296	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1606296	0	0
T1	2879	16	0	0
T2	5651	112	0	0
T3	808740	9280	0	0
T4	107749	279	0	0
T5	43361	534	0	0
T16	69832	28	0	0
T17	641	2	0	0
T18	67298	881	0	0
T19	759438	4563	0	0
T20	136467	14089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3775130	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3775130	0	0
T1	2879	12	0	0
T2	5651	112	0	0
T3	808740	4736	0	0
T4	107749	619	0	0
T5	43361	534	0	0
T16	69832	5	0	0
T17	641	2	0	0
T18	67298	360	0	0
T19	759438	4242	0	0
T20	136467	15146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1589401	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1589401	0	0
T1	2879	10	0	0
T2	5651	105	0	0
T3	808740	5898	0	0
T4	107749	2754	0	0
T5	43361	543	0	0
T16	69832	20	0	0
T17	641	3	0	0
T18	67298	889	0	0
T19	759438	8699	0	0
T20	136467	16861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	2985640	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	2985640	0	0
T1	2879	13	0	0
T2	5651	105	0	0
T3	808740	3194	0	0
T4	107749	964	0	0
T5	43361	543	0	0
T16	69832	5	0	0
T17	641	3	0	0
T18	67298	333	0	0
T19	759438	8744	0	0
T20	136467	11968	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1589142	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1589142	0	0
T1	2879	29	0	0
T2	5651	112	0	0
T3	808740	8768	0	0
T4	107749	1525	0	0
T5	43361	971	0	0
T16	69832	49	0	0
T17	641	7	0	0
T18	67298	1042	0	0
T19	759438	6613	0	0
T20	136467	13253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	4277477	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	4277477	0	0
T1	2879	7	0	0
T2	5651	112	0	0
T3	808740	5435	0	0
T4	107749	1085	0	0
T5	43361	970	0	0
T16	69832	10	0	0
T17	641	7	0	0
T18	67298	479	0	0
T19	759438	6452	0	0
T20	136467	12841	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1515324	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1515324	0	0
T1	2879	25	0	0
T2	5651	101	0	0
T3	808740	10337	0	0
T4	107749	981	0	0
T5	43361	734	0	0
T16	69832	10	0	0
T17	641	8	0	0
T18	67298	836	0	0
T19	759438	4419	0	0
T20	136467	12264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3508175	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3508175	0	0
T1	2879	6	0	0
T2	5651	101	0	0
T3	808740	5733	0	0
T4	107749	269	0	0
T5	43361	734	0	0
T16	69832	3	0	0
T17	641	8	0	0
T18	67298	472	0	0
T19	759438	4290	0	0
T20	136467	12228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1599458	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1599458	0	0
T2	5651	122	0	0
T3	808740	7320	0	0
T4	107749	729	0	0
T5	43361	527	0	0
T16	69832	16	0	0
T17	641	3	0	0
T18	67298	841	0	0
T19	759438	13658	0	0
T20	136467	14539	0	0
T21	57888	628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3656840	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3656840	0	0
T2	5651	122	0	0
T3	808740	3907	0	0
T4	107749	3	0	0
T5	43361	527	0	0
T16	69832	3	0	0
T17	641	3	0	0
T18	67298	381	0	0
T19	759438	13837	0	0
T20	136467	12754	0	0
T21	57888	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1625476	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1625476	0	0
T1	2879	53	0	0
T2	5651	107	0	0
T3	808740	11011	0	0
T4	107749	1607	0	0
T5	43361	946	0	0
T16	69832	34	0	0
T17	641	5	0	0
T18	67298	837	0	0
T19	759438	10464	0	0
T20	136467	12065	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3259327	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3259327	0	0
T1	2879	13	0	0
T2	5651	107	0	0
T3	808740	7260	0	0
T4	107749	471	0	0
T5	43361	945	0	0
T16	69832	7	0	0
T17	641	5	0	0
T18	67298	418	0	0
T19	759438	10247	0	0
T20	136467	13479	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1558401	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1558401	0	0
T1	2879	18	0	0
T2	5651	97	0	0
T3	808740	8659	0	0
T4	107749	2547	0	0
T5	43361	533	0	0
T16	69832	15	0	0
T17	641	8	0	0
T18	67298	745	0	0
T19	759438	7032	0	0
T20	136467	14429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3463842	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3463842	0	0
T1	2879	8	0	0
T2	5651	97	0	0
T3	808740	4450	0	0
T4	107749	781	0	0
T5	43361	533	0	0
T16	69832	7	0	0
T17	641	8	0	0
T18	67298	338	0	0
T19	759438	7889	0	0
T20	136467	13879	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1553658	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1553658	0	0
T1	2879	32	0	0
T2	5651	94	0	0
T3	808740	6423	0	0
T4	107749	1402	0	0
T5	43361	788	0	0
T16	69832	39	0	0
T17	641	5	0	0
T18	67298	812	0	0
T19	759438	7991	0	0
T20	136467	15870	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3791904	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3791904	0	0
T1	2879	3	0	0
T2	5651	94	0	0
T3	808740	3543	0	0
T4	107749	546	0	0
T5	43361	788	0	0
T16	69832	7	0	0
T17	641	5	0	0
T18	67298	360	0	0
T19	759438	8354	0	0
T20	136467	15534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1581686	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1581686	0	0
T1	2879	22	0	0
T2	5651	84	0	0
T3	808740	12703	0	0
T4	107749	2393	0	0
T5	43361	1175	0	0
T16	69832	17	0	0
T17	641	8	0	0
T18	67298	839	0	0
T19	759438	5373	0	0
T20	136467	17189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3844767	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3844767	0	0
T1	2879	13	0	0
T2	5651	84	0	0
T3	808740	6604	0	0
T4	107749	394	0	0
T5	43361	1172	0	0
T16	69832	5	0	0
T17	641	8	0	0
T18	67298	433	0	0
T19	759438	5543	0	0
T20	136467	15708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1546424	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1546424	0	0
T1	2879	21	0	0
T2	5651	102	0	0
T3	808740	10320	0	0
T4	107749	1223	0	0
T5	43361	557	0	0
T16	69832	23	0	0
T17	641	2	0	0
T18	67298	731	0	0
T19	759438	4340	0	0
T20	136467	15206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	2567712	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	2567712	0	0
T1	2879	19	0	0
T2	5651	102	0	0
T3	808740	4953	0	0
T4	107749	525	0	0
T5	43361	556	0	0
T16	69832	6	0	0
T17	641	2	0	0
T18	67298	243	0	0
T19	759438	4254	0	0
T20	136467	10194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1563220	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1563220	0	0
T1	2879	19	0	0
T2	5651	90	0	0
T3	808740	10104	0	0
T4	107749	2890	0	0
T5	43361	573	0	0
T16	69832	48	0	0
T17	641	8	0	0
T18	67298	850	0	0
T19	759438	5064	0	0
T20	136467	11622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3474546	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3474546	0	0
T1	2879	2	0	0
T2	5651	90	0	0
T3	808740	4926	0	0
T4	107749	332	0	0
T5	43361	573	0	0
T16	69832	8	0	0
T17	641	8	0	0
T18	67298	343	0	0
T19	759438	5245	0	0
T20	136467	11572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1592682	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1592682	0	0
T1	2879	29	0	0
T2	5651	79	0	0
T3	808740	7507	0	0
T4	107749	1355	0	0
T5	43361	523	0	0
T16	69832	10	0	0
T17	641	7	0	0
T18	67298	888	0	0
T19	759438	9669	0	0
T20	136467	14293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3019115	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3019115	0	0
T1	2879	5	0	0
T2	5651	79	0	0
T3	808740	3949	0	0
T4	107749	802	0	0
T5	43361	522	0	0
T16	69832	4	0	0
T17	641	7	0	0
T18	67298	366	0	0
T19	759438	9742	0	0
T20	136467	12337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1594799	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1594799	0	0
T1	2879	1	0	0
T2	5651	87	0	0
T3	808740	14337	0	0
T4	107749	278	0	0
T5	43361	552	0	0
T16	69832	50	0	0
T17	641	3	0	0
T18	67298	933	0	0
T19	759438	8161	0	0
T20	136467	18264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	2689070	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	2689070	0	0
T1	2879	5	0	0
T2	5651	87	0	0
T3	808740	7351	0	0
T4	107749	1	0	0
T5	43361	552	0	0
T16	69832	8	0	0
T17	641	3	0	0
T18	67298	404	0	0
T19	759438	8657	0	0
T20	136467	14979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1620377	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1620377	0	0
T2	5651	96	0	0
T3	808740	9137	0	0
T4	107749	2255	0	0
T5	43361	537	0	0
T16	69832	32	0	0
T17	641	1	0	0
T18	67298	858	0	0
T19	759438	4109	0	0
T20	136467	9677	0	0
T21	57888	606	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3219511	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3219511	0	0
T2	5651	96	0	0
T3	808740	4560	0	0
T4	107749	228	0	0
T5	43361	537	0	0
T16	69832	6	0	0
T17	641	1	0	0
T18	67298	328	0	0
T19	759438	4179	0	0
T20	136467	13855	0	0
T21	57888	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1544016	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1544016	0	0
T1	2879	4	0	0
T2	5651	117	0	0
T3	808740	8564	0	0
T4	107749	2102	0	0
T5	43361	783	0	0
T16	69832	3	0	0
T17	641	5	0	0
T18	67298	821	0	0
T19	759438	5854	0	0
T20	136467	12964	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	3332563	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	3332563	0	0
T1	2879	7	0	0
T2	5651	117	0	0
T3	808740	4481	0	0
T4	107749	512	0	0
T5	43361	783	0	0
T16	69832	1	0	0
T17	641	5	0	0
T18	67298	424	0	0
T19	759438	6288	0	0
T20	136467	15300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	1603833	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	1603833	0	0
T1	2879	17	0	0
T2	5651	99	0	0
T3	808740	9796	0	0
T4	107749	89	0	0
T5	43361	518	0	0
T16	69832	24	0	0
T17	641	7	0	0
T18	67298	1022	0	0
T19	759438	4276	0	0
T20	136467	13524	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328572284	4113008	0	0
DepthKnown_A	328572284	328446973	0	0
RvalidKnown_A	328572284	328446973	0	0
WreadyKnown_A	328572284	328446973	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	4113008	0	0
T1	2879	5	0	0
T2	5651	99	0	0
T3	808740	6243	0	0
T4	107749	65	0	0
T5	43361	518	0	0
T16	69832	5	0	0
T17	641	7	0	0
T18	67298	501	0	0
T19	759438	4284	0	0
T20	136467	11712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328572284	328446973	0	0
T1	2879	2841	0	0
T2	5651	5597	0	0
T3	808740	806269	0	0
T4	107749	107723	0	0
T5	43361	41467	0	0
T16	69832	69763	0	0
T17	641	584	0	0
T18	67298	67233	0	0
T19	759438	758422	0	0
T20	136467	136466	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0