Module Definition
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Module : tlul_socket_1n
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.49 100.00 93.97 100.00 100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_s1n_28 98.49 100.00 93.97 100.00 100.00



Module Instance : tb.dut.u_s1n_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.49 100.00 93.97 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.88 100.00 95.53 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
fifo_h 100.00 100.00 100.00 100.00 100.00
gen_dfifo[0].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[10].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[11].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[12].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[13].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[14].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[15].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[16].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[17].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[18].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[19].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[1].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[20].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[21].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[22].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[23].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[24].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[25].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[26].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[2].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[3].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[4].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[5].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[6].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[7].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[8].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[9].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_err_resp.err_resp 100.00 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_socket_1n
Line No.TotalCoveredPercent
TOTAL340340100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
ALWAYS11699100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
ALWAYS18066100.00
CONT_ASSIGN18911100.00
ALWAYS19244100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24111100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 1 1
113 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
MISSING_ELSE
123 1 1
124 1 1
125 1 1
MISSING_ELSE
132 1 1
145 1 1
155 27 27
157 27 27
158 27 27
159 27 27
160 27 27
161 27 27
162 27 27
163 27 27
164 27 27
167 27 27
171 27 27
180 1 1
181 1 1
183 2 2
MISSING_ELSE
185 2 2
MISSING_ELSE
189 1 1
192 1 1
193 1 1
194 2 2
MISSING_ELSE
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
230 1 1
231 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1


Cond Coverage for Module : tlul_socket_1n
TotalCoveredPercent
Conditions34832793.97
Logical34832793.97
Non-Logical00
Event00

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(0))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(1))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(2))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(3))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(4)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(4))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(5)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT2,T3,T5

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(5))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       155
 EXPRESSION ((dev_select_t == 5'(6)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(6))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(7)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(7))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(8)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(8))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(9)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(9))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(10)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(10))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(11)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(11))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(12)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(12))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(13)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(13))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(14)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(14))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(15)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT2,T3,T5

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(15))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       155
 EXPRESSION ((dev_select_t == 5'(16)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(16))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(17)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(17))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(18)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(18))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(19)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(19))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(20)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(20))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(21)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(21))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(22)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(22))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(23)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(23))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(24)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT2,T3,T5

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(24))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       155
 EXPRESSION ((dev_select_t == 5'(25)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(25))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(26)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(26))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[4].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[5].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[6].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[7].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[8].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[9].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[10].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[11].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[12].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[13].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[14].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[15].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT12
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[16].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[17].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[18].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[19].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[20].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[21].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT14,T15,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[22].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[23].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[24].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[25].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[26].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       164
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       164
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[24].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       164
 EXPRESSION (gen_u_o[25].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[26].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       167
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       167
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[24].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       167
 EXPRESSION (gen_u_o[25].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[26].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 5'(idx))
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 5'(idx))
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------
-1--2--3-StatusTests
011CoveredT16,T17,T18
101CoveredT1,T2,T3
110CoveredT1,T3,T5
111CoveredT1,T2,T3

Branch Coverage for Module : tlul_socket_1n
Line No.TotalCoveredPercent
Branches 119 119 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
IF 116 5 5 100.00
IF 183 2 2 100.00
IF 185 2 2 100.00
IF 194 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[4].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[4].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[5].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[5].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[6].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[6].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[7].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[7].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[8].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[8].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[9].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[9].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[10].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[10].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[11].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[11].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[12].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[12].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[13].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[13].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[14].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[14].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[15].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[15].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[16].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[16].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[17].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[17].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[18].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[18].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[19].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[19].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[20].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[20].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[21].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[21].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[22].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[22].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[23].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[23].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[24].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[24].dev_select) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[25].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[25].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[26].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[26].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 119 if (accept_t_req) -3-: 120 if ((!accept_t_rsp)) -4-: 124 if (accept_t_rsp)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Covered T2,T3,T5
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if ((dev_select_t == 5'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 if (hold_all_requests)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((dev_select_outstanding == 5'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_socket_1n
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NotOverflowed_A 328572284 328446973 0 0
maxN 900 900 0 0


NotOverflowed_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 328572284 328446973 0 0
T1 2879 2841 0 0
T2 5651 5597 0 0
T3 808740 806269 0 0
T4 107749 107723 0 0
T5 43361 41467 0 0
T16 69832 69763 0 0
T17 641 584 0 0
T18 67298 67233 0 0
T19 759438 758422 0 0
T20 136467 136466 0 0

maxN
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%