Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1745917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

274925

1

T1

2515

T2

351

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	682851	1			T1	6310		T2	911		T3	50
values[0x0]	654558	1			T1	6184		T2	843		T3	52
values[0x1]	683433	1			T1	6225		T2	869		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1354444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

666398

1

T1

6160

T2

848

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7604	1			T1	78		T2	11		T3	2
valid_sources[0x01]	7472	1			T1	79		T2	9		T23	20
valid_sources[0x02]	8065	1			T1	76		T2	20		T3	1
valid_sources[0x03]	7919	1			T1	90		T2	2		T23	2
valid_sources[0x04]	7694	1			T1	72		T2	34		T3	1
valid_sources[0x05]	8250	1			T1	74		T2	1		T5	10
valid_sources[0x06]	7927	1			T1	64		T2	13		T5	14
valid_sources[0x07]	7936	1			T1	82		T2	10		T5	5
valid_sources[0x08]	8087	1			T1	54		T2	7		T3	1
valid_sources[0x09]	8208	1			T1	60		T2	34		T3	1
valid_sources[0x0a]	7202	1			T1	72		T2	11		T5	1
valid_sources[0x0b]	7720	1			T1	52		T2	10		T5	13
valid_sources[0x0c]	8086	1			T1	62		T2	12		T6	1
valid_sources[0x0d]	7417	1			T1	81		T2	9		T3	1
valid_sources[0x0e]	7286	1			T1	92		T2	17		T5	2
valid_sources[0x0f]	6759	1			T1	58		T2	4		T3	1
valid_sources[0x10]	7289	1			T1	70		T2	11		T3	1
valid_sources[0x11]	8017	1			T1	91		T2	9		T23	4
valid_sources[0x12]	7857	1			T1	54		T2	3		T3	1
valid_sources[0x13]	7187	1			T1	66		T2	2		T5	8
valid_sources[0x14]	7249	1			T1	57		T2	16		T6	3
valid_sources[0x15]	7924	1			T1	59		T2	20		T4	1
valid_sources[0x16]	7753	1			T1	77		T2	14		T5	1
valid_sources[0x17]	8758	1			T1	53		T2	16		T3	2
valid_sources[0x18]	7879	1			T1	66		T2	14		T6	1
valid_sources[0x19]	6975	1			T1	57		T2	1		T3	1
valid_sources[0x1a]	8179	1			T1	66		T2	5		T18	102
valid_sources[0x1b]	7141	1			T1	48		T2	27		T5	2
valid_sources[0x1c]	8131	1			T1	55		T2	18		T22	78
valid_sources[0x1d]	7724	1			T1	83		T2	14		T6	2
valid_sources[0x1e]	6876	1			T1	59		T2	9		T6	1
valid_sources[0x1f]	7321	1			T1	77		T2	14		T23	2
valid_sources[0x20]	7671	1			T1	81		T2	14		T3	1
valid_sources[0x21]	7363	1			T1	83		T2	7		T6	1
valid_sources[0x22]	7983	1			T1	98		T2	16		T4	1
valid_sources[0x23]	8817	1			T1	85		T2	9		T3	1
valid_sources[0x24]	7350	1			T1	122		T2	8		T3	2
valid_sources[0x25]	8639	1			T1	56		T2	10		T3	3
valid_sources[0x26]	7427	1			T1	56		T2	3		T6	1
valid_sources[0x27]	7441	1			T1	64		T2	2		T5	12
valid_sources[0x28]	7161	1			T1	74		T2	6		T24	1
valid_sources[0x29]	7514	1			T1	47		T2	3		T3	1
valid_sources[0x2a]	8150	1			T1	80		T2	14		T23	1
valid_sources[0x2b]	8252	1			T1	55		T2	19		T3	1
valid_sources[0x2c]	8448	1			T1	86		T2	18		T5	1
valid_sources[0x2d]	7760	1			T1	61		T2	10		T3	2
valid_sources[0x2e]	7626	1			T1	84		T2	21		T5	3
valid_sources[0x2f]	8437	1			T1	127		T2	4		T22	394
valid_sources[0x30]	7893	1			T1	63		T2	10		T5	5
valid_sources[0x31]	7086	1			T1	85		T2	4		T6	1
valid_sources[0x32]	8682	1			T1	86		T2	9		T3	2
valid_sources[0x33]	7452	1			T1	73		T2	5		T5	25
valid_sources[0x34]	7443	1			T1	54		T2	9		T3	1
valid_sources[0x35]	7015	1			T1	63		T2	14		T5	10
valid_sources[0x36]	7650	1			T1	59		T2	17		T3	3
valid_sources[0x37]	7481	1			T1	59		T2	4		T3	1
valid_sources[0x38]	7257	1			T1	74		T2	6		T3	2
valid_sources[0x39]	7425	1			T1	57		T2	2		T3	1
valid_sources[0x3a]	8709	1			T1	70		T2	15		T23	6
valid_sources[0x3b]	7895	1			T1	45		T2	9		T3	4
valid_sources[0x3c]	7625	1			T1	91		T2	19		T3	1
valid_sources[0x3d]	7897	1			T1	84		T2	6		T3	1
valid_sources[0x3e]	8758	1			T1	95		T2	2		T6	1
valid_sources[0x3f]	7148	1			T1	101		T2	7		T3	1
valid_sources[0x40]	8466	1			T1	98		T2	3		T25	2
valid_sources[0x41]	9193	1			T1	45		T2	8		T5	4
valid_sources[0x42]	7825	1			T1	103		T2	21		T5	38
valid_sources[0x43]	7569	1			T1	52		T2	14		T3	1
valid_sources[0x44]	7537	1			T1	142		T2	4		T22	65
valid_sources[0x45]	8841	1			T1	109		T2	10		T5	28
valid_sources[0x46]	8127	1			T1	75		T2	11		T5	1
valid_sources[0x47]	11909	1			T1	66		T2	20		T3	1
valid_sources[0x48]	7567	1			T1	68		T2	7		T24	2
valid_sources[0x49]	7663	1			T1	87		T2	8		T25	8
valid_sources[0x4a]	7723	1			T1	74		T2	7		T4	1
valid_sources[0x4b]	7500	1			T1	61		T2	10		T3	1
valid_sources[0x4c]	7331	1			T1	94		T2	3		T5	2
valid_sources[0x4d]	7054	1			T1	92		T2	15		T6	2
valid_sources[0x4e]	8602	1			T1	62		T2	8		T4	1
valid_sources[0x4f]	8464	1			T1	52		T2	1		T6	1
valid_sources[0x50]	8447	1			T1	68		T2	9		T5	10
valid_sources[0x51]	7561	1			T1	70		T2	19		T5	33
valid_sources[0x52]	9086	1			T1	74		T2	10		T3	3
valid_sources[0x53]	7222	1			T1	81		T2	8		T3	1
valid_sources[0x54]	7209	1			T1	48		T2	11		T5	5
valid_sources[0x55]	7714	1			T1	55		T2	4		T3	1
valid_sources[0x56]	7018	1			T1	70		T2	6		T23	1
valid_sources[0x57]	8675	1			T1	47		T2	18		T23	6
valid_sources[0x58]	8197	1			T1	74		T2	3		T23	3
valid_sources[0x59]	7290	1			T1	75		T2	9		T6	1
valid_sources[0x5a]	7766	1			T1	72		T2	16		T3	1
valid_sources[0x5b]	8336	1			T1	83		T2	9		T6	1
valid_sources[0x5c]	7905	1			T1	56		T2	6		T3	1
valid_sources[0x5d]	7721	1			T1	87		T2	30		T3	2
valid_sources[0x5e]	8049	1			T1	76		T2	14		T3	1
valid_sources[0x5f]	7334	1			T1	44		T2	15		T5	1
valid_sources[0x60]	7325	1			T1	91		T2	29		T3	1
valid_sources[0x61]	7953	1			T1	76		T2	12		T3	1
valid_sources[0x62]	7991	1			T1	100		T2	6		T5	7
valid_sources[0x63]	7494	1			T1	59		T2	6		T5	29
valid_sources[0x64]	7711	1			T1	73		T2	1		T3	1
valid_sources[0x65]	8179	1			T1	65		T2	14		T5	1
valid_sources[0x66]	7290	1			T1	82		T2	2		T3	1
valid_sources[0x67]	7732	1			T1	81		T2	18		T18	108
valid_sources[0x68]	7893	1			T1	98		T2	2		T5	9
valid_sources[0x69]	7398	1			T1	59		T2	7		T3	1
valid_sources[0x6a]	7700	1			T1	83		T2	3		T3	1
valid_sources[0x6b]	7290	1			T1	80		T2	8		T4	1
valid_sources[0x6c]	8506	1			T1	72		T2	7		T5	20
valid_sources[0x6d]	7033	1			T1	99		T2	3		T5	28
valid_sources[0x6e]	10191	1			T1	82		T2	9		T24	2
valid_sources[0x6f]	8149	1			T1	67		T2	20		T3	1
valid_sources[0x70]	8348	1			T1	72		T2	13		T5	6
valid_sources[0x71]	9258	1			T1	68		T2	13		T19	1
valid_sources[0x72]	8483	1			T1	90		T2	11		T3	2
valid_sources[0x73]	8104	1			T1	50		T2	11		T23	4
valid_sources[0x74]	7524	1			T1	87		T2	4		T6	1
valid_sources[0x75]	7817	1			T1	87		T2	6		T3	1
valid_sources[0x76]	7343	1			T1	48		T2	7		T24	3
valid_sources[0x77]	7767	1			T1	64		T2	9		T3	2
valid_sources[0x78]	8374	1			T1	72		T2	13		T3	1
valid_sources[0x79]	7314	1			T1	59		T2	14		T3	1
valid_sources[0x7a]	7600	1			T1	82		T2	4		T6	3
valid_sources[0x7b]	7772	1			T1	53		T2	3		T3	1
valid_sources[0x7c]	7381	1			T1	75		T2	17		T23	5
valid_sources[0x7d]	7253	1			T1	65		T2	3		T5	9
valid_sources[0x7e]	7598	1			T1	65		T2	6		T3	2
valid_sources[0x7f]	7664	1			T1	50		T2	9		T3	1
valid_sources[0x80]	8068	1			T1	92		T2	5		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29016

1

T1

255

T2

37

T4

2

values[0x0]

all_enables

biggest_size

216802

1

T1

2033

T2

284

T3

13

values[0x1]

all_enables

biggest_size

29107

1

T1

227

T2

30

T3

4