Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	332893748	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332893748	0	0
T1	2176328	87352	0	0
T2	301112	12869	0	0
T3	32144	716	0	0
T4	949760	18146	0	0
T5	1322216	27683	0	0
T6	9208304	239444	0	0
T18	217000	13671	0	0
T19	5337192	175973	0	0
T20	313320	7383	0	0
T21	826392	20471	0	0
T22	0	3678	0	0
T23	0	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2176328	2100448	0	0
T2	301112	298032	0	0
T3	32144	29736	0	0
T4	949760	948304	0	0
T5	1322216	1319920	0	0
T6	9208304	9206960	0	0
T18	217000	213864	0	0
T19	5337192	5333776	0	0
T20	313320	312536	0	0
T21	826392	823928	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2176328	2100448	0	0
T2	301112	298032	0	0
T3	32144	29736	0	0
T4	949760	948304	0	0
T5	1322216	1319920	0	0
T6	9208304	9206960	0	0
T18	217000	213864	0	0
T19	5337192	5333776	0	0
T20	313320	312536	0	0
T21	826392	823928	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2176328	2100448	0	0
T2	301112	298032	0	0
T3	32144	29736	0	0
T4	949760	948304	0	0
T5	1322216	1319920	0	0
T6	9208304	9206960	0	0
T18	217000	213864	0	0
T19	5337192	5333776	0	0
T20	313320	312536	0	0
T21	826392	823928	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	119545764	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	119545764	0	0
T1	38863	35249	0	0
T2	5377	5000	0	0
T3	574	275	0	0
T4	16960	7979	0	0
T5	23611	12216	0	0
T6	164434	97980	0	0
T18	3875	3419	0	0
T19	95307	92931	0	0
T20	5595	2936	0	0
T21	14757	8726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	88235692	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	88235692	0	0
T1	38863	18719	0	0
T2	5377	2623	0	0
T3	574	147	0	0
T4	16960	2410	0	0
T5	23611	3740	0	0
T6	164434	48605	0	0
T18	3875	3418	0	0
T19	95307	41276	0	0
T20	5595	1539	0	0
T21	14757	4020	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1421085	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1421085	0	0
T1	38863	474	0	0
T2	5377	99	0	0
T3	574	6	0	0
T4	16960	180	0	0
T5	23611	298	0	0
T6	164434	2887	0	0
T18	3875	0	0	0
T19	95307	26	0	0
T20	5595	62	0	0
T21	14757	137	0	0
T22	0	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3191903	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3191903	0	0
T1	38863	474	0	0
T2	5377	99	0	0
T3	574	6	0	0
T4	16960	90	0	0
T5	23611	154	0	0
T6	164434	1621	0	0
T18	3875	0	0	0
T19	95307	2166	0	0
T20	5595	81	0	0
T21	14757	117	0	0
T22	0	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1446453	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1446453	0	0
T1	38863	456	0	0
T2	5377	100	0	0
T3	574	3	0	0
T4	16960	248	0	0
T5	23611	344	0	0
T6	164434	1122	0	0
T18	3875	531	0	0
T19	95307	6	0	0
T20	5595	72	0	0
T21	14757	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3337068	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3337068	0	0
T1	38863	456	0	0
T2	5377	100	0	0
T3	574	3	0	0
T4	16960	136	0	0
T5	23611	158	0	0
T6	164434	1426	0	0
T18	3875	531	0	0
T19	95307	407	0	0
T20	5595	93	0	0
T21	14757	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1417728	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1417728	0	0
T1	38863	454	0	0
T2	5377	99	0	0
T3	574	2	0	0
T4	16960	229	0	0
T5	23611	275	0	0
T6	164434	1106	0	0
T18	3875	0	0	0
T19	95307	9	0	0
T20	5595	8	0	0
T21	14757	124	0	0
T22	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3667324	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3667324	0	0
T1	38863	454	0	0
T2	5377	99	0	0
T3	574	2	0	0
T4	16960	108	0	0
T5	23611	136	0	0
T6	164434	2612	0	0
T18	3875	0	0	0
T19	95307	1547	0	0
T20	5595	9	0	0
T21	14757	108	0	0
T22	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1426906	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1426906	0	0
T1	38863	1160	0	0
T2	5377	104	0	0
T3	574	9	0	0
T4	16960	127	0	0
T5	23611	252	0	0
T6	164434	519	0	0
T18	3875	0	0	0
T19	95307	29	0	0
T20	5595	75	0	0
T21	14757	141	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3627687	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3627687	0	0
T1	38863	1159	0	0
T2	5377	104	0	0
T3	574	9	0	0
T4	16960	45	0	0
T5	23611	115	0	0
T6	164434	127	0	0
T18	3875	0	0	0
T19	95307	769	0	0
T20	5595	107	0	0
T21	14757	126	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1439280	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1439280	0	0
T1	38863	409	0	0
T2	5377	90	0	0
T3	574	5	0	0
T4	16960	167	0	0
T5	23611	261	0	0
T6	164434	2189	0	0
T18	3875	0	0	0
T19	95307	28	0	0
T20	5595	71	0	0
T21	14757	148	0	0
T22	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3283713	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3283713	0	0
T1	38863	409	0	0
T2	5377	90	0	0
T3	574	5	0	0
T4	16960	90	0	0
T5	23611	135	0	0
T6	164434	1438	0	0
T18	3875	0	0	0
T19	95307	2158	0	0
T20	5595	78	0	0
T21	14757	129	0	0
T22	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1376658	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1376658	0	0
T1	38863	664	0	0
T2	5377	109	0	0
T3	574	5	0	0
T4	16960	98	0	0
T5	23611	389	0	0
T6	164434	1944	0	0
T18	3875	0	0	0
T19	95307	15	0	0
T20	5595	31	0	0
T21	14757	148	0	0
T22	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3034515	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3034515	0	0
T1	38863	664	0	0
T2	5377	109	0	0
T3	574	5	0	0
T4	16960	66	0	0
T5	23611	132	0	0
T6	164434	1994	0	0
T18	3875	0	0	0
T19	95307	1159	0	0
T20	5595	43	0	0
T21	14757	172	0	0
T22	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1399447	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1399447	0	0
T1	38863	951	0	0
T2	5377	84	0	0
T3	574	9	0	0
T4	16960	176	0	0
T5	23611	304	0	0
T6	164434	1968	0	0
T18	3875	0	0	0
T19	95307	1	0	0
T20	5595	47	0	0
T21	14757	173	0	0
T22	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	4063448	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	4063448	0	0
T1	38863	951	0	0
T2	5377	84	0	0
T3	574	9	0	0
T4	16960	87	0	0
T5	23611	127	0	0
T6	164434	2392	0	0
T18	3875	0	0	0
T19	95307	482	0	0
T20	5595	80	0	0
T21	14757	289	0	0
T22	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1394371	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1394371	0	0
T1	38863	637	0	0
T2	5377	83	0	0
T3	574	4	0	0
T4	16960	310	0	0
T5	23611	283	0	0
T6	164434	1959	0	0
T18	3875	0	0	0
T19	95307	4	0	0
T20	5595	68	0	0
T21	14757	107	0	0
T22	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3315241	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3315241	0	0
T1	38863	637	0	0
T2	5377	83	0	0
T3	574	4	0	0
T4	16960	124	0	0
T5	23611	159	0	0
T6	164434	2412	0	0
T18	3875	0	0	0
T19	95307	796	0	0
T20	5595	66	0	0
T21	14757	229	0	0
T22	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1407329	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1407329	0	0
T1	38863	786	0	0
T2	5377	106	0	0
T3	574	6	0	0
T4	16960	259	0	0
T5	23611	192	0	0
T6	164434	1172	0	0
T18	3875	0	0	0
T19	95307	9	0	0
T20	5595	60	0	0
T21	14757	149	0	0
T22	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3058431	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3058431	0	0
T1	38863	785	0	0
T2	5377	106	0	0
T3	574	6	0	0
T4	16960	75	0	0
T5	23611	88	0	0
T6	164434	2332	0	0
T18	3875	0	0	0
T19	95307	1009	0	0
T20	5595	69	0	0
T21	14757	134	0	0
T22	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1423743	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1423743	0	0
T1	38863	431	0	0
T2	5377	86	0	0
T3	574	5	0	0
T4	16960	121	0	0
T5	23611	302	0	0
T6	164434	392	0	0
T18	3875	283	0	0
T19	95307	21	0	0
T20	5595	46	0	0
T21	14757	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2966451	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2966451	0	0
T1	38863	431	0	0
T2	5377	86	0	0
T3	574	5	0	0
T4	16960	45	0	0
T5	23611	182	0	0
T6	164434	908	0	0
T18	3875	283	0	0
T19	95307	1688	0	0
T20	5595	28	0	0
T21	14757	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1389927	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1389927	0	0
T1	38863	952	0	0
T2	5377	95	0	0
T3	574	5	0	0
T4	16960	326	0	0
T5	23611	464	0	0
T6	164434	539	0	0
T18	3875	0	0	0
T19	95307	15	0	0
T20	5595	72	0	0
T21	14757	103	0	0
T22	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3966931	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3966931	0	0
T1	38863	952	0	0
T2	5377	95	0	0
T3	574	5	0	0
T4	16960	167	0	0
T5	23611	198	0	0
T6	164434	1270	0	0
T18	3875	0	0	0
T19	95307	1505	0	0
T20	5595	73	0	0
T21	14757	110	0	0
T22	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1422752	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1422752	0	0
T1	38863	473	0	0
T2	5377	99	0	0
T3	574	5	0	0
T4	16960	157	0	0
T5	23611	330	0	0
T6	164434	2668	0	0
T18	3875	0	0	0
T19	95307	6	0	0
T20	5595	40	0	0
T21	14757	120	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2611602	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2611602	0	0
T1	38863	473	0	0
T2	5377	99	0	0
T3	574	5	0	0
T4	16960	112	0	0
T5	23611	138	0	0
T6	164434	1293	0	0
T18	3875	0	0	0
T19	95307	236	0	0
T20	5595	88	0	0
T21	14757	171	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1425953	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1425953	0	0
T1	38863	927	0	0
T2	5377	103	0	0
T3	574	3	0	0
T4	16960	87	0	0
T5	23611	321	0	0
T6	164434	1408	0	0
T18	3875	0	0	0
T19	95307	9	0	0
T20	5595	31	0	0
T21	14757	168	0	0
T22	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2753865	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2753865	0	0
T1	38863	927	0	0
T2	5377	103	0	0
T3	574	3	0	0
T4	16960	36	0	0
T5	23611	140	0	0
T6	164434	811	0	0
T18	3875	0	0	0
T19	95307	592	0	0
T20	5595	34	0	0
T21	14757	114	0	0
T22	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1401406	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1401406	0	0
T1	38863	481	0	0
T2	5377	95	0	0
T3	574	2	0	0
T4	16960	191	0	0
T5	23611	352	0	0
T6	164434	517	0	0
T18	3875	782	0	0
T19	95307	52	0	0
T20	5595	17	0	0
T21	14757	151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3380361	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3380361	0	0
T1	38863	481	0	0
T2	5377	95	0	0
T3	574	2	0	0
T4	16960	68	0	0
T5	23611	131	0	0
T6	164434	815	0	0
T18	3875	782	0	0
T19	95307	3341	0	0
T20	5595	1	0	0
T21	14757	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1395430	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1395430	0	0
T1	38863	1132	0	0
T2	5377	88	0	0
T3	574	7	0	0
T4	16960	276	0	0
T5	23611	270	0	0
T6	164434	1580	0	0
T18	3875	228	0	0
T19	95307	21	0	0
T20	5595	44	0	0
T21	14757	153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3276231	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3276231	0	0
T1	38863	1132	0	0
T2	5377	88	0	0
T3	574	7	0	0
T4	16960	142	0	0
T5	23611	169	0	0
T6	164434	1176	0	0
T18	3875	228	0	0
T19	95307	2239	0	0
T20	5595	25	0	0
T21	14757	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1420364	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1420364	0	0
T1	38863	509	0	0
T2	5377	88	0	0
T3	574	7	0	0
T4	16960	246	0	0
T5	23611	273	0	0
T6	164434	3559	0	0
T18	3875	0	0	0
T19	95307	15	0	0
T20	5595	56	0	0
T21	14757	142	0	0
T22	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3065580	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3065580	0	0
T1	38863	509	0	0
T2	5377	88	0	0
T3	574	7	0	0
T4	16960	127	0	0
T5	23611	173	0	0
T6	164434	3326	0	0
T18	3875	0	0	0
T19	95307	1389	0	0
T20	5595	20	0	0
T21	14757	121	0	0
T22	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1449221	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1449221	0	0
T1	38863	501	0	0
T2	5377	92	0	0
T3	574	2	0	0
T4	16960	98	0	0
T5	23611	175	0	0
T6	164434	1721	0	0
T18	3875	0	0	0
T19	95307	0	0	0
T20	5595	53	0	0
T21	14757	231	0	0
T22	0	110	0	0
T23	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3741978	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3741978	0	0
T1	38863	501	0	0
T2	5377	92	0	0
T3	574	2	0	0
T4	16960	37	0	0
T5	23611	125	0	0
T6	164434	1492	0	0
T18	3875	0	0	0
T19	95307	0	0	0
T20	5595	43	0	0
T21	14757	177	0	0
T22	0	110	0	0
T23	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1393225	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1393225	0	0
T1	38863	712	0	0
T2	5377	112	0	0
T3	574	6	0	0
T4	16960	263	0	0
T5	23611	269	0	0
T6	164434	2940	0	0
T18	3875	486	0	0
T19	95307	21	0	0
T20	5595	37	0	0
T21	14757	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2590809	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2590809	0	0
T1	38863	712	0	0
T2	5377	112	0	0
T3	574	6	0	0
T4	16960	99	0	0
T5	23611	140	0	0
T6	164434	4152	0	0
T18	3875	486	0	0
T19	95307	2031	0	0
T20	5595	56	0	0
T21	14757	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1398731	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1398731	0	0
T1	38863	475	0	0
T2	5377	98	0	0
T3	574	4	0	0
T4	16960	178	0	0
T5	23611	260	0	0
T6	164434	1673	0	0
T18	3875	0	0	0
T19	95307	43	0	0
T20	5595	50	0	0
T21	14757	104	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3027162	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3027162	0	0
T1	38863	475	0	0
T2	5377	98	0	0
T3	574	4	0	0
T4	16960	79	0	0
T5	23611	116	0	0
T6	164434	2464	0	0
T18	3875	0	0	0
T19	95307	3862	0	0
T20	5595	72	0	0
T21	14757	102	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1388665	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1388665	0	0
T1	38863	458	0	0
T2	5377	86	0	0
T3	574	4	0	0
T4	16960	221	0	0
T5	23611	292	0	0
T6	164434	1251	0	0
T18	3875	208	0	0
T19	95307	18	0	0
T20	5595	90	0	0
T21	14757	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3008021	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3008021	0	0
T1	38863	458	0	0
T2	5377	86	0	0
T3	574	4	0	0
T4	16960	72	0	0
T5	23611	119	0	0
T6	164434	1042	0	0
T18	3875	208	0	0
T19	95307	2330	0	0
T20	5595	67	0	0
T21	14757	153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1386602	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1386602	0	0
T1	38863	437	0	0
T2	5377	112	0	0
T3	574	7	0	0
T4	16960	184	0	0
T5	23611	247	0	0
T6	164434	1936	0	0
T18	3875	0	0	0
T19	95307	19	0	0
T20	5595	25	0	0
T21	14757	100	0	0
T22	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3220046	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3220046	0	0
T1	38863	437	0	0
T2	5377	112	0	0
T3	574	7	0	0
T4	16960	87	0	0
T5	23611	96	0	0
T6	164434	3851	0	0
T18	3875	0	0	0
T19	95307	1326	0	0
T20	5595	48	0	0
T21	14757	91	0	0
T22	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1436375	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1436375	0	0
T1	38863	460	0	0
T2	5377	99	0	0
T3	574	5	0	0
T4	16960	183	0	0
T5	23611	279	0	0
T6	164434	754	0	0
T18	3875	421	0	0
T19	95307	28	0	0
T20	5595	12	0	0
T21	14757	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3389520	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3389520	0	0
T1	38863	460	0	0
T2	5377	99	0	0
T3	574	5	0	0
T4	16960	63	0	0
T5	23611	135	0	0
T6	164434	783	0	0
T18	3875	421	0	0
T19	95307	2686	0	0
T20	5595	60	0	0
T21	14757	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1419963	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1419963	0	0
T1	38863	704	0	0
T2	5377	96	0	0
T3	574	6	0	0
T4	16960	185	0	0
T5	23611	348	0	0
T6	164434	950	0	0
T18	3875	0	0	0
T19	95307	6	0	0
T20	5595	85	0	0
T21	14757	147	0	0
T22	0	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3449203	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3449203	0	0
T1	38863	704	0	0
T2	5377	96	0	0
T3	574	6	0	0
T4	16960	92	0	0
T5	23611	165	0	0
T6	164434	1672	0	0
T18	3875	0	0	0
T19	95307	546	0	0
T20	5595	64	0	0
T21	14757	212	0	0
T22	0	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1364165	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1364165	0	0
T1	38863	702	0	0
T2	5377	92	0	0
T3	574	4	0	0
T4	16960	226	0	0
T5	23611	333	0	0
T6	164434	1606	0	0
T18	3875	237	0	0
T19	95307	46	0	0
T20	5595	88	0	0
T21	14757	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3305951	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3305951	0	0
T1	38863	702	0	0
T2	5377	92	0	0
T3	574	4	0	0
T4	16960	111	0	0
T5	23611	121	0	0
T6	164434	2323	0	0
T18	3875	237	0	0
T19	95307	2808	0	0
T20	5595	79	0	0
T21	14757	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1391335	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1391335	0	0
T1	38863	434	0	0
T2	5377	118	0	0
T3	574	7	0	0
T4	16960	201	0	0
T5	23611	339	0	0
T6	164434	2038	0	0
T18	3875	241	0	0
T19	95307	12	0	0
T20	5595	55	0	0
T21	14757	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	3622039	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	3622039	0	0
T1	38863	434	0	0
T2	5377	118	0	0
T3	574	7	0	0
T4	16960	92	0	0
T5	23611	101	0	0
T6	164434	2084	0	0
T18	3875	241	0	0
T19	95307	1363	0	0
T20	5595	61	0	0
T21	14757	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1392022	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1392022	0	0
T1	38863	473	0	0
T2	5377	110	0	0
T3	574	8	0	0
T4	16960	200	0	0
T5	23611	250	0	0
T6	164434	1872	0	0
T18	3875	0	0	0
T19	95307	16	0	0
T20	5595	57	0	0
T21	14757	103	0	0
T22	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2663861	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2663861	0	0
T1	38863	473	0	0
T2	5377	110	0	0
T3	574	8	0	0
T4	16960	93	0	0
T5	23611	151	0	0
T6	164434	1771	0	0
T18	3875	0	0	0
T19	95307	1344	0	0
T20	5595	54	0	0
T21	14757	147	0	0
T22	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	1405764	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	1405764	0	0
T1	38863	441	0	0
T2	5377	80	0	0
T3	574	11	0	0
T4	16960	211	0	0
T5	23611	285	0	0
T6	164434	1984	0	0
T18	3875	0	0	0
T19	95307	15	0	0
T20	5595	17	0	0
T21	14757	162	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299740693	2458451	0	0
DepthKnown_A	299740693	299603787	0	0
RvalidKnown_A	299740693	299603787	0	0
WreadyKnown_A	299740693	299603787	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	2458451	0	0
T1	38863	441	0	0
T2	5377	80	0	0
T3	574	11	0	0
T4	16960	66	0	0
T5	23611	136	0	0
T6	164434	1018	0	0
T18	3875	0	0	0
T19	95307	1497	0	0
T20	5595	40	0	0
T21	14757	184	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299740693	299603787	0	0
T1	38863	37508	0	0
T2	5377	5322	0	0
T3	574	531	0	0
T4	16960	16934	0	0
T5	23611	23570	0	0
T6	164434	164410	0	0
T18	3875	3819	0	0
T19	95307	95246	0	0
T20	5595	5581	0	0
T21	14757	14713	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0