Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1709152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269306

1

T1

213

T2

15

T3

179

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	668070	1			T1	523		T2	49		T3	378
values[0x0]	641501	1			T1	504		T2	14		T3	376
values[0x1]	668887	1			T1	544		T2	66		T3	402

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1324316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

654142

1

T1

532

T2

55

T3

403

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7491	1			T1	4		T2	2		T4	13
valid_sources[0x01]	7761	1			T1	5		T3	5		T4	14
valid_sources[0x02]	6956	1			T1	12		T2	1		T3	10
valid_sources[0x03]	6856	1			T3	9		T4	16		T16	6
valid_sources[0x04]	8158	1			T1	9		T2	1		T4	11
valid_sources[0x05]	7678	1			T1	3		T4	14		T16	11
valid_sources[0x06]	8989	1			T1	12		T3	10		T4	4
valid_sources[0x07]	9166	1			T1	4		T4	8		T17	10
valid_sources[0x08]	8193	1			T1	10		T4	5		T16	12
valid_sources[0x09]	6929	1			T1	4		T2	2		T3	5
valid_sources[0x0a]	7239	1			T1	2		T3	7		T4	12
valid_sources[0x0b]	7431	1			T1	2		T4	11		T16	7
valid_sources[0x0c]	7742	1			T1	10		T2	1		T3	15
valid_sources[0x0d]	8150	1			T2	1		T4	10		T16	16
valid_sources[0x0e]	7386	1			T3	16		T4	7		T16	4
valid_sources[0x0f]	8178	1			T1	6		T4	15		T16	11
valid_sources[0x10]	7877	1			T1	4		T4	7		T16	6
valid_sources[0x11]	9406	1			T1	1		T4	11		T16	29
valid_sources[0x12]	8198	1			T1	8		T3	7		T4	7
valid_sources[0x13]	8450	1			T2	1		T3	19		T4	11
valid_sources[0x14]	7997	1			T4	10		T16	7		T17	7
valid_sources[0x15]	8236	1			T1	8		T2	2		T3	15
valid_sources[0x16]	7628	1			T1	10		T4	12		T16	2
valid_sources[0x17]	8060	1			T1	14		T4	3		T17	8
valid_sources[0x18]	7183	1			T4	8		T16	1		T17	6
valid_sources[0x19]	7442	1			T1	11		T2	1		T3	14
valid_sources[0x1a]	8237	1			T4	8		T17	6		T18	1
valid_sources[0x1b]	8536	1			T4	9		T17	5		T18	1
valid_sources[0x1c]	8216	1			T1	11		T3	13		T4	9
valid_sources[0x1d]	7668	1			T1	5		T4	14		T16	1
valid_sources[0x1e]	8689	1			T1	5		T4	9		T16	5
valid_sources[0x1f]	7408	1			T1	18		T3	12		T4	12
valid_sources[0x20]	7678	1			T3	11		T4	9		T16	14
valid_sources[0x21]	7408	1			T1	1		T3	14		T4	8
valid_sources[0x22]	7271	1			T1	5		T2	1		T4	11
valid_sources[0x23]	7905	1			T1	21		T4	13		T16	1
valid_sources[0x24]	7568	1			T1	5		T4	13		T16	56
valid_sources[0x25]	7539	1			T4	11		T16	4		T17	5
valid_sources[0x26]	7779	1			T4	8		T16	18		T17	14
valid_sources[0x27]	7142	1			T3	32		T4	10		T16	15
valid_sources[0x28]	7060	1			T3	37		T4	11		T16	14
valid_sources[0x29]	7324	1			T1	11		T2	1		T3	6
valid_sources[0x2a]	7772	1			T1	3		T2	2		T3	9
valid_sources[0x2b]	7065	1			T2	1		T4	12		T16	1
valid_sources[0x2c]	7207	1			T1	16		T4	12		T16	1
valid_sources[0x2d]	8143	1			T1	1		T4	9		T16	2
valid_sources[0x2e]	8066	1			T4	17		T16	1		T17	13
valid_sources[0x2f]	7755	1			T2	5		T3	8		T4	11
valid_sources[0x30]	6945	1			T2	2		T3	5		T4	8
valid_sources[0x31]	6821	1			T1	18		T4	9		T16	23
valid_sources[0x32]	7665	1			T1	8		T2	3		T4	8
valid_sources[0x33]	7260	1			T2	1		T4	9		T16	1
valid_sources[0x34]	7683	1			T1	2		T4	8		T16	11
valid_sources[0x35]	7924	1			T1	13		T4	10		T16	23
valid_sources[0x36]	7762	1			T4	13		T16	1		T17	7
valid_sources[0x37]	7735	1			T1	3		T2	2		T4	12
valid_sources[0x38]	7563	1			T2	2		T4	13		T16	7
valid_sources[0x39]	8535	1			T1	17		T2	2		T4	9
valid_sources[0x3a]	8906	1			T1	7		T4	7		T16	2
valid_sources[0x3b]	7128	1			T4	13		T16	19		T17	4
valid_sources[0x3c]	7285	1			T1	5		T4	9		T16	4
valid_sources[0x3d]	7440	1			T1	16		T3	15		T4	6
valid_sources[0x3e]	8281	1			T1	22		T4	11		T16	1
valid_sources[0x3f]	8753	1			T1	18		T4	12		T16	14
valid_sources[0x40]	7828	1			T3	18		T4	11		T16	14
valid_sources[0x41]	7889	1			T1	7		T4	11		T16	17
valid_sources[0x42]	7209	1			T3	14		T4	10		T16	4
valid_sources[0x43]	7651	1			T3	13		T4	12		T17	12
valid_sources[0x44]	7030	1			T1	6		T2	1		T4	10
valid_sources[0x45]	8236	1			T1	4		T2	1		T3	5
valid_sources[0x46]	7168	1			T1	15		T4	7		T16	11
valid_sources[0x47]	7467	1			T3	12		T4	16		T16	9
valid_sources[0x48]	7231	1			T1	5		T4	9		T16	1
valid_sources[0x49]	9005	1			T4	8		T16	2		T17	5
valid_sources[0x4a]	7008	1			T1	14		T4	17		T16	7
valid_sources[0x4b]	7628	1			T1	7		T3	20		T4	5
valid_sources[0x4c]	7583	1			T2	1		T3	13		T4	9
valid_sources[0x4d]	7851	1			T3	9		T4	15		T16	7
valid_sources[0x4e]	7750	1			T1	6		T2	1		T3	10
valid_sources[0x4f]	6844	1			T1	2		T4	8		T16	11
valid_sources[0x50]	7314	1			T1	16		T3	8		T4	17
valid_sources[0x51]	7932	1			T1	8		T4	12		T16	9
valid_sources[0x52]	6900	1			T1	8		T4	13		T16	6
valid_sources[0x53]	7528	1			T1	42		T4	4		T16	4
valid_sources[0x54]	8631	1			T1	8		T4	14		T16	15
valid_sources[0x55]	7500	1			T1	9		T4	11		T16	7
valid_sources[0x56]	8327	1			T1	14		T2	4		T4	11
valid_sources[0x57]	7878	1			T1	4		T4	7		T17	5
valid_sources[0x58]	7996	1			T3	12		T4	11		T16	22
valid_sources[0x59]	7918	1			T4	9		T16	2		T17	10
valid_sources[0x5a]	8988	1			T1	6		T2	1		T3	13
valid_sources[0x5b]	7577	1			T4	14		T16	9		T17	3
valid_sources[0x5c]	7806	1			T1	2		T4	7		T16	3
valid_sources[0x5d]	9845	1			T4	11		T16	6		T17	6
valid_sources[0x5e]	7086	1			T4	14		T16	9		T17	13
valid_sources[0x5f]	7810	1			T2	1		T3	5		T4	14
valid_sources[0x60]	8798	1			T1	1		T4	11		T16	19
valid_sources[0x61]	7308	1			T1	4		T4	6		T16	2
valid_sources[0x62]	7340	1			T1	7		T3	18		T4	11
valid_sources[0x63]	8284	1			T1	2		T2	3		T3	5
valid_sources[0x64]	7069	1			T1	8		T4	12		T16	9
valid_sources[0x65]	7650	1			T1	16		T2	1		T4	9
valid_sources[0x66]	6971	1			T4	12		T16	27		T17	11
valid_sources[0x67]	8363	1			T4	11		T16	7		T17	12
valid_sources[0x68]	7017	1			T4	13		T16	11		T17	7
valid_sources[0x69]	8176	1			T1	13		T2	3		T4	13
valid_sources[0x6a]	8373	1			T1	15		T3	18		T4	7
valid_sources[0x6b]	7529	1			T1	7		T4	10		T16	33
valid_sources[0x6c]	7796	1			T1	3		T3	11		T4	7
valid_sources[0x6d]	7928	1			T1	11		T3	11		T4	8
valid_sources[0x6e]	7964	1			T1	38		T3	21		T4	12
valid_sources[0x6f]	7915	1			T1	2		T3	9		T4	10
valid_sources[0x70]	7935	1			T1	1		T2	4		T3	20
valid_sources[0x71]	7054	1			T3	19		T4	11		T16	34
valid_sources[0x72]	8532	1			T2	4		T4	15		T16	7
valid_sources[0x73]	7070	1			T4	4		T16	4		T17	10
valid_sources[0x74]	7539	1			T1	5		T4	14		T16	27
valid_sources[0x75]	7693	1			T3	14		T4	5		T16	4
valid_sources[0x76]	7308	1			T4	21		T16	26		T17	6
valid_sources[0x77]	8129	1			T1	7		T2	1		T4	11
valid_sources[0x78]	7501	1			T4	11		T16	8		T17	7
valid_sources[0x79]	7081	1			T1	13		T4	12		T16	9
valid_sources[0x7a]	7165	1			T1	14		T4	11		T16	4
valid_sources[0x7b]	8348	1			T1	8		T3	20		T4	15
valid_sources[0x7c]	8531	1			T1	18		T4	15		T16	3
valid_sources[0x7d]	7377	1			T1	6		T4	17		T16	10
valid_sources[0x7e]	7048	1			T4	12		T16	6		T17	7
valid_sources[0x7f]	7564	1			T1	8		T2	1		T3	15
valid_sources[0x80]	7879	1			T1	5		T2	2		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28135

1

T1

25

T2

6

T3

24

values[0x0]

all_enables

biggest_size

212972

1

T1

171

T2

5

T3

131

values[0x1]

all_enables

biggest_size

28199

1

T1

17

T2

4

T3

24