Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	334966099	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334966099	0	0
T1	181888	7714	0	0
T2	4666480	117025	0	0
T3	2549176	36644	0	0
T4	13444424	2154957	0	0
T14	3130008	63028	0	0
T15	808472	19329	0	0
T16	2547608	54024	0	0
T17	2396800	72090	0	0
T18	46256	804	0	0
T19	19880	517	0	0
T20	0	36796	0	0
T21	0	18419	0	0
T22	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	181888	179928	0	0
T2	4666480	4663680	0	0
T3	2549176	2546152	0	0
T4	13444424	13444200	0	0
T14	3130008	3125976	0	0
T15	808472	774368	0	0
T16	2547608	2545984	0	0
T17	2396800	2394728	0	0
T18	46256	43288	0	0
T19	19880	18480	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	181888	179928	0	0
T2	4666480	4663680	0	0
T3	2549176	2546152	0	0
T4	13444424	13444200	0	0
T14	3130008	3125976	0	0
T15	808472	774368	0	0
T16	2547608	2545984	0	0
T17	2396800	2394728	0	0
T18	46256	43288	0	0
T19	19880	18480	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	181888	179928	0	0
T2	4666480	4663680	0	0
T3	2549176	2546152	0	0
T4	13444424	13444200	0	0
T14	3130008	3125976	0	0
T15	808472	774368	0	0
T16	2547608	2545984	0	0
T17	2396800	2394728	0	0
T18	46256	43288	0	0
T19	19880	18480	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	121950110	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	121950110	0	0
T1	3248	3001	0	0
T2	83330	51593	0	0
T3	45521	9359	0	0
T4	240079	237129	0	0
T14	55893	25682	0	0
T15	14437	8357	0	0
T16	45493	16864	0	0
T17	42800	17651	0	0
T18	826	312	0	0
T19	355	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	88941730	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	88941730	0	0
T1	3248	1571	0	0
T2	83330	21129	0	0
T3	45521	8967	0	0
T4	240079	953809	0	0
T14	55893	17338	0	0
T15	14437	3640	0	0
T16	45493	10148	0	0
T17	42800	18410	0	0
T18	826	164	0	0
T19	355	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1302127	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1302127	0	0
T1	3248	58	0	0
T2	83330	828	0	0
T3	45521	276	0	0
T4	240079	516	0	0
T14	55893	371	0	0
T15	14437	198	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	5	0	0
T20	0	25	0	0
T21	0	426	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3376264	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3376264	0	0
T1	3248	58	0	0
T2	83330	817	0	0
T3	45521	264	0	0
T4	240079	41964	0	0
T14	55893	333	0	0
T15	14437	175	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	5	0	0
T20	0	2335	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1326494	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1326494	0	0
T1	3248	52	0	0
T2	83330	872	0	0
T3	45521	439	0	0
T4	240079	365	0	0
T14	55893	379	0	0
T15	14437	152	0	0
T16	45493	0	0	0
T17	42800	2335	0	0
T18	826	5	0	0
T19	355	7	0	0
T20	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3179943	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3179943	0	0
T1	3248	52	0	0
T2	83330	840	0	0
T3	45521	329	0	0
T4	240079	33445	0	0
T14	55893	333	0	0
T15	14437	110	0	0
T16	45493	0	0	0
T17	42800	2361	0	0
T18	826	5	0	0
T19	355	7	0	0
T20	0	1097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1363989	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1363989	0	0
T1	3248	63	0	0
T2	83330	863	0	0
T3	45521	417	0	0
T4	240079	356	0	0
T14	55893	399	0	0
T15	14437	40	0	0
T16	45493	1424	0	0
T17	42800	1293	0	0
T18	826	4	0	0
T19	355	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3571226	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3571226	0	0
T1	3248	63	0	0
T2	83330	796	0	0
T3	45521	336	0	0
T4	240079	31331	0	0
T14	55893	414	0	0
T15	14437	41	0	0
T16	45493	1045	0	0
T17	42800	1717	0	0
T18	826	4	0	0
T19	355	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1350078	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1350078	0	0
T1	3248	60	0	0
T2	83330	831	0	0
T3	45521	272	0	0
T4	240079	319	0	0
T14	55893	446	0	0
T15	14437	120	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	5	0	0
T19	355	4	0	0
T20	0	11	0	0
T21	0	1016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3918278	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3918278	0	0
T1	3248	60	0	0
T2	83330	666	0	0
T3	45521	287	0	0
T4	240079	34257	0	0
T14	55893	444	0	0
T15	14437	94	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	5	0	0
T19	355	4	0	0
T20	0	1120	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1313057	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1313057	0	0
T1	3248	50	0	0
T2	83330	655	0	0
T3	45521	347	0	0
T4	240079	365	0	0
T14	55893	419	0	0
T15	14437	371	0	0
T16	45493	0	0	0
T17	42800	3463	0	0
T18	826	8	0	0
T19	355	1	0	0
T20	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3374827	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3374827	0	0
T1	3248	50	0	0
T2	83330	649	0	0
T3	45521	374	0	0
T4	240079	26767	0	0
T14	55893	309	0	0
T15	14437	279	0	0
T16	45493	0	0	0
T17	42800	3406	0	0
T18	826	8	0	0
T19	355	1	0	0
T20	0	1025	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1285570	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1285570	0	0
T1	3248	64	0	0
T2	83330	1007	0	0
T3	45521	323	0	0
T4	240079	379	0	0
T14	55893	300	0	0
T15	14437	128	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	5	0	0
T19	355	4	0	0
T20	0	16	0	0
T21	0	1076	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3005372	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3005372	0	0
T1	3248	64	0	0
T2	83330	875	0	0
T3	45521	281	0	0
T4	240079	32118	0	0
T14	55893	376	0	0
T15	14437	113	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	5	0	0
T19	355	4	0	0
T20	0	1102	0	0
T21	0	155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1339035	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1339035	0	0
T1	3248	60	0	0
T2	83330	775	0	0
T3	45521	309	0	0
T4	240079	519	0	0
T14	55893	325	0	0
T15	14437	238	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	9	0	0
T19	355	3	0	0
T20	0	27	0	0
T21	0	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3484926	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3484926	0	0
T1	3248	60	0	0
T2	83330	855	0	0
T3	45521	355	0	0
T4	240079	41565	0	0
T14	55893	256	0	0
T15	14437	238	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	9	0	0
T19	355	3	0	0
T20	0	2122	0	0
T21	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1300246	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1300246	0	0
T1	3248	81	0	0
T2	83330	940	0	0
T3	45521	339	0	0
T4	240079	444	0	0
T14	55893	543	0	0
T15	14437	188	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	5	0	0
T20	0	41	0	0
T21	0	2065	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3511585	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3511585	0	0
T1	3248	81	0	0
T2	83330	843	0	0
T3	45521	329	0	0
T4	240079	38395	0	0
T14	55893	505	0	0
T15	14437	153	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	5	0	0
T20	0	1983	0	0
T21	0	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1319791	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1319791	0	0
T1	3248	65	0	0
T2	83330	762	0	0
T3	45521	268	0	0
T4	240079	439	0	0
T14	55893	471	0	0
T15	14437	98	0	0
T16	45493	1776	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	5	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3351997	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3351997	0	0
T1	3248	65	0	0
T2	83330	821	0	0
T3	45521	290	0	0
T4	240079	33722	0	0
T14	55893	478	0	0
T15	14437	84	0	0
T16	45493	847	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	5	0	0
T20	0	1837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1363985	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1363985	0	0
T1	3248	52	0	0
T2	83330	777	0	0
T3	45521	431	0	0
T4	240079	457	0	0
T14	55893	415	0	0
T15	14437	142	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	4	0	0
T20	0	23	0	0
T21	0	880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3183226	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3183226	0	0
T1	3248	52	0	0
T2	83330	670	0	0
T3	45521	338	0	0
T4	240079	37444	0	0
T14	55893	316	0	0
T15	14437	151	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	4	0	0
T20	0	828	0	0
T21	0	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1381735	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1381735	0	0
T1	3248	56	0	0
T2	83330	918	0	0
T3	45521	274	0	0
T4	240079	396	0	0
T14	55893	406	0	0
T15	14437	59	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	3	0	0
T20	0	3	0	0
T21	0	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3650416	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3650416	0	0
T1	3248	56	0	0
T2	83330	955	0	0
T3	45521	238	0	0
T4	240079	32997	0	0
T14	55893	398	0	0
T15	14437	59	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	3	0	0
T20	0	549	0	0
T21	0	1223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1390016	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1390016	0	0
T1	3248	55	0	0
T2	83330	1045	0	0
T3	45521	368	0	0
T4	240079	416	0	0
T14	55893	382	0	0
T15	14437	76	0	0
T16	45493	4022	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	9	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3128559	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3128559	0	0
T1	3248	55	0	0
T2	83330	877	0	0
T3	45521	248	0	0
T4	240079	31924	0	0
T14	55893	308	0	0
T15	14437	95	0	0
T16	45493	1906	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	9	0	0
T20	0	1500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1322015	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1322015	0	0
T1	3248	57	0	0
T2	83330	768	0	0
T3	45521	287	0	0
T4	240079	349	0	0
T14	55893	324	0	0
T15	14437	104	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	9	0	0
T19	355	2	0	0
T20	0	18	0	0
T21	0	639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3111331	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3111331	0	0
T1	3248	57	0	0
T2	83330	576	0	0
T3	45521	316	0	0
T4	240079	33606	0	0
T14	55893	349	0	0
T15	14437	143	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	9	0	0
T19	355	2	0	0
T20	0	2441	0	0
T21	0	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1287707	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1287707	0	0
T1	3248	65	0	0
T2	83330	1157	0	0
T3	45521	371	0	0
T4	240079	463	0	0
T14	55893	485	0	0
T15	14437	52	0	0
T16	45493	0	0	0
T17	42800	1780	0	0
T18	826	14	0	0
T19	355	5	0	0
T20	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2550435	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2550435	0	0
T1	3248	65	0	0
T2	83330	1052	0	0
T3	45521	416	0	0
T4	240079	40819	0	0
T14	55893	428	0	0
T15	14437	61	0	0
T16	45493	0	0	0
T17	42800	2121	0	0
T18	826	14	0	0
T19	355	5	0	0
T20	0	1294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1337318	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1337318	0	0
T1	3248	72	0	0
T2	83330	928	0	0
T3	45521	461	0	0
T4	240079	403	0	0
T14	55893	395	0	0
T15	14437	124	0	0
T16	45493	1180	0	0
T17	42800	2194	0	0
T18	826	5	0	0
T19	355	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3449096	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3449096	0	0
T1	3248	72	0	0
T2	83330	764	0	0
T3	45521	505	0	0
T4	240079	37380	0	0
T14	55893	431	0	0
T15	14437	83	0	0
T16	45493	1150	0	0
T17	42800	2181	0	0
T18	826	5	0	0
T19	355	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1299614	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1299614	0	0
T1	3248	41	0	0
T2	83330	790	0	0
T3	45521	357	0	0
T4	240079	365	0	0
T14	55893	339	0	0
T15	14437	92	0	0
T16	45493	0	0	0
T17	42800	2369	0	0
T18	826	6	0	0
T19	355	7	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2735207	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2735207	0	0
T1	3248	41	0	0
T2	83330	782	0	0
T3	45521	417	0	0
T4	240079	33386	0	0
T14	55893	325	0	0
T15	14437	148	0	0
T16	45493	0	0	0
T17	42800	2361	0	0
T18	826	6	0	0
T19	355	7	0	0
T20	0	638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1325555	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1325555	0	0
T1	3248	64	0	0
T2	83330	935	0	0
T3	45521	372	0	0
T4	240079	375	0	0
T14	55893	316	0	0
T15	14437	71	0	0
T16	45493	2731	0	0
T17	42800	1779	0	0
T18	826	6	0	0
T19	355	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3556603	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3556603	0	0
T1	3248	64	0	0
T2	83330	748	0	0
T3	45521	355	0	0
T4	240079	32634	0	0
T14	55893	303	0	0
T15	14437	66	0	0
T16	45493	2069	0	0
T17	42800	1812	0	0
T18	826	6	0	0
T19	355	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1305927	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1305927	0	0
T1	3248	66	0	0
T2	83330	888	0	0
T3	45521	250	0	0
T4	240079	332	0	0
T14	55893	375	0	0
T15	14437	28	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	4	0	0
T20	0	26	0	0
T21	0	831	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2592936	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2592936	0	0
T1	3248	66	0	0
T2	83330	813	0	0
T3	45521	223	0	0
T4	240079	26586	0	0
T14	55893	328	0	0
T15	14437	29	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	4	0	0
T20	0	3570	0	0
T21	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1365877	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1365877	0	0
T1	3248	55	0	0
T2	83330	786	0	0
T3	45521	326	0	0
T4	240079	377	0	0
T14	55893	271	0	0
T15	14437	155	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	6	0	0
T19	355	3	0	0
T20	0	3	0	0
T21	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3980231	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3980231	0	0
T1	3248	55	0	0
T2	83330	710	0	0
T3	45521	351	0	0
T4	240079	34165	0	0
T14	55893	272	0	0
T15	14437	83	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	6	0	0
T19	355	3	0	0
T20	0	1239	0	0
T21	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1359632	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1359632	0	0
T1	3248	58	0	0
T2	83330	923	0	0
T3	45521	376	0	0
T4	240079	317	0	0
T14	55893	314	0	0
T15	14437	289	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	0	0	0
T20	0	31	0	0
T21	0	934	0	0
T22	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3694864	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3694864	0	0
T1	3248	58	0	0
T2	83330	721	0	0
T3	45521	345	0	0
T4	240079	26638	0	0
T14	55893	265	0	0
T15	14437	321	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	3	0	0
T19	355	0	0	0
T20	0	2594	0	0
T21	0	705	0	0
T22	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1267507	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1267507	0	0
T1	3248	54	0	0
T2	83330	831	0	0
T3	45521	258	0	0
T4	240079	415	0	0
T14	55893	458	0	0
T15	14437	313	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	5	0	0
T20	0	33	0	0
T21	0	658	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2638697	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2638697	0	0
T1	3248	54	0	0
T2	83330	738	0	0
T3	45521	254	0	0
T4	240079	40953	0	0
T14	55893	393	0	0
T15	14437	224	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	5	0	0
T20	0	1761	0	0
T21	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1339667	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1339667	0	0
T1	3248	58	0	0
T2	83330	709	0	0
T3	45521	427	0	0
T4	240079	482	0	0
T14	55893	257	0	0
T15	14437	93	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	3	0	0
T20	0	8	0	0
T21	0	1071	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3468194	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3468194	0	0
T1	3248	58	0	0
T2	83330	619	0	0
T3	45521	272	0	0
T4	240079	41632	0	0
T14	55893	295	0	0
T15	14437	109	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	8	0	0
T19	355	3	0	0
T20	0	95	0	0
T21	0	607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1353697	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1353697	0	0
T1	3248	56	0	0
T2	83330	788	0	0
T3	45521	403	0	0
T4	240079	426	0	0
T14	55893	339	0	0
T15	14437	139	0	0
T16	45493	1025	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	3	0	0
T20	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2803362	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2803362	0	0
T1	3248	56	0	0
T2	83330	762	0	0
T3	45521	316	0	0
T4	240079	37755	0	0
T14	55893	404	0	0
T15	14437	144	0	0
T16	45493	821	0	0
T17	42800	0	0	0
T18	826	7	0	0
T19	355	3	0	0
T20	0	1255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1347584	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1347584	0	0
T1	3248	57	0	0
T2	83330	851	0	0
T3	45521	481	0	0
T4	240079	466	0	0
T14	55893	388	0	0
T15	14437	181	0	0
T16	45493	2450	0	0
T17	42800	2432	0	0
T18	826	3	0	0
T19	355	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	2951561	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	2951561	0	0
T1	3248	57	0	0
T2	83330	758	0	0
T3	45521	469	0	0
T4	240079	34680	0	0
T14	55893	378	0	0
T15	14437	99	0	0
T16	45493	1245	0	0
T17	42800	2425	0	0
T18	826	3	0	0
T19	355	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1349899	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1349899	0	0
T1	3248	38	0	0
T2	83330	910	0	0
T3	45521	271	0	0
T4	240079	402	0	0
T14	55893	423	0	0
T15	14437	102	0	0
T16	45493	2256	0	0
T17	42800	0	0	0
T18	826	6	0	0
T19	355	4	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3178515	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3178515	0	0
T1	3248	38	0	0
T2	83330	846	0	0
T3	45521	264	0	0
T4	240079	34890	0	0
T14	55893	316	0	0
T15	14437	127	0	0
T16	45493	1065	0	0
T17	42800	0	0	0
T18	826	6	0	0
T19	355	4	0	0
T20	0	2302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1319347	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1319347	0	0
T1	3248	56	0	0
T2	83330	958	0	0
T3	45521	263	0	0
T4	240079	478	0	0
T14	55893	424	0	0
T15	14437	123	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	2	0	0
T20	0	9	0	0
T21	0	721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3145833	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3145833	0	0
T1	3248	56	0	0
T2	83330	889	0	0
T3	45521	424	0	0
T4	240079	38715	0	0
T14	55893	368	0	0
T15	14437	140	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	2	0	0
T20	0	1251	0	0
T21	0	861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	1376085	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	1376085	0	0
T1	3248	58	0	0
T2	83330	702	0	0
T3	45521	389	0	0
T4	240079	483	0	0
T14	55893	367	0	0
T15	14437	148	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	2	0	0
T20	0	36	0	0
T21	0	2123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303893808	3487221	0	0
DepthKnown_A	303893808	303772082	0	0
RvalidKnown_A	303893808	303772082	0	0
WreadyKnown_A	303893808	303772082	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	3487221	0	0
T1	3248	58	0	0
T2	83330	664	0	0
T3	45521	367	0	0
T4	240079	43147	0	0
T14	55893	352	0	0
T15	14437	139	0	0
T16	45493	0	0	0
T17	42800	0	0	0
T18	826	4	0	0
T19	355	2	0	0
T20	0	2418	0	0
T21	0	236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303893808	303772082	0	0
T1	3248	3213	0	0
T2	83330	83280	0	0
T3	45521	45467	0	0
T4	240079	240075	0	0
T14	55893	55821	0	0
T15	14437	13828	0	0
T16	45493	45464	0	0
T17	42800	42763	0	0
T18	826	773	0	0
T19	355	330	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0