Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1728185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

271566

1

T1

6

T2

1423

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	676794	1			T1	23		T2	3326		T3	45
values[0x0]	645461	1			T1	3		T2	3353		T3	57
values[0x1]	677496	1			T1	28		T2	3412		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1339706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

660045

1

T1

20

T2

3395

T3

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8065	1			T2	54		T14	7		T15	20
valid_sources[0x01]	7928	1			T2	73		T3	8		T4	3
valid_sources[0x02]	8429	1			T2	34		T14	6		T13	1
valid_sources[0x03]	7842	1			T2	42		T14	7		T15	33
valid_sources[0x04]	6971	1			T1	1		T2	36		T4	2
valid_sources[0x05]	7698	1			T2	35		T4	1		T14	7
valid_sources[0x06]	9364	1			T2	48		T4	1		T14	3
valid_sources[0x07]	7319	1			T2	37		T4	5		T14	4
valid_sources[0x08]	8527	1			T2	32		T4	8		T14	5
valid_sources[0x09]	8294	1			T2	46		T4	3		T14	4
valid_sources[0x0a]	8566	1			T2	32		T4	1		T14	6
valid_sources[0x0b]	7833	1			T1	1		T2	30		T4	4
valid_sources[0x0c]	7486	1			T2	32		T3	3		T14	3
valid_sources[0x0d]	7156	1			T2	31		T3	7		T4	1
valid_sources[0x0e]	8145	1			T1	2		T2	64		T4	11
valid_sources[0x0f]	7815	1			T2	35		T4	8		T14	8
valid_sources[0x10]	7998	1			T2	53		T4	8		T14	7
valid_sources[0x11]	7902	1			T2	68		T4	1		T14	6
valid_sources[0x12]	7409	1			T2	30		T4	5		T14	2
valid_sources[0x13]	7419	1			T2	32		T3	5		T4	2
valid_sources[0x14]	7899	1			T2	27		T4	5		T14	3
valid_sources[0x15]	8120	1			T2	32		T14	4		T15	26
valid_sources[0x16]	7355	1			T2	43		T4	1		T14	5
valid_sources[0x17]	8119	1			T2	31		T14	7		T16	16
valid_sources[0x18]	7754	1			T2	40		T4	1		T14	5
valid_sources[0x19]	8424	1			T2	22		T14	7		T15	16
valid_sources[0x1a]	7309	1			T2	45		T4	4		T14	6
valid_sources[0x1b]	7815	1			T2	63		T4	3		T14	5
valid_sources[0x1c]	7528	1			T2	63		T4	2		T14	4
valid_sources[0x1d]	7489	1			T2	26		T4	6		T14	6
valid_sources[0x1e]	7793	1			T2	45		T4	2		T14	3
valid_sources[0x1f]	8508	1			T2	27		T14	3		T15	3
valid_sources[0x20]	8213	1			T2	45		T4	1		T14	7
valid_sources[0x21]	7684	1			T1	1		T2	31		T14	5
valid_sources[0x22]	7930	1			T1	1		T2	26		T4	1
valid_sources[0x23]	7538	1			T2	57		T4	1		T14	6
valid_sources[0x24]	8442	1			T1	1		T2	72		T4	2
valid_sources[0x25]	7449	1			T2	53		T4	1		T14	9
valid_sources[0x26]	7607	1			T2	27		T4	1		T14	8
valid_sources[0x27]	7425	1			T2	62		T14	3		T13	1
valid_sources[0x28]	7955	1			T1	2		T2	40		T4	1
valid_sources[0x29]	8824	1			T2	37		T3	7		T4	3
valid_sources[0x2a]	7873	1			T2	33		T4	1		T14	4
valid_sources[0x2b]	7966	1			T1	1		T2	30		T4	4
valid_sources[0x2c]	8054	1			T1	1		T2	36		T3	8
valid_sources[0x2d]	7200	1			T2	28		T4	2		T14	12
valid_sources[0x2e]	7341	1			T1	1		T2	30		T4	2
valid_sources[0x2f]	8560	1			T2	31		T3	1		T14	5
valid_sources[0x30]	7945	1			T2	37		T4	1		T14	7
valid_sources[0x31]	8134	1			T2	40		T14	8		T13	2
valid_sources[0x32]	7471	1			T2	35		T4	5		T14	5
valid_sources[0x33]	7138	1			T2	37		T4	1		T14	2
valid_sources[0x34]	8103	1			T2	32		T4	1		T14	7
valid_sources[0x35]	7989	1			T2	51		T4	3		T14	8
valid_sources[0x36]	7743	1			T2	28		T4	5		T14	7
valid_sources[0x37]	7690	1			T2	27		T4	4		T14	6
valid_sources[0x38]	7812	1			T1	1		T2	32		T3	3
valid_sources[0x39]	7604	1			T2	24		T3	1		T4	2
valid_sources[0x3a]	7496	1			T2	39		T3	4		T4	1
valid_sources[0x3b]	7250	1			T2	38		T4	4		T14	5
valid_sources[0x3c]	7327	1			T2	21		T4	1		T14	7
valid_sources[0x3d]	8448	1			T1	1		T2	43		T14	6
valid_sources[0x3e]	7247	1			T1	1		T2	33		T4	1
valid_sources[0x3f]	6861	1			T2	42		T14	6		T15	26
valid_sources[0x40]	7499	1			T2	55		T4	1		T14	6
valid_sources[0x41]	7818	1			T2	29		T4	1		T14	7
valid_sources[0x42]	7684	1			T2	38		T4	4		T14	2
valid_sources[0x43]	7423	1			T2	38		T4	1		T14	3
valid_sources[0x44]	6831	1			T2	33		T14	7		T13	1
valid_sources[0x45]	7984	1			T2	42		T4	3		T14	9
valid_sources[0x46]	8204	1			T2	42		T14	5		T15	2
valid_sources[0x47]	7719	1			T2	31		T4	2		T14	2
valid_sources[0x48]	7151	1			T2	33		T4	1		T14	2
valid_sources[0x49]	7324	1			T1	2		T2	31		T3	2
valid_sources[0x4a]	7493	1			T2	33		T14	5		T13	1
valid_sources[0x4b]	7632	1			T2	39		T4	2		T14	12
valid_sources[0x4c]	8575	1			T2	19		T14	6		T15	15
valid_sources[0x4d]	7968	1			T2	45		T14	4		T15	7
valid_sources[0x4e]	7435	1			T2	48		T4	2		T14	4
valid_sources[0x4f]	9814	1			T2	59		T14	4		T15	20
valid_sources[0x50]	7623	1			T2	47		T4	1		T14	4
valid_sources[0x51]	8990	1			T1	1		T2	49		T4	1
valid_sources[0x52]	7946	1			T2	27		T4	1		T14	4
valid_sources[0x53]	9142	1			T2	52		T14	4		T15	6
valid_sources[0x54]	7466	1			T2	39		T4	1		T14	9
valid_sources[0x55]	7001	1			T2	73		T14	5		T15	9
valid_sources[0x56]	7399	1			T2	39		T4	1		T14	6
valid_sources[0x57]	7702	1			T2	38		T4	5		T14	4
valid_sources[0x58]	7033	1			T2	35		T4	3		T14	5
valid_sources[0x59]	7383	1			T1	1		T2	41		T4	1
valid_sources[0x5a]	7571	1			T2	50		T4	2		T14	4
valid_sources[0x5b]	8559	1			T2	38		T14	5		T13	1
valid_sources[0x5c]	7927	1			T2	31		T4	4		T14	3
valid_sources[0x5d]	7835	1			T2	24		T4	2		T14	4
valid_sources[0x5e]	8008	1			T2	36		T3	9		T4	4
valid_sources[0x5f]	7211	1			T2	23		T14	9		T15	6
valid_sources[0x60]	7392	1			T2	30		T4	1		T14	3
valid_sources[0x61]	7649	1			T2	60		T4	3		T14	4
valid_sources[0x62]	7867	1			T1	1		T2	28		T4	8
valid_sources[0x63]	7015	1			T2	31		T4	1		T14	10
valid_sources[0x64]	8346	1			T2	46		T4	6		T14	8
valid_sources[0x65]	9439	1			T2	41		T14	2		T15	13
valid_sources[0x66]	8540	1			T1	1		T2	43		T14	6
valid_sources[0x67]	7986	1			T2	25		T4	3		T14	3
valid_sources[0x68]	7485	1			T2	21		T14	5		T15	2
valid_sources[0x69]	7587	1			T2	27		T4	2		T14	6
valid_sources[0x6a]	8847	1			T2	79		T4	19		T14	3
valid_sources[0x6b]	6863	1			T2	31		T4	4		T14	5
valid_sources[0x6c]	9010	1			T2	51		T4	6		T14	6
valid_sources[0x6d]	7823	1			T2	47		T4	1		T14	6
valid_sources[0x6e]	8127	1			T2	50		T14	3		T15	5
valid_sources[0x6f]	8472	1			T1	1		T2	44		T4	1
valid_sources[0x70]	7290	1			T2	36		T4	1		T14	8
valid_sources[0x71]	8054	1			T1	1		T2	33		T4	2
valid_sources[0x72]	6876	1			T2	33		T4	1		T14	6
valid_sources[0x73]	8367	1			T2	54		T4	3		T14	8
valid_sources[0x74]	7828	1			T1	1		T2	54		T14	3
valid_sources[0x75]	7859	1			T2	32		T14	5		T15	6
valid_sources[0x76]	6926	1			T2	31		T4	4		T14	1
valid_sources[0x77]	8034	1			T2	39		T4	8		T14	4
valid_sources[0x78]	7447	1			T2	48		T14	3		T15	23
valid_sources[0x79]	7153	1			T2	33		T4	16		T14	3
valid_sources[0x7a]	7744	1			T2	33		T4	3		T14	3
valid_sources[0x7b]	7623	1			T1	2		T2	43		T4	8
valid_sources[0x7c]	7403	1			T2	29		T3	2		T4	2
valid_sources[0x7d]	8255	1			T2	24		T4	5		T14	5
valid_sources[0x7e]	7313	1			T2	37		T3	3		T4	4
valid_sources[0x7f]	7230	1			T2	41		T4	2		T14	5
valid_sources[0x80]	6812	1			T2	50		T4	2		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28737

1

T1

4

T2

126

T3

3

values[0x0]

all_enables

biggest_size

213760

1

T1

1

T2

1168

T3

22

values[0x1]

all_enables

biggest_size

29069

1

T1

1

T2

129

T3

2