Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335471003	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335471003	0	0
T1	1394400	31431	0	0
T2	13679064	340639	0	0
T3	11622632	215243	0	0
T4	1809864	77484	0	0
T13	3768968	81748	0	0
T14	39541768	707286	0	0
T15	2377424	66320	0	0
T16	26324480	1995680	0	0
T17	2659104	55698	0	0
T18	277872	11389	0	0
T19	0	13922	0	0
T20	0	1644	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1394400	1391992	0	0
T2	13679064	13675088	0	0
T3	11622632	11618152	0	0
T4	1809864	1800176	0	0
T13	3768968	3765384	0	0
T14	39541768	39540816	0	0
T15	2377424	2373336	0	0
T16	26324480	26324312	0	0
T17	2659104	2657312	0	0
T18	277872	274120	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1394400	1391992	0	0
T2	13679064	13675088	0	0
T3	11622632	11618152	0	0
T4	1809864	1800176	0	0
T13	3768968	3765384	0	0
T14	39541768	39540816	0	0
T15	2377424	2373336	0	0
T16	26324480	26324312	0	0
T17	2659104	2657312	0	0
T18	277872	274120	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1394400	1391992	0	0
T2	13679064	13675088	0	0
T3	11622632	11618152	0	0
T4	1809864	1800176	0	0
T13	3768968	3765384	0	0
T14	39541768	39540816	0	0
T15	2377424	2373336	0	0
T16	26324480	26324312	0	0
T17	2659104	2657312	0	0
T18	277872	274120	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	121705252	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	121705252	0	0
T1	24900	11862	0	0
T2	244269	137633	0	0
T3	207547	92008	0	0
T4	32319	27792	0	0
T13	67303	35386	0	0
T14	706103	689224	0	0
T15	42454	15914	0	0
T16	470080	22826	0	0
T17	47484	25762	0	0
T18	4962	4428	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	88625478	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	88625478	0	0
T1	24900	10396	0	0
T2	244269	81915	0	0
T3	207547	35338	0	0
T4	32319	17482	0	0
T13	67303	14476	0	0
T14	706103	5906	0	0
T15	42454	17247	0	0
T16	470080	177275	0	0
T17	47484	6934	0	0
T18	4962	2323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1374739	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1374739	0	0
T1	24900	185	0	0
T2	244269	1729	0	0
T3	207547	3100	0	0
T4	32319	646	0	0
T13	67303	768	0	0
T14	706103	287	0	0
T15	42454	0	0	0
T16	470080	2051	0	0
T17	47484	566	0	0
T18	4962	84	0	0
T19	0	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3513887	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3513887	0	0
T1	24900	116	0	0
T2	244269	1610	0	0
T3	207547	1822	0	0
T4	32319	646	0	0
T13	67303	711	0	0
T14	706103	57	0	0
T15	42454	0	0	0
T16	470080	160670	0	0
T17	47484	259	0	0
T18	4962	84	0	0
T19	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1429152	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1429152	0	0
T1	24900	148	0	0
T2	244269	1743	0	0
T3	207547	1751	0	0
T4	32319	683	0	0
T13	67303	467	0	0
T14	706103	292	0	0
T15	42454	0	0	0
T16	470080	1142	0	0
T17	47484	702	0	0
T18	4962	99	0	0
T19	0	277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2898793	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2898793	0	0
T1	24900	187	0	0
T2	244269	1740	0	0
T3	207547	614	0	0
T4	32319	683	0	0
T13	67303	356	0	0
T14	706103	723	0	0
T15	42454	0	0	0
T16	470080	79090	0	0
T17	47484	274	0	0
T18	4962	99	0	0
T19	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1399354	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1399354	0	0
T1	24900	144	0	0
T2	244269	3505	0	0
T3	207547	2419	0	0
T4	32319	659	0	0
T13	67303	698	0	0
T14	706103	192	0	0
T15	42454	1754	0	0
T16	470080	0	0	0
T17	47484	568	0	0
T18	4962	67	0	0
T19	0	350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2973482	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2973482	0	0
T1	24900	180	0	0
T2	244269	3340	0	0
T3	207547	926	0	0
T4	32319	659	0	0
T13	67303	560	0	0
T14	706103	42	0	0
T15	42454	1715	0	0
T16	470080	0	0	0
T17	47484	226	0	0
T18	4962	67	0	0
T19	0	366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1382025	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1382025	0	0
T1	24900	141	0	0
T2	244269	1405	0	0
T3	207547	1789	0	0
T4	32319	1191	0	0
T13	67303	719	0	0
T14	706103	271	0	0
T15	42454	1229	0	0
T16	470080	1234	0	0
T17	47484	619	0	0
T18	4962	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3258288	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3258288	0	0
T1	24900	177	0	0
T2	244269	1528	0	0
T3	207547	881	0	0
T4	32319	1191	0	0
T13	67303	489	0	0
T14	706103	528	0	0
T15	42454	1654	0	0
T16	470080	99861	0	0
T17	47484	245	0	0
T18	4962	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1356621	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1356621	0	0
T1	24900	224	0	0
T2	244269	3633	0	0
T3	207547	2001	0	0
T4	32319	409	0	0
T13	67303	509	0	0
T14	706103	229	0	0
T15	42454	0	0	0
T16	470080	3281	0	0
T17	47484	582	0	0
T18	4962	93	0	0
T19	0	293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3303539	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3303539	0	0
T1	24900	262	0	0
T2	244269	3614	0	0
T3	207547	786	0	0
T4	32319	409	0	0
T13	67303	287	0	0
T14	706103	590	0	0
T15	42454	0	0	0
T16	470080	259428	0	0
T17	47484	271	0	0
T18	4962	93	0	0
T19	0	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1430437	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1430437	0	0
T1	24900	152	0	0
T2	244269	1505	0	0
T3	207547	1810	0	0
T4	32319	882	0	0
T13	67303	565	0	0
T14	706103	261	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	645	0	0
T18	4962	100	0	0
T19	0	378	0	0
T20	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3035237	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3035237	0	0
T1	24900	98	0	0
T2	244269	1539	0	0
T3	207547	2196	0	0
T4	32319	882	0	0
T13	67303	523	0	0
T14	706103	66	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	243	0	0
T18	4962	100	0	0
T19	0	85	0	0
T20	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1411551	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1411551	0	0
T1	24900	160	0	0
T2	244269	1820	0	0
T3	207547	1789	0	0
T4	32319	414	0	0
T13	67303	534	0	0
T14	706103	226	0	0
T15	42454	1444	0	0
T16	470080	0	0	0
T17	47484	570	0	0
T18	4962	85	0	0
T19	0	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3485693	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3485693	0	0
T1	24900	179	0	0
T2	244269	1822	0	0
T3	207547	2800	0	0
T4	32319	414	0	0
T13	67303	412	0	0
T14	706103	46	0	0
T15	42454	1706	0	0
T16	470080	0	0	0
T17	47484	283	0	0
T18	4962	85	0	0
T19	0	540	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1379555	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1379555	0	0
T1	24900	196	0	0
T2	244269	1608	0	0
T3	207547	2587	0	0
T4	32319	646	0	0
T13	67303	745	0	0
T14	706103	285	0	0
T15	42454	0	0	0
T16	470080	1282	0	0
T17	47484	629	0	0
T18	4962	90	0	0
T19	0	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3933431	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3933431	0	0
T1	24900	238	0	0
T2	244269	1612	0	0
T3	207547	2748	0	0
T4	32319	646	0	0
T13	67303	668	0	0
T14	706103	399	0	0
T15	42454	0	0	0
T16	470080	82506	0	0
T17	47484	229	0	0
T18	4962	90	0	0
T19	0	852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1404825	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1404825	0	0
T1	24900	224	0	0
T2	244269	1768	0	0
T3	207547	3154	0	0
T4	32319	407	0	0
T13	67303	561	0	0
T14	706103	225	0	0
T15	42454	2823	0	0
T16	470080	1232	0	0
T17	47484	646	0	0
T18	4962	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3344138	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3344138	0	0
T1	24900	222	0	0
T2	244269	1785	0	0
T3	207547	1990	0	0
T4	32319	407	0	0
T13	67303	486	0	0
T14	706103	858	0	0
T15	42454	3899	0	0
T16	470080	99271	0	0
T17	47484	284	0	0
T18	4962	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1395981	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1395981	0	0
T1	24900	154	0	0
T2	244269	3678	0	0
T3	207547	1915	0	0
T4	32319	906	0	0
T13	67303	573	0	0
T14	706103	196	0	0
T15	42454	2051	0	0
T16	470080	0	0	0
T17	47484	637	0	0
T18	4962	90	0	0
T19	0	366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2968481	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2968481	0	0
T1	24900	154	0	0
T2	244269	3597	0	0
T3	207547	428	0	0
T4	32319	906	0	0
T13	67303	527	0	0
T14	706103	50	0	0
T15	42454	1942	0	0
T16	470080	0	0	0
T17	47484	302	0	0
T18	4962	90	0	0
T19	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1363546	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1363546	0	0
T1	24900	150	0	0
T2	244269	1342	0	0
T3	207547	1994	0	0
T4	32319	635	0	0
T13	67303	684	0	0
T14	706103	255	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	571	0	0
T18	4962	91	0	0
T19	0	351	0	0
T20	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3260994	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3260994	0	0
T1	24900	119	0	0
T2	244269	1476	0	0
T3	207547	1199	0	0
T4	32319	635	0	0
T13	67303	478	0	0
T14	706103	795	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	251	0	0
T18	4962	91	0	0
T19	0	86	0	0
T20	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1424154	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1424154	0	0
T1	24900	129	0	0
T2	244269	1756	0	0
T3	207547	1799	0	0
T4	32319	411	0	0
T13	67303	633	0	0
T14	706103	207	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	436	0	0
T18	4962	93	0	0
T19	0	375	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	4034996	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	4034996	0	0
T1	24900	152	0	0
T2	244269	1590	0	0
T3	207547	1138	0	0
T4	32319	411	0	0
T13	67303	511	0	0
T14	706103	52	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	164	0	0
T18	4962	93	0	0
T19	0	299	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1378314	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1378314	0	0
T1	24900	178	0	0
T2	244269	1654	0	0
T3	207547	1318	0	0
T4	32319	852	0	0
T13	67303	658	0	0
T14	706103	248	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	600	0	0
T18	4962	83	0	0
T19	0	407	0	0
T20	0	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2269293	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2269293	0	0
T1	24900	164	0	0
T2	244269	1596	0	0
T3	207547	1434	0	0
T4	32319	852	0	0
T13	67303	602	0	0
T14	706103	55	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	293	0	0
T18	4962	83	0	0
T19	0	108	0	0
T20	0	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1435693	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1435693	0	0
T1	24900	161	0	0
T2	244269	3567	0	0
T3	207547	2160	0	0
T4	32319	868	0	0
T13	67303	747	0	0
T14	706103	160	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	605	0	0
T18	4962	90	0	0
T19	0	331	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3926923	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3926923	0	0
T1	24900	181	0	0
T2	244269	3562	0	0
T3	207547	777	0	0
T4	32319	868	0	0
T13	67303	553	0	0
T14	706103	41	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	278	0	0
T18	4962	90	0	0
T19	0	498	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1377006	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1377006	0	0
T1	24900	236	0	0
T2	244269	5427	0	0
T3	207547	211	0	0
T4	32319	396	0	0
T13	67303	597	0	0
T14	706103	226	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	417	0	0
T18	4962	60	0	0
T19	0	283	0	0
T20	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3439142	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3439142	0	0
T1	24900	212	0	0
T2	244269	5212	0	0
T3	207547	415	0	0
T4	32319	396	0	0
T13	67303	565	0	0
T14	706103	414	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	203	0	0
T18	4962	60	0	0
T19	0	639	0	0
T20	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1392364	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1392364	0	0
T1	24900	137	0	0
T2	244269	1738	0	0
T3	207547	1617	0	0
T4	32319	388	0	0
T13	67303	733	0	0
T14	706103	207	0	0
T15	42454	4201	0	0
T16	470080	1026	0	0
T17	47484	581	0	0
T18	4962	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2802342	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2802342	0	0
T1	24900	121	0	0
T2	244269	1603	0	0
T3	207547	684	0	0
T4	32319	388	0	0
T13	67303	643	0	0
T14	706103	48	0	0
T15	42454	4103	0	0
T16	470080	72685	0	0
T17	47484	262	0	0
T18	4962	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1339492	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1339492	0	0
T1	24900	100	0	0
T2	244269	1625	0	0
T3	207547	718	0	0
T4	32319	415	0	0
T13	67303	663	0	0
T14	706103	203	0	0
T15	42454	0	0	0
T16	470080	917	0	0
T17	47484	576	0	0
T18	4962	97	0	0
T19	0	301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3027309	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3027309	0	0
T1	24900	111	0	0
T2	244269	1616	0	0
T3	207547	1173	0	0
T4	32319	415	0	0
T13	67303	557	0	0
T14	706103	50	0	0
T15	42454	0	0	0
T16	470080	76066	0	0
T17	47484	215	0	0
T18	4962	97	0	0
T19	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1421343	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1421343	0	0
T1	24900	173	0	0
T2	244269	3312	0	0
T3	207547	2004	0	0
T4	32319	375	0	0
T13	67303	624	0	0
T14	706103	175	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	677	0	0
T18	4962	89	0	0
T19	0	266	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3199375	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3199375	0	0
T1	24900	191	0	0
T2	244269	3197	0	0
T3	207547	437	0	0
T4	32319	375	0	0
T13	67303	521	0	0
T14	706103	43	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	328	0	0
T18	4962	89	0	0
T19	0	610	0	0
T20	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1413472	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1413472	0	0
T1	24900	164	0	0
T2	244269	1845	0	0
T3	207547	654	0	0
T4	32319	419	0	0
T13	67303	716	0	0
T14	706103	236	0	0
T15	42454	2411	0	0
T16	470080	1244	0	0
T17	47484	633	0	0
T18	4962	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3468477	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3468477	0	0
T1	24900	185	0	0
T2	244269	1744	0	0
T3	207547	1035	0	0
T4	32319	419	0	0
T13	67303	569	0	0
T14	706103	60	0	0
T15	42454	2227	0	0
T16	470080	98468	0	0
T17	47484	239	0	0
T18	4962	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1382104	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1382104	0	0
T1	24900	145	0	0
T2	244269	3650	0	0
T3	207547	978	0	0
T4	32319	420	0	0
T13	67303	758	0	0
T14	706103	187	0	0
T15	42454	0	0	0
T16	470080	2305	0	0
T17	47484	781	0	0
T18	4962	85	0	0
T19	0	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3790709	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3790709	0	0
T1	24900	122	0	0
T2	244269	3834	0	0
T3	207547	732	0	0
T4	32319	420	0	0
T13	67303	570	0	0
T14	706103	44	0	0
T15	42454	0	0	0
T16	470080	191863	0	0
T17	47484	340	0	0
T18	4962	85	0	0
T19	0	490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1380504	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1380504	0	0
T1	24900	162	0	0
T2	244269	3159	0	0
T3	207547	3353	0	0
T4	32319	675	0	0
T13	67303	609	0	0
T14	706103	236	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	558	0	0
T18	4962	90	0	0
T19	0	276	0	0
T20	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3887479	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3887479	0	0
T1	24900	156	0	0
T2	244269	3024	0	0
T3	207547	2337	0	0
T4	32319	675	0	0
T13	67303	583	0	0
T14	706103	59	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	218	0	0
T18	4962	90	0	0
T19	0	73	0	0
T20	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1389422	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1389422	0	0
T1	24900	227	0	0
T2	244269	1693	0	0
T3	207547	157	0	0
T4	32319	596	0	0
T13	67303	515	0	0
T14	706103	243	0	0
T15	42454	0	0	0
T16	470080	967	0	0
T17	47484	522	0	0
T18	4962	79	0	0
T19	0	354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3354560	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3354560	0	0
T1	24900	208	0	0
T2	244269	1567	0	0
T3	207547	1	0	0
T4	32319	596	0	0
T13	67303	442	0	0
T14	706103	56	0	0
T15	42454	0	0	0
T16	470080	79115	0	0
T17	47484	244	0	0
T18	4962	79	0	0
T19	0	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1435806	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1435806	0	0
T1	24900	227	0	0
T2	244269	1801	0	0
T3	207547	5191	0	0
T4	32319	589	0	0
T13	67303	615	0	0
T14	706103	223	0	0
T15	42454	0	0	0
T16	470080	1204	0	0
T17	47484	481	0	0
T18	4962	85	0	0
T19	0	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2848238	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2848238	0	0
T1	24900	221	0	0
T2	244269	1591	0	0
T3	207547	1432	0	0
T4	32319	589	0	0
T13	67303	585	0	0
T14	706103	47	0	0
T15	42454	0	0	0
T16	470080	96086	0	0
T17	47484	256	0	0
T18	4962	85	0	0
T19	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1385646	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1385646	0	0
T1	24900	228	0	0
T2	244269	1599	0	0
T3	207547	3205	0	0
T4	32319	402	0	0
T13	67303	625	0	0
T14	706103	238	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	726	0	0
T18	4962	78	0	0
T19	0	411	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2566392	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2566392	0	0
T1	24900	212	0	0
T2	244269	1626	0	0
T3	207547	3242	0	0
T4	32319	402	0	0
T13	67303	504	0	0
T14	706103	610	0	0
T15	42454	0	0	0
T16	470080	0	0	0
T17	47484	284	0	0
T18	4962	78	0	0
T19	0	328	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1364807	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1364807	0	0
T1	24900	97	0	0
T2	244269	1536	0	0
T3	207547	2631	0	0
T4	32319	984	0	0
T13	67303	598	0	0
T14	706103	210	0	0
T15	42454	0	0	0
T16	470080	2409	0	0
T17	47484	654	0	0
T18	4962	85	0	0
T19	0	359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3220061	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3220061	0	0
T1	24900	92	0	0
T2	244269	1671	0	0
T3	207547	1006	0	0
T4	32319	984	0	0
T13	67303	480	0	0
T14	706103	61	0	0
T15	42454	0	0	0
T16	470080	178276	0	0
T17	47484	308	0	0
T18	4962	85	0	0
T19	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1353790	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1353790	0	0
T1	24900	149	0	0
T2	244269	1480	0	0
T3	207547	833	0	0
T4	32319	413	0	0
T13	67303	808	0	0
T14	706103	232	0	0
T15	42454	0	0	0
T16	470080	1434	0	0
T17	47484	456	0	0
T18	4962	81	0	0
T19	0	306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	3321976	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	3321976	0	0
T1	24900	88	0	0
T2	244269	1413	0	0
T3	207547	1201	0	0
T4	32319	413	0	0
T13	67303	602	0	0
T14	706103	49	0	0
T15	42454	0	0	0
T16	470080	109000	0	0
T17	47484	215	0	0
T18	4962	81	0	0
T19	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	1378951	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	1378951	0	0
T1	24900	228	0	0
T2	244269	1504	0	0
T3	207547	1421	0	0
T4	32319	424	0	0
T13	67303	688	0	0
T14	706103	300	0	0
T15	42454	0	0	0
T16	470080	1098	0	0
T17	47484	633	0	0
T18	4962	68	0	0
T19	0	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303776116	2426384	0	0
DepthKnown_A	303776116	303659626	0	0
RvalidKnown_A	303776116	303659626	0	0
WreadyKnown_A	303776116	303659626	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	2426384	0	0
T1	24900	206	0	0
T2	244269	1500	0	0
T3	207547	1904	0	0
T4	32319	424	0	0
T13	67303	692	0	0
T14	706103	63	0	0
T15	42454	0	0	0
T16	470080	90368	0	0
T17	47484	217	0	0
T18	4962	68	0	0
T19	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303776116	303659626	0	0
T1	24900	24857	0	0
T2	244269	244198	0	0
T3	207547	207467	0	0
T4	32319	32146	0	0
T13	67303	67239	0	0
T14	706103	706086	0	0
T15	42454	42381	0	0
T16	470080	470077	0	0
T17	47484	47452	0	0
T18	4962	4895	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0