Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1671303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263174

1

T1

68

T2

33

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	653914	1			T1	167		T2	149		T3	26
values[0x0]	625904	1			T1	163		T2	26		T3	4
values[0x1]	654659	1			T1	165		T2	166		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1295247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639230

1

T1

168

T2

123

T3

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7674	1			T1	1		T2	1		T4	2
valid_sources[0x01]	9552	1			T1	1		T4	3		T5	8
valid_sources[0x02]	7278	1			T2	2		T3	1		T4	1
valid_sources[0x03]	6941	1			T1	1		T2	4		T4	1
valid_sources[0x04]	6989	1			T1	5		T2	2		T4	9
valid_sources[0x05]	9344	1			T1	3		T4	4		T16	8
valid_sources[0x06]	7260	1			T2	1		T4	3		T5	7
valid_sources[0x07]	8345	1			T1	4		T2	1		T3	1
valid_sources[0x08]	7325	1			T1	3		T2	3		T4	3
valid_sources[0x09]	8124	1			T1	4		T2	3		T4	1
valid_sources[0x0a]	6821	1			T2	1		T4	1		T5	8
valid_sources[0x0b]	7422	1			T1	2		T2	2		T4	2
valid_sources[0x0c]	7437	1			T1	2		T5	6		T24	8
valid_sources[0x0d]	9549	1			T1	2		T2	1		T4	1
valid_sources[0x0e]	6387	1			T1	1		T2	1		T4	2
valid_sources[0x0f]	6896	1			T1	2		T2	3		T4	2
valid_sources[0x10]	7891	1			T1	2		T4	3		T5	6
valid_sources[0x11]	7787	1			T1	4		T2	6		T4	4
valid_sources[0x12]	8267	1			T1	2		T4	1		T5	6
valid_sources[0x13]	8346	1			T2	1		T4	5		T5	8
valid_sources[0x14]	7511	1			T1	1		T2	6		T3	1
valid_sources[0x15]	7344	1			T4	7		T5	7		T15	1
valid_sources[0x16]	7497	1			T1	2		T3	1		T4	4
valid_sources[0x17]	7894	1			T1	2		T2	1		T5	5
valid_sources[0x18]	7503	1			T1	2		T3	1		T5	7
valid_sources[0x19]	6844	1			T1	2		T4	5		T5	7
valid_sources[0x1a]	7937	1			T4	3		T5	6		T19	1
valid_sources[0x1b]	7161	1			T4	5		T5	7		T15	1
valid_sources[0x1c]	7032	1			T1	1		T2	1		T4	2
valid_sources[0x1d]	7564	1			T1	2		T2	1		T4	4
valid_sources[0x1e]	7804	1			T2	2		T4	3		T5	10
valid_sources[0x1f]	8071	1			T1	2		T2	2		T4	5
valid_sources[0x20]	7300	1			T1	2		T2	2		T4	2
valid_sources[0x21]	6718	1			T2	2		T4	1		T5	7
valid_sources[0x22]	7393	1			T1	2		T4	2		T5	6
valid_sources[0x23]	8377	1			T1	3		T4	6		T5	7
valid_sources[0x24]	7533	1			T1	1		T2	1		T4	5
valid_sources[0x25]	11483	1			T1	3		T2	1		T4	3
valid_sources[0x26]	6792	1			T1	3		T2	2		T5	7
valid_sources[0x27]	7130	1			T1	2		T2	2		T4	2
valid_sources[0x28]	7806	1			T4	1		T5	7		T15	2
valid_sources[0x29]	7017	1			T1	2		T4	3		T5	8
valid_sources[0x2a]	7163	1			T1	3		T2	1		T4	5
valid_sources[0x2b]	9686	1			T1	1		T2	2		T4	3
valid_sources[0x2c]	7802	1			T1	3		T2	1		T4	4
valid_sources[0x2d]	7215	1			T4	1		T5	6		T15	2
valid_sources[0x2e]	6853	1			T1	4		T2	1		T4	3
valid_sources[0x2f]	7981	1			T1	1		T2	1		T3	2
valid_sources[0x30]	7648	1			T1	3		T4	2		T5	7
valid_sources[0x31]	7840	1			T1	3		T4	4		T5	7
valid_sources[0x32]	7446	1			T2	2		T4	5		T5	6
valid_sources[0x33]	8059	1			T1	4		T4	3		T5	7
valid_sources[0x34]	6894	1			T1	2		T2	2		T4	2
valid_sources[0x35]	7526	1			T1	2		T2	1		T4	5
valid_sources[0x36]	6976	1			T1	2		T2	1		T4	4
valid_sources[0x37]	7020	1			T1	5		T3	1		T4	1
valid_sources[0x38]	7212	1			T1	4		T2	2		T4	2
valid_sources[0x39]	7436	1			T1	1		T4	1		T5	7
valid_sources[0x3a]	7466	1			T1	1		T2	2		T4	7
valid_sources[0x3b]	7839	1			T1	3		T2	2		T4	2
valid_sources[0x3c]	7982	1			T1	3		T2	1		T3	1
valid_sources[0x3d]	7513	1			T1	2		T2	1		T4	1
valid_sources[0x3e]	6881	1			T1	2		T2	1		T4	2
valid_sources[0x3f]	7042	1			T1	1		T2	1		T4	2
valid_sources[0x40]	6871	1			T2	2		T5	7		T15	3
valid_sources[0x41]	7731	1			T1	5		T2	1		T4	9
valid_sources[0x42]	7364	1			T1	1		T2	1		T4	3
valid_sources[0x43]	7667	1			T4	1		T5	8		T15	1
valid_sources[0x44]	7695	1			T1	3		T2	2		T4	5
valid_sources[0x45]	7106	1			T2	1		T4	6		T5	8
valid_sources[0x46]	8378	1			T1	1		T4	4		T5	5
valid_sources[0x47]	7088	1			T1	3		T2	1		T4	5
valid_sources[0x48]	8021	1			T1	2		T4	7		T5	8
valid_sources[0x49]	7551	1			T1	1		T2	1		T4	2
valid_sources[0x4a]	6599	1			T1	1		T2	1		T4	2
valid_sources[0x4b]	7445	1			T1	2		T2	4		T3	1
valid_sources[0x4c]	8642	1			T1	1		T2	3		T4	3
valid_sources[0x4d]	7633	1			T1	3		T2	1		T3	1
valid_sources[0x4e]	6611	1			T1	2		T3	1		T4	4
valid_sources[0x4f]	7460	1			T1	1		T2	2		T3	2
valid_sources[0x50]	7277	1			T1	2		T5	6		T15	2
valid_sources[0x51]	7350	1			T1	1		T2	1		T4	2
valid_sources[0x52]	7412	1			T1	2		T4	5		T5	7
valid_sources[0x53]	7420	1			T1	1		T2	1		T3	1
valid_sources[0x54]	7096	1			T1	1		T3	1		T4	2
valid_sources[0x55]	7107	1			T1	4		T4	2		T5	7
valid_sources[0x56]	8093	1			T1	1		T2	1		T4	3
valid_sources[0x57]	6844	1			T1	2		T4	5		T5	7
valid_sources[0x58]	7716	1			T1	5		T2	3		T16	12
valid_sources[0x59]	7881	1			T2	1		T4	6		T5	6
valid_sources[0x5a]	7819	1			T1	2		T2	3		T3	1
valid_sources[0x5b]	7496	1			T1	3		T2	1		T4	1
valid_sources[0x5c]	7543	1			T3	1		T4	3		T5	6
valid_sources[0x5d]	8590	1			T1	4		T2	4		T3	1
valid_sources[0x5e]	8188	1			T1	2		T3	1		T4	1
valid_sources[0x5f]	8272	1			T1	2		T2	6		T5	6
valid_sources[0x60]	7203	1			T1	3		T5	6		T15	3
valid_sources[0x61]	7297	1			T1	2		T4	9		T5	6
valid_sources[0x62]	7259	1			T2	3		T3	1		T4	1
valid_sources[0x63]	7265	1			T1	2		T2	2		T4	3
valid_sources[0x64]	6985	1			T2	1		T3	1		T4	6
valid_sources[0x65]	7389	1			T1	1		T4	1		T5	8
valid_sources[0x66]	6694	1			T1	4		T2	1		T4	1
valid_sources[0x67]	8234	1			T1	1		T2	2		T4	3
valid_sources[0x68]	7314	1			T1	2		T2	3		T4	1
valid_sources[0x69]	7590	1			T1	3		T4	6		T16	2
valid_sources[0x6a]	7079	1			T1	3		T2	2		T4	1
valid_sources[0x6b]	7041	1			T1	1		T2	2		T4	1
valid_sources[0x6c]	7726	1			T1	3		T2	1		T4	7
valid_sources[0x6d]	7603	1			T1	2		T2	2		T3	1
valid_sources[0x6e]	6753	1			T1	2		T2	4		T4	2
valid_sources[0x6f]	6728	1			T1	1		T2	3		T3	1
valid_sources[0x70]	7321	1			T2	1		T4	3		T5	6
valid_sources[0x71]	7446	1			T1	1		T4	5		T5	7
valid_sources[0x72]	7666	1			T2	3		T4	3		T5	5
valid_sources[0x73]	6931	1			T1	1		T2	1		T4	2
valid_sources[0x74]	7201	1			T1	3		T2	2		T4	5
valid_sources[0x75]	8170	1			T2	2		T3	1		T4	1
valid_sources[0x76]	7192	1			T1	1		T4	2		T5	6
valid_sources[0x77]	6855	1			T1	3		T2	2		T4	1
valid_sources[0x78]	7672	1			T1	3		T2	1		T4	3
valid_sources[0x79]	8141	1			T1	2		T2	1		T4	4
valid_sources[0x7a]	7105	1			T1	3		T2	1		T4	1
valid_sources[0x7b]	8664	1			T1	1		T3	1		T4	3
valid_sources[0x7c]	8308	1			T1	1		T2	1		T4	4
valid_sources[0x7d]	7098	1			T1	4		T2	4		T4	1
valid_sources[0x7e]	7402	1			T3	1		T4	4		T5	7
valid_sources[0x7f]	6727	1			T1	2		T2	1		T4	5
valid_sources[0x80]	9069	1			T1	7		T2	2		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27749

1

T1

6

T2

12

T3

2

values[0x0]

all_enables

biggest_size

208039

1

T1

54

T2

12

T4

98

values[0x1]

all_enables

biggest_size

27386

1

T1

8

T2

9

T3

2