Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335680485	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335680485	0	0
T1	59304	2423	0	0
T2	828296	35087	0	0
T3	186872	6263	0	0
T4	938056	13185	0	0
T5	9522632	1307751	0	0
T15	43568	1692	0	0
T16	251328	8100	0	0
T17	645848	15226	0	0
T18	8707104	1603165	0	0
T19	38920	865	0	0
T20	0	1786	0	0
T21	0	948	0	0
T22	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	59304	58520	0	0
T2	828296	825216	0	0
T3	186872	185304	0	0
T4	938056	933856	0	0
T5	9522632	9522240	0	0
T15	43568	40936	0	0
T16	251328	247072	0	0
T17	645848	622720	0	0
T18	8707104	8706824	0	0
T19	38920	35728	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	59304	58520	0	0
T2	828296	825216	0	0
T3	186872	185304	0	0
T4	938056	933856	0	0
T5	9522632	9522240	0	0
T15	43568	40936	0	0
T16	251328	247072	0	0
T17	645848	622720	0	0
T18	8707104	8706824	0	0
T19	38920	35728	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	59304	58520	0	0
T2	828296	825216	0	0
T3	186872	185304	0	0
T4	938056	933856	0	0
T5	9522632	9522240	0	0
T15	43568	40936	0	0
T16	251328	247072	0	0
T17	645848	622720	0	0
T18	8707104	8706824	0	0
T19	38920	35728	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	123007932	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	123007932	0	0
T1	1059	942	0	0
T2	14791	12675	0	0
T3	3337	3107	0	0
T4	16751	5788	0	0
T5	170047	7759	0	0
T15	778	423	0	0
T16	4488	3994	0	0
T17	11533	6187	0	0
T18	155484	753194	0	0
T19	695	337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	87701807	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	87701807	0	0
T1	1059	495	0	0
T2	14791	7676	0	0
T3	3337	1586	0	0
T4	16751	2160	0	0
T5	170047	646126	0	0
T15	778	423	0	0
T16	4488	2040	0	0
T17	11533	3342	0	0
T18	155484	174990	0	0
T19	695	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1405216	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1405216	0	0
T1	1059	13	0	0
T2	14791	177	0	0
T3	3337	33	0	0
T4	16751	136	0	0
T5	170047	0	0	0
T15	778	211	0	0
T16	4488	36	0	0
T17	11533	128	0	0
T18	155484	18088	0	0
T19	695	6	0	0
T20	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2907157	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2907157	0	0
T1	1059	13	0	0
T2	14791	177	0	0
T3	3337	33	0	0
T4	16751	86	0	0
T5	170047	0	0	0
T15	778	211	0	0
T16	4488	36	0	0
T17	11533	106	0	0
T18	155484	4479	0	0
T19	695	6	0	0
T20	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1423655	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1423655	0	0
T1	1059	27	0	0
T2	14791	468	0	0
T3	3337	21	0	0
T4	16751	131	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	26	0	0
T17	11533	92	0	0
T18	155484	19197	0	0
T19	695	4	0	0
T20	0	27	0	0
T21	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2978409	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2978409	0	0
T1	1059	27	0	0
T2	14791	468	0	0
T3	3337	21	0	0
T4	16751	33	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	26	0	0
T17	11533	62	0	0
T18	155484	6992	0	0
T19	695	4	0	0
T20	0	27	0	0
T21	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1449513	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1449513	0	0
T1	1059	24	0	0
T2	14791	447	0	0
T3	3337	29	0	0
T4	16751	82	0	0
T5	170047	887	0	0
T15	778	0	0	0
T16	4488	41	0	0
T17	11533	96	0	0
T18	155484	19429	0	0
T19	695	8	0	0
T20	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3123660	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3123660	0	0
T1	1059	24	0	0
T2	14791	447	0	0
T3	3337	29	0	0
T4	16751	24	0	0
T5	170047	75883	0	0
T15	778	0	0	0
T16	4488	41	0	0
T17	11533	57	0	0
T18	155484	7167	0	0
T19	695	8	0	0
T20	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1412388	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1412388	0	0
T1	1059	17	0	0
T2	14791	163	0	0
T3	3337	27	0	0
T4	16751	81	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	34	0	0
T17	11533	46	0	0
T18	155484	17319	0	0
T19	695	5	0	0
T20	0	45	0	0
T21	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3081330	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3081330	0	0
T1	1059	17	0	0
T2	14791	163	0	0
T3	3337	27	0	0
T4	16751	55	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	34	0	0
T17	11533	39	0	0
T18	155484	6182	0	0
T19	695	5	0	0
T20	0	45	0	0
T21	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1367286	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1367286	0	0
T1	1059	15	0	0
T2	14791	375	0	0
T3	3337	35	0	0
T4	16751	138	0	0
T5	170047	1025	0	0
T15	778	0	0	0
T16	4488	46	0	0
T17	11533	76	0	0
T18	155484	19060	0	0
T19	695	4	0	0
T20	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3192115	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3192115	0	0
T1	1059	15	0	0
T2	14791	375	0	0
T3	3337	35	0	0
T4	16751	59	0	0
T5	170047	85377	0	0
T15	778	0	0	0
T16	4488	46	0	0
T17	11533	81	0	0
T18	155484	7237	0	0
T19	695	4	0	0
T20	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1446296	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1446296	0	0
T1	1059	16	0	0
T2	14791	387	0	0
T3	3337	38	0	0
T4	16751	113	0	0
T5	170047	0	0	0
T15	778	212	0	0
T16	4488	40	0	0
T17	11533	27	0	0
T18	155484	13086	0	0
T19	695	6	0	0
T20	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2982948	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2982948	0	0
T1	1059	16	0	0
T2	14791	387	0	0
T3	3337	38	0	0
T4	16751	61	0	0
T5	170047	0	0	0
T15	778	212	0	0
T16	4488	40	0	0
T17	11533	47	0	0
T18	155484	3934	0	0
T19	695	6	0	0
T20	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1420136	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1420136	0	0
T1	1059	20	0	0
T2	14791	153	0	0
T3	3337	23	0	0
T4	16751	152	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	38	0	0
T17	11533	113	0	0
T18	155484	21477	0	0
T19	695	13	0	0
T20	0	40	0	0
T21	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3635918	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3635918	0	0
T1	1059	20	0	0
T2	14791	153	0	0
T3	3337	23	0	0
T4	16751	45	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	38	0	0
T17	11533	102	0	0
T18	155484	6981	0	0
T19	695	13	0	0
T20	0	40	0	0
T21	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1441414	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1441414	0	0
T1	1059	26	0	0
T2	14791	155	0	0
T3	3337	27	0	0
T4	16751	146	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	31	0	0
T17	11533	72	0	0
T18	155484	16802	0	0
T19	695	3	0	0
T20	0	26	0	0
T21	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2902561	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2902561	0	0
T1	1059	26	0	0
T2	14791	155	0	0
T3	3337	27	0	0
T4	16751	80	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	31	0	0
T17	11533	47	0	0
T18	155484	5542	0	0
T19	695	3	0	0
T20	0	26	0	0
T21	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1416339	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1416339	0	0
T1	1059	23	0	0
T2	14791	180	0	0
T3	3337	30	0	0
T4	16751	145	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	44	0	0
T17	11533	50	0	0
T18	155484	19434	0	0
T19	695	14	0	0
T20	0	29	0	0
T21	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	4032440	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	4032440	0	0
T1	1059	23	0	0
T2	14791	180	0	0
T3	3337	30	0	0
T4	16751	44	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	44	0	0
T17	11533	58	0	0
T18	155484	4991	0	0
T19	695	14	0	0
T20	0	29	0	0
T21	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1403415	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1403415	0	0
T1	1059	19	0	0
T2	14791	434	0	0
T3	3337	25	0	0
T4	16751	103	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	39	0	0
T17	11533	151	0	0
T18	155484	17177	0	0
T19	695	5	0	0
T20	0	33	0	0
T21	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3193821	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3193821	0	0
T1	1059	19	0	0
T2	14791	434	0	0
T3	3337	25	0	0
T4	16751	66	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	39	0	0
T17	11533	130	0	0
T18	155484	7965	0	0
T19	695	5	0	0
T20	0	33	0	0
T21	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1427895	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1427895	0	0
T1	1059	20	0	0
T2	14791	151	0	0
T3	3337	26	0	0
T4	16751	128	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	30	0	0
T17	11533	81	0	0
T18	155484	22176	0	0
T19	695	9	0	0
T20	0	32	0	0
T21	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2916210	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2916210	0	0
T1	1059	20	0	0
T2	14791	151	0	0
T3	3337	26	0	0
T4	16751	34	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	30	0	0
T17	11533	59	0	0
T18	155484	5677	0	0
T19	695	9	0	0
T20	0	32	0	0
T21	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1429887	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1429887	0	0
T1	1059	20	0	0
T2	14791	156	0	0
T3	3337	17	0	0
T4	16751	140	0	0
T5	170047	1261	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	344	0	0
T18	155484	23140	0	0
T19	695	5	0	0
T20	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3438323	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3438323	0	0
T1	1059	20	0	0
T2	14791	156	0	0
T3	3337	17	0	0
T4	16751	68	0	0
T5	170047	114076	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	299	0	0
T18	155484	8420	0	0
T19	695	5	0	0
T20	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1379888	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1379888	0	0
T1	1059	16	0	0
T2	14791	466	0	0
T3	3337	27	0	0
T4	16751	140	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	34	0	0
T17	11533	547	0	0
T18	155484	13888	0	0
T19	695	2	0	0
T20	0	38	0	0
T21	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2124775	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2124775	0	0
T1	1059	16	0	0
T2	14791	466	0	0
T3	3337	27	0	0
T4	16751	102	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	34	0	0
T17	11533	616	0	0
T18	155484	4765	0	0
T19	695	2	0	0
T20	0	38	0	0
T21	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1445297	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1445297	0	0
T1	1059	21	0	0
T2	14791	182	0	0
T3	3337	25	0	0
T4	16751	144	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	30	0	0
T17	11533	57	0	0
T18	155484	21736	0	0
T19	695	6	0	0
T20	0	40	0	0
T21	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	2820420	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	2820420	0	0
T1	1059	21	0	0
T2	14791	182	0	0
T3	3337	25	0	0
T4	16751	38	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	30	0	0
T17	11533	87	0	0
T18	155484	5772	0	0
T19	695	6	0	0
T20	0	40	0	0
T21	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1427409	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1427409	0	0
T1	1059	21	0	0
T2	14791	183	0	0
T3	3337	28	0	0
T4	16751	167	0	0
T5	170047	2227	0	0
T15	778	0	0	0
T16	4488	36	0	0
T17	11533	55	0	0
T18	155484	15805	0	0
T19	695	9	0	0
T20	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	4219859	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	4219859	0	0
T1	1059	21	0	0
T2	14791	183	0	0
T3	3337	28	0	0
T4	16751	59	0	0
T5	170047	182598	0	0
T15	778	0	0	0
T16	4488	36	0	0
T17	11533	51	0	0
T18	155484	6064	0	0
T19	695	9	0	0
T20	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1378263	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1378263	0	0
T1	1059	20	0	0
T2	14791	171	0	0
T3	3337	38	0	0
T4	16751	106	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	64	0	0
T18	155484	18474	0	0
T19	695	8	0	0
T20	0	36	0	0
T21	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3251592	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3251592	0	0
T1	1059	20	0	0
T2	14791	171	0	0
T3	3337	38	0	0
T4	16751	51	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	40	0	0
T18	155484	7463	0	0
T19	695	8	0	0
T20	0	36	0	0
T21	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1411859	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1411859	0	0
T1	1059	15	0	0
T2	14791	182	0	0
T3	3337	30	0	0
T4	16751	129	0	0
T5	170047	1279	0	0
T15	778	0	0	0
T16	4488	48	0	0
T17	11533	65	0	0
T18	155484	22886	0	0
T19	695	4	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3191577	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3191577	0	0
T1	1059	15	0	0
T2	14791	182	0	0
T3	3337	30	0	0
T4	16751	70	0	0
T5	170047	97865	0	0
T15	778	0	0	0
T16	4488	48	0	0
T17	11533	92	0	0
T18	155484	5711	0	0
T19	695	4	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1437316	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1437316	0	0
T1	1059	14	0	0
T2	14791	621	0	0
T3	3337	23	0	0
T4	16751	122	0	0
T5	170047	1070	0	0
T15	778	0	0	0
T16	4488	52	0	0
T17	11533	100	0	0
T18	155484	17006	0	0
T19	695	5	0	0
T20	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3102817	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3102817	0	0
T1	1059	14	0	0
T2	14791	621	0	0
T3	3337	23	0	0
T4	16751	71	0	0
T5	170047	90318	0	0
T15	778	0	0	0
T16	4488	52	0	0
T17	11533	122	0	0
T18	155484	7152	0	0
T19	695	5	0	0
T20	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1412574	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1412574	0	0
T1	1059	15	0	0
T2	14791	151	0	0
T3	3337	31	0	0
T4	16751	130	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	36	0	0
T17	11533	101	0	0
T18	155484	18843	0	0
T19	695	7	0	0
T20	0	32	0	0
T21	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3334738	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3334738	0	0
T1	1059	15	0	0
T2	14791	151	0	0
T3	3337	31	0	0
T4	16751	27	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	36	0	0
T17	11533	87	0	0
T18	155484	7498	0	0
T19	695	7	0	0
T20	0	32	0	0
T21	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1445833	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1445833	0	0
T1	1059	14	0	0
T2	14791	170	0	0
T3	3337	26	0	0
T4	16751	229	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	33	0	0
T17	11533	112	0	0
T18	155484	12733	0	0
T19	695	5	0	0
T20	0	29	0	0
T21	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3049947	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3049947	0	0
T1	1059	14	0	0
T2	14791	170	0	0
T3	3337	26	0	0
T4	16751	117	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	33	0	0
T17	11533	123	0	0
T18	155484	4228	0	0
T19	695	5	0	0
T20	0	29	0	0
T21	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1376170	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1376170	0	0
T1	1059	21	0	0
T2	14791	162	0	0
T3	3337	24	0	0
T4	16751	125	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	28	0	0
T17	11533	75	0	0
T18	155484	19076	0	0
T19	695	1	0	0
T20	0	32	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3159345	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3159345	0	0
T1	1059	21	0	0
T2	14791	162	0	0
T3	3337	24	0	0
T4	16751	52	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	28	0	0
T17	11533	72	0	0
T18	155484	5523	0	0
T19	695	1	0	0
T20	0	32	0	0
T21	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1422082	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1422082	0	0
T1	1059	13	0	0
T2	14791	411	0	0
T3	3337	33	0	0
T4	16751	93	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	47	0	0
T17	11533	95	0	0
T18	155484	25669	0	0
T19	695	6	0	0
T20	0	31	0	0
T21	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3012266	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3012266	0	0
T1	1059	13	0	0
T2	14791	411	0	0
T3	3337	33	0	0
T4	16751	57	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	47	0	0
T17	11533	92	0	0
T18	155484	8370	0	0
T19	695	6	0	0
T20	0	31	0	0
T21	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1383697	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1383697	0	0
T1	1059	9	0	0
T2	14791	199	0	0
T3	3337	28	0	0
T4	16751	186	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	57	0	0
T18	155484	17189	0	0
T19	695	10	0	0
T20	0	30	0	0
T21	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3231286	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3231286	0	0
T1	1059	9	0	0
T2	14791	199	0	0
T3	3337	28	0	0
T4	16751	106	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	40	0	0
T17	11533	39	0	0
T18	155484	8090	0	0
T19	695	10	0	0
T20	0	30	0	0
T21	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1413825	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1413825	0	0
T1	1059	13	0	0
T2	14791	167	0	0
T3	3337	32	0	0
T4	16751	126	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	46	0	0
T17	11533	123	0	0
T18	155484	16448	0	0
T19	695	10	0	0
T20	0	34	0	0
T21	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3992262	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3992262	0	0
T1	1059	13	0	0
T2	14791	167	0	0
T3	3337	32	0	0
T4	16751	73	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	46	0	0
T17	11533	115	0	0
T18	155484	7812	0	0
T19	695	10	0	0
T20	0	34	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1424575	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1424575	0	0
T1	1059	23	0	0
T2	14791	441	0	0
T3	3337	40	0	0
T4	16751	81	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	35	0	0
T17	11533	45	0	0
T18	155484	14775	0	0
T19	695	4	0	0
T20	0	27	0	0
T21	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3641384	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3641384	0	0
T1	1059	23	0	0
T2	14791	441	0	0
T3	3337	40	0	0
T4	16751	51	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	35	0	0
T17	11533	39	0	0
T18	155484	5779	0	0
T19	695	4	0	0
T20	0	27	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1436115	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1436115	0	0
T1	1059	19	0	0
T2	14791	169	0	0
T3	3337	35	0	0
T4	16751	106	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	39	0	0
T17	11533	24	0	0
T18	155484	22643	0	0
T19	695	8	0	0
T20	0	30	0	0
T21	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3123782	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3123782	0	0
T1	1059	19	0	0
T2	14791	169	0	0
T3	3337	35	0	0
T4	16751	75	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	39	0	0
T17	11533	66	0	0
T18	155484	8785	0	0
T19	695	8	0	0
T20	0	30	0	0
T21	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	1469025	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	1469025	0	0
T1	1059	19	0	0
T2	14791	447	0	0
T3	3337	34	0	0
T4	16751	166	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	44	0	0
T17	11533	79	0	0
T18	155484	16438	0	0
T19	695	9	0	0
T20	0	39	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306080334	3022436	0	0
DepthKnown_A	306080334	305951666	0	0
RvalidKnown_A	306080334	305951666	0	0
WreadyKnown_A	306080334	305951666	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	3022436	0	0
T1	1059	19	0	0
T2	14791	447	0	0
T3	3337	34	0	0
T4	16751	88	0	0
T5	170047	0	0	0
T15	778	0	0	0
T16	4488	44	0	0
T17	11533	94	0	0
T18	155484	6408	0	0
T19	695	9	0	0
T20	0	39	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306080334	305951666	0	0
T1	1059	1045	0	0
T2	14791	14736	0	0
T3	3337	3309	0	0
T4	16751	16676	0	0
T5	170047	170040	0	0
T15	778	731	0	0
T16	4488	4412	0	0
T17	11533	11120	0	0
T18	155484	155479	0	0
T19	695	638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0