Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1566975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247085

1

T1

146

T2

929

T3

343

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613526	1			T1	388		T2	2209		T3	875
values[0x0]	586137	1			T1	360		T2	2248		T3	839
values[0x1]	614397	1			T1	379		T2	2283		T3	802

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214375	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599685

1

T1

364

T2

2238

T3

848

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7059	1			T1	9		T2	120		T3	11
valid_sources[0x01]	7120	1			T1	2		T2	22		T3	7
valid_sources[0x02]	6771	1			T1	7		T2	13		T3	19
valid_sources[0x03]	7235	1			T1	8		T2	13		T3	12
valid_sources[0x04]	6430	1			T1	2		T2	15		T3	2
valid_sources[0x05]	6355	1			T2	7		T3	24		T4	7
valid_sources[0x06]	7129	1			T1	9		T2	2		T3	14
valid_sources[0x07]	7423	1			T2	8		T3	14		T4	23
valid_sources[0x08]	7298	1			T1	2		T2	12		T3	3
valid_sources[0x09]	7148	1			T1	19		T2	9		T3	10
valid_sources[0x0a]	7309	1			T1	7		T2	109		T3	7
valid_sources[0x0b]	6957	1			T2	15		T3	6		T4	27
valid_sources[0x0c]	7609	1			T2	52		T4	25		T12	19
valid_sources[0x0d]	6739	1			T1	2		T2	6		T3	12
valid_sources[0x0e]	8524	1			T1	6		T2	13		T3	10
valid_sources[0x0f]	6584	1			T2	5		T3	10		T4	5
valid_sources[0x10]	7664	1			T1	6		T2	34		T4	8
valid_sources[0x11]	8363	1			T1	1		T2	8		T3	33
valid_sources[0x12]	6279	1			T1	11		T2	55		T3	3
valid_sources[0x13]	7096	1			T1	2		T2	19		T3	17
valid_sources[0x14]	8329	1			T1	6		T2	21		T3	13
valid_sources[0x15]	7168	1			T1	1		T2	10		T3	28
valid_sources[0x16]	6863	1			T1	17		T2	24		T3	14
valid_sources[0x17]	6725	1			T1	8		T2	34		T4	13
valid_sources[0x18]	6558	1			T1	2		T2	24		T3	11
valid_sources[0x19]	6765	1			T2	7		T3	22		T4	7
valid_sources[0x1a]	7042	1			T1	7		T2	26		T3	3
valid_sources[0x1b]	6490	1			T1	11		T2	112		T4	10
valid_sources[0x1c]	6967	1			T1	1		T2	9		T3	4
valid_sources[0x1d]	6418	1			T1	6		T2	22		T3	6
valid_sources[0x1e]	7171	1			T1	2		T2	14		T3	11
valid_sources[0x1f]	7030	1			T1	6		T2	15		T3	23
valid_sources[0x20]	7117	1			T1	7		T3	14		T4	6
valid_sources[0x21]	6222	1			T1	17		T2	32		T3	2
valid_sources[0x22]	6828	1			T1	1		T2	13		T3	9
valid_sources[0x23]	7343	1			T1	2		T2	14		T3	10
valid_sources[0x24]	7045	1			T2	12		T4	23		T12	17
valid_sources[0x25]	7320	1			T1	5		T2	25		T3	12
valid_sources[0x26]	6969	1			T2	10		T3	1		T4	15
valid_sources[0x27]	6677	1			T2	49		T4	3		T12	8
valid_sources[0x28]	7593	1			T1	18		T2	31		T3	3
valid_sources[0x29]	6810	1			T1	1		T2	36		T3	14
valid_sources[0x2a]	7282	1			T1	8		T2	31		T3	6
valid_sources[0x2b]	6513	1			T1	3		T2	7		T3	6
valid_sources[0x2c]	7600	1			T2	4		T3	4		T4	16
valid_sources[0x2d]	7344	1			T1	3		T2	20		T4	16
valid_sources[0x2e]	6727	1			T1	2		T2	28		T3	11
valid_sources[0x2f]	7285	1			T1	5		T2	11		T4	10
valid_sources[0x30]	8044	1			T1	1		T2	54		T3	4
valid_sources[0x31]	6738	1			T1	12		T2	8		T3	2
valid_sources[0x32]	7688	1			T1	3		T2	13		T3	3
valid_sources[0x33]	7740	1			T1	1		T2	12		T3	4
valid_sources[0x34]	6964	1			T1	3		T2	19		T3	2
valid_sources[0x35]	6869	1			T1	7		T2	17		T4	10
valid_sources[0x36]	6483	1			T1	4		T2	36		T3	12
valid_sources[0x37]	7064	1			T1	11		T2	14		T3	11
valid_sources[0x38]	6824	1			T2	16		T3	1		T4	16
valid_sources[0x39]	7557	1			T2	21		T3	10		T4	14
valid_sources[0x3a]	6509	1			T2	22		T3	4		T4	13
valid_sources[0x3b]	6777	1			T2	7		T3	19		T4	14
valid_sources[0x3c]	7219	1			T1	3		T2	12		T3	20
valid_sources[0x3d]	7014	1			T1	10		T3	17		T4	16
valid_sources[0x3e]	6684	1			T2	63		T3	4		T4	26
valid_sources[0x3f]	6599	1			T1	6		T2	10		T3	23
valid_sources[0x40]	7729	1			T2	15		T3	25		T4	5
valid_sources[0x41]	6698	1			T2	26		T3	5		T4	25
valid_sources[0x42]	7733	1			T1	18		T2	10		T3	36
valid_sources[0x43]	7085	1			T2	91		T3	6		T4	5
valid_sources[0x44]	7325	1			T1	5		T2	3		T3	3
valid_sources[0x45]	7274	1			T1	5		T2	9		T3	2
valid_sources[0x46]	7332	1			T1	2		T2	10		T3	15
valid_sources[0x47]	6625	1			T1	9		T2	3		T3	8
valid_sources[0x48]	6803	1			T1	4		T2	9		T3	13
valid_sources[0x49]	7017	1			T1	10		T2	18		T3	3
valid_sources[0x4a]	7053	1			T1	3		T2	1		T3	6
valid_sources[0x4b]	7430	1			T2	5		T3	6		T4	14
valid_sources[0x4c]	7522	1			T1	4		T2	20		T3	8
valid_sources[0x4d]	9046	1			T1	7		T2	30		T3	1
valid_sources[0x4e]	6655	1			T2	18		T3	14		T4	10
valid_sources[0x4f]	7135	1			T1	5		T2	46		T3	30
valid_sources[0x50]	6747	1			T2	20		T3	22		T4	4
valid_sources[0x51]	7046	1			T2	49		T3	9		T4	7
valid_sources[0x52]	6805	1			T3	9		T4	17		T12	16
valid_sources[0x53]	7207	1			T1	3		T2	16		T3	8
valid_sources[0x54]	6461	1			T1	7		T2	29		T3	14
valid_sources[0x55]	6341	1			T1	3		T2	17		T3	9
valid_sources[0x56]	7610	1			T1	5		T2	64		T3	8
valid_sources[0x57]	6678	1			T1	7		T2	11		T3	7
valid_sources[0x58]	6757	1			T1	3		T2	79		T4	10
valid_sources[0x59]	6955	1			T1	1		T2	35		T3	15
valid_sources[0x5a]	6239	1			T1	6		T2	19		T3	11
valid_sources[0x5b]	6474	1			T2	28		T3	15		T4	9
valid_sources[0x5c]	7328	1			T1	4		T2	52		T3	16
valid_sources[0x5d]	7058	1			T2	19		T3	22		T4	16
valid_sources[0x5e]	7150	1			T1	1		T2	43		T3	4
valid_sources[0x5f]	6501	1			T1	10		T2	5		T3	16
valid_sources[0x60]	6965	1			T1	1		T2	41		T3	15
valid_sources[0x61]	6669	1			T2	9		T3	9		T4	25
valid_sources[0x62]	7099	1			T1	3		T2	26		T3	2
valid_sources[0x63]	7351	1			T2	7		T3	21		T4	30
valid_sources[0x64]	6493	1			T1	5		T2	7		T3	4
valid_sources[0x65]	6996	1			T1	2		T2	126		T3	11
valid_sources[0x66]	7391	1			T1	1		T2	33		T3	6
valid_sources[0x67]	6530	1			T2	18		T3	7		T4	5
valid_sources[0x68]	8048	1			T1	1		T2	40		T3	12
valid_sources[0x69]	6613	1			T1	6		T2	10		T3	3
valid_sources[0x6a]	6771	1			T1	8		T2	5		T3	8
valid_sources[0x6b]	7309	1			T2	65		T3	5		T4	12
valid_sources[0x6c]	6768	1			T1	6		T2	19		T3	7
valid_sources[0x6d]	6673	1			T2	26		T3	1		T4	15
valid_sources[0x6e]	6965	1			T1	12		T2	27		T3	22
valid_sources[0x6f]	6917	1			T2	19		T3	8		T4	32
valid_sources[0x70]	6712	1			T1	5		T2	54		T3	4
valid_sources[0x71]	8255	1			T1	4		T2	150		T3	16
valid_sources[0x72]	6603	1			T1	5		T2	3		T3	6
valid_sources[0x73]	6762	1			T2	68		T3	15		T4	25
valid_sources[0x74]	7462	1			T1	4		T2	30		T3	24
valid_sources[0x75]	6408	1			T1	8		T2	21		T3	2
valid_sources[0x76]	6792	1			T1	3		T2	16		T3	10
valid_sources[0x77]	8297	1			T1	13		T2	24		T3	15
valid_sources[0x78]	6853	1			T1	10		T2	21		T3	22
valid_sources[0x79]	6641	1			T2	22		T4	26		T12	19
valid_sources[0x7a]	7429	1			T2	15		T3	15		T4	8
valid_sources[0x7b]	6593	1			T2	38		T3	17		T4	21
valid_sources[0x7c]	7368	1			T1	10		T2	96		T4	9
valid_sources[0x7d]	7369	1			T2	12		T3	32		T4	8
valid_sources[0x7e]	7065	1			T1	1		T2	2		T4	11
valid_sources[0x7f]	7334	1			T1	5		T2	11		T3	4
valid_sources[0x80]	7862	1			T2	6		T3	21		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26196

1

T1

12

T2

93

T3

38

values[0x0]

all_enables

biggest_size

194968

1

T1

113

T2

767

T3

286

values[0x1]

all_enables

biggest_size

25921

1

T1

21

T2

69

T3

19