Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	351873865	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351873865	0	0
T1	8717688	1895635	0	0
T2	8369928	220805	0	0
T3	283528	9994	0	0
T4	4670904	133040	0	0
T12	3744664	69571	0	0
T13	33339320	721627	0	0
T15	3193624	73397	0	0
T16	6578376	113891	0	0
T17	124096	5073	0	0
T18	250824	8664	0	0
T19	0	14407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8717688	8717408	0	0
T2	8369928	8363936	0	0
T3	283528	282856	0	0
T4	4670904	4667376	0	0
T12	3744664	3743936	0	0
T13	33339320	33322576	0	0
T15	3193624	3188864	0	0
T16	6578376	6577032	0	0
T17	124096	122136	0	0
T18	250824	249872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8717688	8717408	0	0
T2	8369928	8363936	0	0
T3	283528	282856	0	0
T4	4670904	4667376	0	0
T12	3744664	3743936	0	0
T13	33339320	33322576	0	0
T15	3193624	3188864	0	0
T16	6578376	6577032	0	0
T17	124096	122136	0	0
T18	250824	249872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8717688	8717408	0	0
T2	8369928	8363936	0	0
T3	283528	282856	0	0
T4	4670904	4667376	0	0
T12	3744664	3743936	0	0
T13	33339320	33322576	0	0
T15	3193624	3188864	0	0
T16	6578376	6577032	0	0
T17	124096	122136	0	0
T18	250824	249872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	125740861	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	125740861	0	0
T1	155673	754511	0	0
T2	149463	73969	0	0
T3	5063	4942	0	0
T4	83409	32492	0	0
T12	66869	28772	0	0
T13	595345	268762	0	0
T15	57029	28234	0	0
T16	117471	47523	0	0
T17	2216	1978	0	0
T18	4479	2171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	93609236	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	93609236	0	0
T1	155673	374257	0	0
T2	149463	54421	0	0
T3	5063	2516	0	0
T4	83409	34028	0	0
T12	66869	18174	0	0
T13	595345	145651	0	0
T15	57029	24026	0	0
T16	117471	15835	0	0
T17	2216	1033	0	0
T18	4479	2171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1454547	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1454547	0	0
T1	155673	16900	0	0
T2	149463	753	0	0
T3	5063	46	0	0
T4	83409	0	0	0
T12	66869	483	0	0
T13	595345	3001	0	0
T15	57029	608	0	0
T16	117471	1051	0	0
T17	2216	43	0	0
T18	4479	82	0	0
T19	0	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3608545	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3608545	0	0
T1	155673	15916	0	0
T2	149463	735	0	0
T3	5063	46	0	0
T4	83409	0	0	0
T12	66869	374	0	0
T13	595345	2543	0	0
T15	57029	558	0	0
T16	117471	730	0	0
T17	2216	43	0	0
T18	4479	82	0	0
T19	0	528	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1515978	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1515978	0	0
T1	155673	13456	0	0
T2	149463	2580	0	0
T3	5063	35	0	0
T4	83409	0	0	0
T12	66869	485	0	0
T13	595345	5250	0	0
T15	57029	392	0	0
T16	117471	1014	0	0
T17	2216	41	0	0
T18	4479	72	0	0
T19	0	673	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3350207	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3350207	0	0
T1	155673	14058	0	0
T2	149463	2559	0	0
T3	5063	35	0	0
T4	83409	0	0	0
T12	66869	316	0	0
T13	595345	3972	0	0
T15	57029	406	0	0
T16	117471	750	0	0
T17	2216	41	0	0
T18	4479	72	0	0
T19	0	667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1517792	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1517792	0	0
T1	155673	16358	0	0
T2	149463	622	0	0
T3	5063	38	0	0
T4	83409	2083	0	0
T12	66869	487	0	0
T13	595345	5011	0	0
T15	57029	379	0	0
T16	117471	2274	0	0
T17	2216	36	0	0
T18	4479	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	4051594	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	4051594	0	0
T1	155673	15333	0	0
T2	149463	590	0	0
T3	5063	38	0	0
T4	83409	2176	0	0
T12	66869	478	0	0
T13	595345	4106	0	0
T15	57029	433	0	0
T16	117471	453	0	0
T17	2216	36	0	0
T18	4479	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1505223	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1505223	0	0
T1	155673	11863	0	0
T2	149463	794	0	0
T3	5063	40	0	0
T4	83409	0	0	0
T12	66869	590	0	0
T13	595345	3069	0	0
T15	57029	463	0	0
T16	117471	1425	0	0
T17	2216	36	0	0
T18	4479	69	0	0
T19	0	701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	4170682	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	4170682	0	0
T1	155673	13338	0	0
T2	149463	738	0	0
T3	5063	40	0	0
T4	83409	0	0	0
T12	66869	377	0	0
T13	595345	2617	0	0
T15	57029	405	0	0
T16	117471	355	0	0
T17	2216	36	0	0
T18	4479	69	0	0
T19	0	732	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1525853	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1525853	0	0
T1	155673	15035	0	0
T2	149463	693	0	0
T3	5063	50	0	0
T4	83409	1966	0	0
T12	66869	560	0	0
T13	595345	6787	0	0
T15	57029	312	0	0
T16	117471	49	0	0
T17	2216	40	0	0
T18	4479	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3340740	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3340740	0	0
T1	155673	13404	0	0
T2	149463	710	0	0
T3	5063	50	0	0
T4	83409	1852	0	0
T12	66869	375	0	0
T13	595345	5259	0	0
T15	57029	256	0	0
T16	117471	1	0	0
T17	2216	40	0	0
T18	4479	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1423447	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1423447	0	0
T1	155673	12107	0	0
T2	149463	2324	0	0
T3	5063	52	0	0
T4	83409	1904	0	0
T12	66869	496	0	0
T13	595345	6393	0	0
T15	57029	397	0	0
T16	117471	2758	0	0
T17	2216	38	0	0
T18	4479	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2961163	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2961163	0	0
T1	155673	11266	0	0
T2	149463	2426	0	0
T3	5063	52	0	0
T4	83409	1802	0	0
T12	66869	364	0	0
T13	595345	5458	0	0
T15	57029	440	0	0
T16	117471	1341	0	0
T17	2216	38	0	0
T18	4479	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1485178	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1485178	0	0
T1	155673	13618	0	0
T2	149463	533	0	0
T3	5063	45	0	0
T4	83409	0	0	0
T12	66869	406	0	0
T13	595345	7229	0	0
T15	57029	379	0	0
T16	117471	125	0	0
T17	2216	32	0	0
T18	4479	70	0	0
T19	0	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2902660	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2902660	0	0
T1	155673	13905	0	0
T2	149463	570	0	0
T3	5063	45	0	0
T4	83409	0	0	0
T12	66869	446	0	0
T13	595345	5760	0	0
T15	57029	385	0	0
T16	117471	24	0	0
T17	2216	32	0	0
T18	4479	70	0	0
T19	0	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1493443	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1493443	0	0
T1	155673	14967	0	0
T2	149463	860	0	0
T3	5063	53	0	0
T4	83409	1882	0	0
T12	66869	476	0	0
T13	595345	4561	0	0
T15	57029	325	0	0
T16	117471	409	0	0
T17	2216	44	0	0
T18	4479	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3015183	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3015183	0	0
T1	155673	12759	0	0
T2	149463	781	0	0
T3	5063	53	0	0
T4	83409	1988	0	0
T12	66869	327	0	0
T13	595345	3649	0	0
T15	57029	297	0	0
T16	117471	1631	0	0
T17	2216	44	0	0
T18	4479	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1490887	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1490887	0	0
T1	155673	17483	0	0
T2	149463	2930	0	0
T3	5063	59	0	0
T4	83409	1704	0	0
T12	66869	477	0	0
T13	595345	7467	0	0
T15	57029	361	0	0
T16	117471	269	0	0
T17	2216	40	0	0
T18	4479	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2786934	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2786934	0	0
T1	155673	14823	0	0
T2	149463	2892	0	0
T3	5063	59	0	0
T4	83409	2283	0	0
T12	66869	444	0	0
T13	595345	5374	0	0
T15	57029	334	0	0
T16	117471	714	0	0
T17	2216	40	0	0
T18	4479	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1456668	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1456668	0	0
T1	155673	12669	0	0
T2	149463	2978	0	0
T3	5063	42	0	0
T4	83409	1205	0	0
T12	66869	460	0	0
T13	595345	6533	0	0
T15	57029	430	0	0
T16	117471	1057	0	0
T17	2216	35	0	0
T18	4479	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	4292724	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	4292724	0	0
T1	155673	12312	0	0
T2	149463	2866	0	0
T3	5063	42	0	0
T4	83409	1561	0	0
T12	66869	414	0	0
T13	595345	5509	0	0
T15	57029	432	0	0
T16	117471	307	0	0
T17	2216	35	0	0
T18	4479	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1433790	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1433790	0	0
T1	155673	12223	0	0
T2	149463	739	0	0
T3	5063	54	0	0
T4	83409	0	0	0
T12	66869	621	0	0
T13	595345	5320	0	0
T15	57029	388	0	0
T16	117471	1492	0	0
T17	2216	33	0	0
T18	4479	87	0	0
T19	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2988255	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2988255	0	0
T1	155673	12337	0	0
T2	149463	754	0	0
T3	5063	54	0	0
T4	83409	0	0	0
T12	66869	550	0	0
T13	595345	4227	0	0
T15	57029	369	0	0
T16	117471	452	0	0
T17	2216	33	0	0
T18	4479	87	0	0
T19	0	390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1420431	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1420431	0	0
T1	155673	14368	0	0
T2	149463	730	0	0
T3	5063	55	0	0
T4	83409	0	0	0
T12	66869	480	0	0
T13	595345	5316	0	0
T15	57029	383	0	0
T16	117471	1693	0	0
T17	2216	39	0	0
T18	4479	77	0	0
T19	0	648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3041883	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3041883	0	0
T1	155673	14117	0	0
T2	149463	633	0	0
T3	5063	55	0	0
T4	83409	0	0	0
T12	66869	360	0	0
T13	595345	4223	0	0
T15	57029	309	0	0
T16	117471	1203	0	0
T17	2216	39	0	0
T18	4479	77	0	0
T19	0	571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1509250	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1509250	0	0
T1	155673	13113	0	0
T2	149463	6440	0	0
T3	5063	47	0	0
T4	83409	2411	0	0
T12	66869	406	0	0
T13	595345	7524	0	0
T15	57029	306	0	0
T16	117471	3204	0	0
T17	2216	33	0	0
T18	4479	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3502223	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3502223	0	0
T1	155673	13684	0	0
T2	149463	6230	0	0
T3	5063	47	0	0
T4	83409	2436	0	0
T12	66869	398	0	0
T13	595345	5676	0	0
T15	57029	364	0	0
T16	117471	457	0	0
T17	2216	33	0	0
T18	4479	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1470815	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1470815	0	0
T1	155673	13836	0	0
T2	149463	827	0	0
T3	5063	40	0	0
T4	83409	0	0	0
T12	66869	504	0	0
T13	595345	6394	0	0
T15	57029	371	0	0
T16	117471	1482	0	0
T17	2216	42	0	0
T18	4479	82	0	0
T19	0	615	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3068345	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3068345	0	0
T1	155673	12582	0	0
T2	149463	756	0	0
T3	5063	40	0	0
T4	83409	0	0	0
T12	66869	423	0	0
T13	595345	5057	0	0
T15	57029	392	0	0
T16	117471	751	0	0
T17	2216	42	0	0
T18	4479	82	0	0
T19	0	604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1473699	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1473699	0	0
T1	155673	16579	0	0
T2	149463	4972	0	0
T3	5063	37	0	0
T4	83409	4408	0	0
T12	66869	401	0	0
T13	595345	2944	0	0
T15	57029	280	0	0
T16	117471	398	0	0
T17	2216	36	0	0
T18	4479	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3489593	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3489593	0	0
T1	155673	11638	0	0
T2	149463	4868	0	0
T3	5063	37	0	0
T4	83409	4420	0	0
T12	66869	368	0	0
T13	595345	2554	0	0
T15	57029	308	0	0
T16	117471	81	0	0
T17	2216	36	0	0
T18	4479	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1454300	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1454300	0	0
T1	155673	14827	0	0
T2	149463	2388	0	0
T3	5063	44	0	0
T4	83409	0	0	0
T12	66869	498	0	0
T13	595345	7297	0	0
T15	57029	334	0	0
T16	117471	345	0	0
T17	2216	37	0	0
T18	4479	103	0	0
T19	0	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3552896	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3552896	0	0
T1	155673	16266	0	0
T2	149463	2409	0	0
T3	5063	44	0	0
T4	83409	0	0	0
T12	66869	431	0	0
T13	595345	5869	0	0
T15	57029	355	0	0
T16	117471	179	0	0
T17	2216	37	0	0
T18	4479	103	0	0
T19	0	464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1468766	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1468766	0	0
T1	155673	19921	0	0
T2	149463	737	0	0
T3	5063	55	0	0
T4	83409	1645	0	0
T12	66869	408	0	0
T13	595345	11598	0	0
T15	57029	546	0	0
T16	117471	1079	0	0
T17	2216	33	0	0
T18	4479	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2973708	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2973708	0	0
T1	155673	15199	0	0
T2	149463	794	0	0
T3	5063	55	0	0
T4	83409	1827	0	0
T12	66869	287	0	0
T13	595345	9257	0	0
T15	57029	563	0	0
T16	117471	740	0	0
T17	2216	33	0	0
T18	4479	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1494695	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1494695	0	0
T1	155673	17420	0	0
T2	149463	2019	0	0
T3	5063	51	0	0
T4	83409	3628	0	0
T12	66869	452	0	0
T13	595345	2829	0	0
T15	57029	477	0	0
T16	117471	3118	0	0
T17	2216	38	0	0
T18	4479	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	4061426	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	4061426	0	0
T1	155673	17358	0	0
T2	149463	2383	0	0
T3	5063	51	0	0
T4	83409	3712	0	0
T12	66869	365	0	0
T13	595345	2353	0	0
T15	57029	412	0	0
T16	117471	1215	0	0
T17	2216	38	0	0
T18	4479	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1492424	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1492424	0	0
T1	155673	20964	0	0
T2	149463	2940	0	0
T3	5063	38	0	0
T4	83409	1720	0	0
T12	66869	414	0	0
T13	595345	5084	0	0
T15	57029	399	0	0
T16	117471	781	0	0
T17	2216	42	0	0
T18	4479	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3697587	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3697587	0	0
T1	155673	19019	0	0
T2	149463	2896	0	0
T3	5063	38	0	0
T4	83409	1623	0	0
T12	66869	403	0	0
T13	595345	3944	0	0
T15	57029	429	0	0
T16	117471	149	0	0
T17	2216	42	0	0
T18	4479	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1522769	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1522769	0	0
T1	155673	15320	0	0
T2	149463	670	0	0
T3	5063	62	0	0
T4	83409	0	0	0
T12	66869	444	0	0
T13	595345	7238	0	0
T15	57029	351	0	0
T16	117471	1595	0	0
T17	2216	41	0	0
T18	4479	74	0	0
T19	0	380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3448927	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3448927	0	0
T1	155673	17297	0	0
T2	149463	728	0	0
T3	5063	62	0	0
T4	83409	0	0	0
T12	66869	357	0	0
T13	595345	5531	0	0
T15	57029	420	0	0
T16	117471	777	0	0
T17	2216	41	0	0
T18	4479	74	0	0
T19	0	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1439744	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1439744	0	0
T1	155673	14906	0	0
T2	149463	2627	0	0
T3	5063	57	0	0
T4	83409	0	0	0
T12	66869	341	0	0
T13	595345	7343	0	0
T15	57029	436	0	0
T16	117471	480	0	0
T17	2216	28	0	0
T18	4479	85	0	0
T19	0	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3593137	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3593137	0	0
T1	155673	13567	0	0
T2	149463	2516	0	0
T3	5063	57	0	0
T4	83409	0	0	0
T12	66869	321	0	0
T13	595345	5439	0	0
T15	57029	328	0	0
T16	117471	174	0	0
T17	2216	28	0	0
T18	4479	85	0	0
T19	0	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1462886	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1462886	0	0
T1	155673	13770	0	0
T2	149463	766	0	0
T3	5063	52	0	0
T4	83409	1938	0	0
T12	66869	470	0	0
T13	595345	9959	0	0
T15	57029	412	0	0
T16	117471	2182	0	0
T17	2216	46	0	0
T18	4479	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3365670	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3365670	0	0
T1	155673	12432	0	0
T2	149463	819	0	0
T3	5063	52	0	0
T4	83409	2134	0	0
T12	66869	415	0	0
T13	595345	8342	0	0
T15	57029	407	0	0
T16	117471	744	0	0
T17	2216	46	0	0
T18	4479	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1506461	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1506461	0	0
T1	155673	12928	0	0
T2	149463	2380	0	0
T3	5063	38	0	0
T4	83409	0	0	0
T12	66869	398	0	0
T13	595345	9895	0	0
T15	57029	287	0	0
T16	117471	390	0	0
T17	2216	45	0	0
T18	4479	93	0	0
T19	0	514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3417943	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3417943	0	0
T1	155673	13348	0	0
T2	149463	2882	0	0
T3	5063	38	0	0
T4	83409	0	0	0
T12	66869	320	0	0
T13	595345	7360	0	0
T15	57029	280	0	0
T16	117471	154	0	0
T17	2216	45	0	0
T18	4479	93	0	0
T19	0	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1470857	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1470857	0	0
T1	155673	7379	0	0
T2	149463	715	0	0
T3	5063	39	0	0
T4	83409	0	0	0
T12	66869	443	0	0
T13	595345	5779	0	0
T15	57029	492	0	0
T16	117471	229	0	0
T17	2216	37	0	0
T18	4479	59	0	0
T19	0	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3407047	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3407047	0	0
T1	155673	8685	0	0
T2	149463	767	0	0
T3	5063	39	0	0
T4	83409	0	0	0
T12	66869	381	0	0
T13	595345	4187	0	0
T15	57029	449	0	0
T16	117471	84	0	0
T17	2216	37	0	0
T18	4479	59	0	0
T19	0	510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1455971	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1455971	0	0
T1	155673	11992	0	0
T2	149463	690	0	0
T3	5063	41	0	0
T4	83409	4153	0	0
T12	66869	369	0	0
T13	595345	7354	0	0
T15	57029	319	0	0
T16	117471	1788	0	0
T17	2216	37	0	0
T18	4479	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	4054867	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	4054867	0	0
T1	155673	10713	0	0
T2	149463	633	0	0
T3	5063	41	0	0
T4	83409	4266	0	0
T12	66869	277	0	0
T13	595345	5690	0	0
T15	57029	353	0	0
T16	117471	280	0	0
T17	2216	37	0	0
T18	4479	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1446497	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1446497	0	0
T1	155673	14236	0	0
T2	149463	655	0	0
T3	5063	45	0	0
T4	83409	0	0	0
T12	66869	428	0	0
T13	595345	5883	0	0
T15	57029	368	0	0
T16	117471	1566	0	0
T17	2216	37	0	0
T18	4479	73	0	0
T19	0	668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	3879377	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	3879377	0	0
T1	155673	12488	0	0
T2	149463	611	0	0
T3	5063	45	0	0
T4	83409	0	0	0
T12	66869	296	0	0
T13	595345	5085	0	0
T15	57029	395	0	0
T16	117471	992	0	0
T17	2216	37	0	0
T18	4479	73	0	0
T19	0	766	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	1445758	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	1445758	0	0
T1	155673	14372	0	0
T2	149463	725	0	0
T3	5063	53	0	0
T4	83409	1845	0	0
T12	66869	414	0	0
T13	595345	8332	0	0
T15	57029	402	0	0
T16	117471	2445	0	0
T17	2216	42	0	0
T18	4479	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318956540	2662323	0	0
DepthKnown_A	318956540	318831796	0	0
RvalidKnown_A	318956540	318831796	0	0
WreadyKnown_A	318956540	318831796	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	2662323	0	0
T1	155673	16413	0	0
T2	149463	782	0	0
T3	5063	53	0	0
T4	83409	1948	0	0
T12	66869	347	0	0
T13	595345	6783	0	0
T15	57029	461	0	0
T16	117471	1097	0	0
T17	2216	42	0	0
T18	4479	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318956540	318831796	0	0
T1	155673	155668	0	0
T2	149463	149356	0	0
T3	5063	5051	0	0
T4	83409	83346	0	0
T12	66869	66856	0	0
T13	595345	595046	0	0
T15	57029	56944	0	0
T16	117471	117447	0	0
T17	2216	2181	0	0
T18	4479	4462	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0