Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1618493	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254647

1

T1

57

T2

75

T3

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	633342	1			T1	248		T2	135		T3	199
values[0x0]	605366	1			T1	53		T2	145		T3	188
values[0x1]	634432	1			T1	280		T2	150		T3	229

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619450

1

T1

224

T2

162

T3

206

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6821	1			T2	4		T16	2		T17	8
valid_sources[0x01]	7105	1			T3	18		T17	11		T19	2
valid_sources[0x02]	7925	1			T1	44		T2	3		T16	3
valid_sources[0x03]	7096	1			T1	1		T16	2		T17	6
valid_sources[0x04]	8502	1			T1	2		T17	11		T18	3
valid_sources[0x05]	8983	1			T1	9		T2	1		T16	3
valid_sources[0x06]	7185	1			T16	1		T17	10		T19	2
valid_sources[0x07]	8025	1			T4	151		T17	16		T20	12
valid_sources[0x08]	7583	1			T1	8		T2	1		T16	1
valid_sources[0x09]	7954	1			T1	1		T16	1		T17	4
valid_sources[0x0a]	9254	1			T1	1		T2	4		T3	6
valid_sources[0x0b]	7901	1			T1	1		T4	26		T16	2
valid_sources[0x0c]	7151	1			T1	2		T2	3		T17	6
valid_sources[0x0d]	7091	1			T1	1		T16	3		T17	9
valid_sources[0x0e]	7268	1			T1	17		T17	22		T13	10
valid_sources[0x0f]	6783	1			T1	1		T2	11		T3	15
valid_sources[0x10]	6614	1			T2	6		T17	6		T15	33
valid_sources[0x11]	6867	1			T2	1		T4	52		T16	1
valid_sources[0x12]	8210	1			T1	8		T16	2		T17	1
valid_sources[0x13]	7652	1			T2	5		T4	12		T16	1
valid_sources[0x14]	7047	1			T2	6		T16	3		T17	5
valid_sources[0x15]	6810	1			T3	10		T17	4		T19	5
valid_sources[0x16]	8136	1			T1	9		T2	6		T4	16
valid_sources[0x17]	7039	1			T1	3		T16	2		T17	5
valid_sources[0x18]	6945	1			T1	20		T4	3		T16	1
valid_sources[0x19]	7691	1			T3	17		T17	1		T20	18
valid_sources[0x1a]	7600	1			T1	2		T2	8		T16	3
valid_sources[0x1b]	7314	1			T1	1		T19	2		T20	20
valid_sources[0x1c]	7375	1			T1	2		T2	1		T4	74
valid_sources[0x1d]	7481	1			T2	5		T17	5		T18	7
valid_sources[0x1e]	7089	1			T19	2		T20	10		T15	40
valid_sources[0x1f]	7140	1			T1	1		T2	9		T16	3
valid_sources[0x20]	6873	1			T1	2		T16	2		T17	2
valid_sources[0x21]	7533	1			T2	2		T16	1		T17	10
valid_sources[0x22]	8072	1			T17	2		T20	4		T15	22
valid_sources[0x23]	7094	1			T1	4		T16	1		T17	8
valid_sources[0x24]	7954	1			T2	1		T17	6		T15	33
valid_sources[0x25]	6900	1			T1	1		T16	4		T17	5
valid_sources[0x26]	8154	1			T18	3		T15	24		T22	17
valid_sources[0x27]	7089	1			T1	1		T2	1		T4	66
valid_sources[0x28]	7010	1			T16	1		T17	1		T15	65
valid_sources[0x29]	7872	1			T1	1		T2	6		T17	4
valid_sources[0x2a]	7627	1			T1	11		T2	2		T4	11
valid_sources[0x2b]	7217	1			T1	18		T16	2		T17	8
valid_sources[0x2c]	7038	1			T1	5		T2	3		T16	2
valid_sources[0x2d]	7122	1			T1	3		T2	4		T16	3
valid_sources[0x2e]	7179	1			T1	1		T3	14		T16	2
valid_sources[0x2f]	7931	1			T16	5		T17	4		T18	7
valid_sources[0x30]	6844	1			T16	1		T17	6		T19	2
valid_sources[0x31]	6781	1			T1	2		T16	1		T17	3
valid_sources[0x32]	7068	1			T1	8		T17	2		T15	41
valid_sources[0x33]	7496	1			T1	3		T2	3		T17	3
valid_sources[0x34]	6938	1			T1	2		T2	3		T17	2
valid_sources[0x35]	7237	1			T2	3		T16	1		T17	4
valid_sources[0x36]	6916	1			T2	2		T16	2		T20	35
valid_sources[0x37]	6964	1			T1	3		T16	1		T17	1
valid_sources[0x38]	7665	1			T16	3		T17	9		T15	25
valid_sources[0x39]	7314	1			T16	3		T17	11		T20	20
valid_sources[0x3a]	6983	1			T1	2		T2	4		T17	8
valid_sources[0x3b]	7239	1			T1	3		T2	1		T16	3
valid_sources[0x3c]	7334	1			T1	2		T2	2		T16	1
valid_sources[0x3d]	6732	1			T2	1		T17	1		T15	16
valid_sources[0x3e]	6625	1			T17	6		T15	17		T22	21
valid_sources[0x3f]	7721	1			T2	3		T16	1		T17	13
valid_sources[0x40]	7129	1			T1	2		T16	1		T17	6
valid_sources[0x41]	6999	1			T2	10		T3	14		T16	1
valid_sources[0x42]	7787	1			T1	2		T3	11		T4	6
valid_sources[0x43]	6960	1			T2	1		T15	38		T22	27
valid_sources[0x44]	7954	1			T3	15		T4	59		T16	1
valid_sources[0x45]	7277	1			T1	3		T16	1		T17	15
valid_sources[0x46]	7638	1			T2	2		T17	10		T19	2
valid_sources[0x47]	7139	1			T17	6		T15	31		T22	17
valid_sources[0x48]	7455	1			T2	15		T4	34		T16	1
valid_sources[0x49]	7195	1			T2	4		T16	2		T17	11
valid_sources[0x4a]	6626	1			T4	57		T16	1		T17	6
valid_sources[0x4b]	6805	1			T2	6		T16	1		T17	5
valid_sources[0x4c]	7602	1			T1	1		T2	6		T3	10
valid_sources[0x4d]	7036	1			T2	7		T16	2		T17	11
valid_sources[0x4e]	7535	1			T1	4		T2	4		T17	3
valid_sources[0x4f]	7185	1			T1	8		T2	8		T16	4
valid_sources[0x50]	7669	1			T1	2		T16	1		T17	3
valid_sources[0x51]	7035	1			T1	2		T16	1		T17	12
valid_sources[0x52]	7003	1			T1	4		T2	1		T16	2
valid_sources[0x53]	7557	1			T1	4		T17	1		T20	15
valid_sources[0x54]	7133	1			T1	5		T16	3		T17	7
valid_sources[0x55]	6457	1			T2	6		T16	3		T17	8
valid_sources[0x56]	7186	1			T17	6		T19	1		T15	27
valid_sources[0x57]	7125	1			T3	15		T16	4		T17	10
valid_sources[0x58]	7775	1			T16	5		T15	24		T22	15
valid_sources[0x59]	8638	1			T17	7		T15	27		T21	3
valid_sources[0x5a]	7708	1			T1	3		T2	6		T4	20
valid_sources[0x5b]	6694	1			T1	2		T2	2		T16	1
valid_sources[0x5c]	6990	1			T16	5		T17	14		T20	17
valid_sources[0x5d]	8081	1			T2	2		T4	121		T16	2
valid_sources[0x5e]	7667	1			T1	3		T16	5		T17	12
valid_sources[0x5f]	7453	1			T18	8		T19	1		T20	20
valid_sources[0x60]	7234	1			T2	1		T16	2		T17	15
valid_sources[0x61]	7211	1			T16	6		T17	5		T15	20
valid_sources[0x62]	7840	1			T2	2		T16	3		T19	1
valid_sources[0x63]	7074	1			T16	1		T17	2		T20	16
valid_sources[0x64]	7687	1			T16	1		T20	29		T15	29
valid_sources[0x65]	6863	1			T1	10		T16	3		T17	20
valid_sources[0x66]	6784	1			T16	2		T17	10		T20	19
valid_sources[0x67]	7073	1			T1	2		T3	11		T16	2
valid_sources[0x68]	8020	1			T2	4		T16	3		T17	5
valid_sources[0x69]	7427	1			T1	15		T16	2		T18	6
valid_sources[0x6a]	7632	1			T2	8		T4	2		T16	3
valid_sources[0x6b]	6702	1			T2	1		T16	3		T19	1
valid_sources[0x6c]	7174	1			T2	5		T4	43		T16	2
valid_sources[0x6d]	8006	1			T17	2		T20	16		T15	20
valid_sources[0x6e]	6761	1			T2	5		T4	13		T16	3
valid_sources[0x6f]	7385	1			T1	3		T17	2		T15	15
valid_sources[0x70]	6872	1			T3	13		T16	4		T17	4
valid_sources[0x71]	7017	1			T16	2		T17	2		T13	12
valid_sources[0x72]	7274	1			T4	83		T16	1		T17	7
valid_sources[0x73]	7155	1			T17	4		T18	1		T15	20
valid_sources[0x74]	7581	1			T2	3		T16	3		T17	14
valid_sources[0x75]	7232	1			T1	1		T3	11		T17	8
valid_sources[0x76]	7721	1			T16	4		T17	3		T18	1
valid_sources[0x77]	7414	1			T16	1		T19	1		T15	26
valid_sources[0x78]	6820	1			T16	1		T17	10		T18	1
valid_sources[0x79]	7107	1			T1	1		T16	2		T17	3
valid_sources[0x7a]	8096	1			T1	3		T17	2		T19	2
valid_sources[0x7b]	7074	1			T1	1		T2	8		T16	3
valid_sources[0x7c]	7000	1			T2	2		T3	39		T16	1
valid_sources[0x7d]	7220	1			T1	4		T16	3		T17	1
valid_sources[0x7e]	6428	1			T1	1		T16	3		T17	3
valid_sources[0x7f]	6822	1			T1	23		T3	9		T16	6
valid_sources[0x80]	7113	1			T16	3		T17	21		T20	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26980

1

T1

18

T2

6

T3

10

values[0x0]

all_enables

biggest_size

200865

1

T1

20

T2

60

T3

63

values[0x1]

all_enables

biggest_size

26802

1

T1

19

T2

9

T3

13