Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	338433571	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338433571	0	0
T1	1471120	57174	0	0
T2	24416336	453587	0	0
T3	1370656	19252	0	0
T4	1540840	24002	0	0
T13	4333056	76929	0	0
T16	75376	2083	0	0
T17	10429160	1791343	0	0
T18	271600	6261	0	0
T19	22120	732	0	0
T20	4226880	63296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1471120	1426376	0	0
T2	24416336	24414992	0	0
T3	1370656	1367856	0	0
T4	1540840	1540000	0	0
T13	4333056	4330704	0	0
T16	75376	70672	0	0
T17	10429160	10428880	0	0
T18	271600	271208	0	0
T19	22120	21168	0	0
T20	4226880	4222064	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1471120	1426376	0	0
T2	24416336	24414992	0	0
T3	1370656	1367856	0	0
T4	1540840	1540000	0	0
T13	4333056	4330704	0	0
T16	75376	70672	0	0
T17	10429160	10428880	0	0
T18	271600	271208	0	0
T19	22120	21168	0	0
T20	4226880	4222064	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1471120	1426376	0	0
T2	24416336	24414992	0	0
T3	1370656	1367856	0	0
T4	1540840	1540000	0	0
T13	4333056	4330704	0	0
T16	75376	70672	0	0
T17	10429160	10428880	0	0
T18	271600	271208	0	0
T19	22120	21168	0	0
T20	4226880	4222064	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	123939418	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	123939418	0	0
T1	26270	21367	0	0
T2	436006	203807	0	0
T3	24476	4876	0	0
T4	27515	10895	0	0
T13	77376	75091	0	0
T16	1346	814	0	0
T17	186235	799246	0	0
T18	4850	2444	0	0
T19	395	282	0	0
T20	75480	15373	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	88117035	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	88117035	0	0
T1	26270	12642	0	0
T2	436006	55526	0	0
T3	24476	4751	0	0
T4	27515	3690	0	0
T13	77376	529	0	0
T16	1346	423	0	0
T17	186235	215880	0	0
T18	4850	1334	0	0
T19	395	150	0	0
T20	75480	16278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1462837	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1462837	0	0
T1	26270	381	0	0
T2	436006	4146	0	0
T3	24476	164	0	0
T4	27515	240	0	0
T13	77376	34	0	0
T16	1346	23	0	0
T17	186235	18512	0	0
T18	4850	38	0	0
T19	395	5	0	0
T20	75480	587	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2925290	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2925290	0	0
T1	26270	381	0	0
T2	436006	1956	0	0
T3	24476	133	0	0
T4	27515	74	0	0
T13	77376	7	0	0
T16	1346	23	0	0
T17	186235	5244	0	0
T18	4850	35	0	0
T19	395	5	0	0
T20	75480	549	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1474172	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1474172	0	0
T1	26270	425	0	0
T2	436006	2538	0	0
T3	24476	255	0	0
T4	27515	106	0	0
T13	77376	48	0	0
T16	1346	18	0	0
T17	186235	16226	0	0
T18	4850	37	0	0
T19	395	8	0	0
T20	75480	437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3167711	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3167711	0	0
T1	26270	425	0	0
T2	436006	893	0	0
T3	24476	254	0	0
T4	27515	74	0	0
T13	77376	13	0	0
T16	1346	18	0	0
T17	186235	4909	0	0
T18	4850	47	0	0
T19	395	8	0	0
T20	75480	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1497496	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1497496	0	0
T1	26270	369	0	0
T2	436006	3197	0	0
T3	24476	176	0	0
T4	27515	304	0	0
T13	77376	32	0	0
T16	1346	12	0	0
T17	186235	19851	0	0
T18	4850	59	0	0
T19	395	4	0	0
T20	75480	582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3479963	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3479963	0	0
T1	26270	369	0	0
T2	436006	2187	0	0
T3	24476	192	0	0
T4	27515	129	0	0
T13	77376	7	0	0
T16	1346	12	0	0
T17	186235	7810	0	0
T18	4850	54	0	0
T19	395	4	0	0
T20	75480	682	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1474709	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1474709	0	0
T1	26270	405	0	0
T2	436006	9778	0	0
T3	24476	163	0	0
T4	27515	237	0	0
T13	77376	33	0	0
T16	1346	11	0	0
T17	186235	23162	0	0
T18	4850	58	0	0
T19	395	6	0	0
T20	75480	571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3297883	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3297883	0	0
T1	26270	405	0	0
T2	436006	2737	0	0
T3	24476	197	0	0
T4	27515	86	0	0
T13	77376	5	0	0
T16	1346	11	0	0
T17	186235	10804	0	0
T18	4850	52	0	0
T19	395	6	0	0
T20	75480	593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1449068	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1449068	0	0
T1	26270	705	0	0
T2	436006	6809	0	0
T3	24476	238	0	0
T4	27515	252	0	0
T13	77376	26	0	0
T16	1346	14	0	0
T17	186235	17533	0	0
T18	4850	67	0	0
T19	395	5	0	0
T20	75480	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2728494	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2728494	0	0
T1	26270	705	0	0
T2	436006	1214	0	0
T3	24476	170	0	0
T4	27515	90	0	0
T13	77376	374	0	0
T16	1346	14	0	0
T17	186235	4781	0	0
T18	4850	68	0	0
T19	395	5	0	0
T20	75480	660	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1454925	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1454925	0	0
T1	26270	716	0	0
T2	436006	5807	0	0
T3	24476	214	0	0
T4	27515	202	0	0
T13	77376	16	0	0
T16	1346	14	0	0
T17	186235	23989	0	0
T18	4850	30	0	0
T19	395	8	0	0
T20	75480	443	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3232649	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3232649	0	0
T1	26270	716	0	0
T2	436006	1711	0	0
T3	24476	226	0	0
T4	27515	68	0	0
T13	77376	3	0	0
T16	1346	14	0	0
T17	186235	9536	0	0
T18	4850	38	0	0
T19	395	8	0	0
T20	75480	466	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1453661	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1453661	0	0
T1	26270	404	0	0
T2	436006	4670	0	0
T3	24476	213	0	0
T4	27515	225	0	0
T13	77376	14	0	0
T16	1346	12	0	0
T17	186235	22742	0	0
T18	4850	58	0	0
T19	395	6	0	0
T20	75480	460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2683263	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2683263	0	0
T1	26270	404	0	0
T2	436006	1345	0	0
T3	24476	164	0	0
T4	27515	102	0	0
T13	77376	3	0	0
T16	1346	12	0	0
T17	186235	7310	0	0
T18	4850	37	0	0
T19	395	6	0	0
T20	75480	558	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1500896	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1500896	0	0
T1	26270	392	0	0
T2	436006	7873	0	0
T3	24476	155	0	0
T4	27515	248	0	0
T13	77376	9	0	0
T16	1346	18	0	0
T17	186235	28018	0	0
T18	4850	42	0	0
T19	395	3	0	0
T20	75480	527	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3686491	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3686491	0	0
T1	26270	391	0	0
T2	436006	1982	0	0
T3	24476	198	0	0
T4	27515	73	0	0
T13	77376	3	0	0
T16	1346	18	0	0
T17	186235	9573	0	0
T18	4850	25	0	0
T19	395	3	0	0
T20	75480	623	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1469682	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1469682	0	0
T1	26270	554	0	0
T2	436006	5083	0	0
T3	24476	219	0	0
T4	27515	239	0	0
T13	77376	26	0	0
T16	1346	15	0	0
T17	186235	17156	0	0
T18	4850	14	0	0
T19	395	3	0	0
T20	75480	681	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3683838	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3683838	0	0
T1	26270	554	0	0
T2	436006	2113	0	0
T3	24476	188	0	0
T4	27515	110	0	0
T13	77376	4	0	0
T16	1346	15	0	0
T17	186235	4990	0	0
T18	4850	44	0	0
T19	395	3	0	0
T20	75480	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1465886	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1465886	0	0
T1	26270	391	0	0
T2	436006	5954	0	0
T3	24476	172	0	0
T4	27515	233	0	0
T13	77376	51	0	0
T16	1346	18	0	0
T17	186235	23573	0	0
T18	4850	23	0	0
T19	395	6	0	0
T20	75480	685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3717234	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3717234	0	0
T1	26270	391	0	0
T2	436006	1488	0	0
T3	24476	219	0	0
T4	27515	108	0	0
T13	77376	9	0	0
T16	1346	18	0	0
T17	186235	10639	0	0
T18	4850	31	0	0
T19	395	6	0	0
T20	75480	720	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1443888	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1443888	0	0
T1	26270	435	0	0
T2	436006	4920	0	0
T3	24476	140	0	0
T4	27515	217	0	0
T13	77376	26	0	0
T16	1346	18	0	0
T17	186235	26121	0	0
T18	4850	11	0	0
T19	395	8	0	0
T20	75480	442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2937058	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2937058	0	0
T1	26270	435	0	0
T2	436006	2700	0	0
T3	24476	160	0	0
T4	27515	124	0	0
T13	77376	4	0	0
T16	1346	18	0	0
T17	186235	8303	0	0
T18	4850	27	0	0
T19	395	8	0	0
T20	75480	455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1479781	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1479781	0	0
T1	26270	406	0	0
T2	436006	5133	0	0
T3	24476	180	0	0
T4	27515	171	0	0
T13	77376	19	0	0
T16	1346	13	0	0
T17	186235	16560	0	0
T18	4850	37	0	0
T19	395	4	0	0
T20	75480	621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3227096	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3227096	0	0
T1	26270	406	0	0
T2	436006	3077	0	0
T3	24476	188	0	0
T4	27515	64	0	0
T13	77376	6	0	0
T16	1346	13	0	0
T17	186235	6693	0	0
T18	4850	29	0	0
T19	395	4	0	0
T20	75480	585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1425254	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1425254	0	0
T1	26270	409	0	0
T2	436006	5446	0	0
T3	24476	119	0	0
T4	27515	279	0	0
T13	77376	36	0	0
T16	1346	13	0	0
T17	186235	22388	0	0
T18	4850	36	0	0
T19	395	4	0	0
T20	75480	529	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2482668	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2482668	0	0
T1	26270	409	0	0
T2	436006	1904	0	0
T3	24476	131	0	0
T4	27515	120	0	0
T13	77376	6	0	0
T16	1346	13	0	0
T17	186235	8467	0	0
T18	4850	67	0	0
T19	395	4	0	0
T20	75480	599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1470244	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1470244	0	0
T1	26270	393	0	0
T2	436006	6776	0	0
T3	24476	151	0	0
T4	27515	239	0	0
T13	77376	31	0	0
T16	1346	19	0	0
T17	186235	18580	0	0
T18	4850	20	0	0
T19	395	5	0	0
T20	75480	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3247539	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3247539	0	0
T1	26270	393	0	0
T2	436006	2853	0	0
T3	24476	142	0	0
T4	27515	129	0	0
T13	77376	7	0	0
T16	1346	19	0	0
T17	186235	6596	0	0
T18	4850	30	0	0
T19	395	5	0	0
T20	75480	529	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1476912	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1476912	0	0
T1	26270	382	0	0
T2	436006	3371	0	0
T3	24476	166	0	0
T4	27515	256	0	0
T13	77376	34	0	0
T16	1346	22	0	0
T17	186235	27659	0	0
T18	4850	15	0	0
T19	395	3	0	0
T20	75480	580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3752228	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3752228	0	0
T1	26270	382	0	0
T2	436006	2082	0	0
T3	24476	177	0	0
T4	27515	156	0	0
T13	77376	7	0	0
T16	1346	22	0	0
T17	186235	12772	0	0
T18	4850	17	0	0
T19	395	3	0	0
T20	75480	582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1477029	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1477029	0	0
T1	26270	379	0	0
T2	436006	4089	0	0
T3	24476	165	0	0
T4	27515	329	0	0
T13	77376	24	0	0
T16	1346	20	0	0
T17	186235	20422	0	0
T18	4850	20	0	0
T19	395	2	0	0
T20	75480	539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3552037	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3552037	0	0
T1	26270	379	0	0
T2	436006	541	0	0
T3	24476	170	0	0
T4	27515	114	0	0
T13	77376	6	0	0
T16	1346	20	0	0
T17	186235	6017	0	0
T18	4850	54	0	0
T19	395	2	0	0
T20	75480	509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1431278	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1431278	0	0
T1	26270	392	0	0
T2	436006	3852	0	0
T3	24476	179	0	0
T4	27515	289	0	0
T13	77376	12	0	0
T16	1346	15	0	0
T17	186235	22084	0	0
T18	4850	54	0	0
T19	395	2	0	0
T20	75480	632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2324584	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2324584	0	0
T1	26270	392	0	0
T2	436006	792	0	0
T3	24476	142	0	0
T4	27515	110	0	0
T13	77376	3	0	0
T16	1346	15	0	0
T17	186235	8304	0	0
T18	4850	58	0	0
T19	395	2	0	0
T20	75480	614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1470295	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1470295	0	0
T1	26270	396	0	0
T2	436006	3414	0	0
T3	24476	134	0	0
T4	27515	223	0	0
T13	77376	16	0	0
T16	1346	12	0	0
T17	186235	18921	0	0
T18	4850	73	0	0
T19	395	1	0	0
T20	75480	656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3387107	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3387107	0	0
T1	26270	396	0	0
T2	436006	1424	0	0
T3	24476	146	0	0
T4	27515	114	0	0
T13	77376	4	0	0
T16	1346	12	0	0
T17	186235	9733	0	0
T18	4850	117	0	0
T19	395	1	0	0
T20	75480	700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1451578	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1451578	0	0
T1	26270	389	0	0
T2	436006	3427	0	0
T3	24476	189	0	0
T4	27515	199	0	0
T13	77376	17	0	0
T16	1346	14	0	0
T17	186235	19467	0	0
T18	4850	16	0	0
T19	395	5	0	0
T20	75480	542	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2877094	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2877094	0	0
T1	26270	389	0	0
T2	436006	2458	0	0
T3	24476	242	0	0
T4	27515	106	0	0
T13	77376	4	0	0
T16	1346	14	0	0
T17	186235	9346	0	0
T18	4850	37	0	0
T19	395	5	0	0
T20	75480	610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1395961	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1395961	0	0
T1	26270	411	0	0
T2	436006	7560	0	0
T3	24476	233	0	0
T4	27515	274	0	0
T13	77376	11	0	0
T16	1346	21	0	0
T17	186235	22437	0	0
T18	4850	51	0	0
T19	395	9	0	0
T20	75480	700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	4034517	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	4034517	0	0
T1	26270	411	0	0
T2	436006	3985	0	0
T3	24476	203	0	0
T4	27515	97	0	0
T13	77376	2	0	0
T16	1346	21	0	0
T17	186235	9764	0	0
T18	4850	47	0	0
T19	395	9	0	0
T20	75480	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1454307	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1454307	0	0
T1	26270	387	0	0
T2	436006	4838	0	0
T3	24476	142	0	0
T4	27515	262	0	0
T13	77376	55	0	0
T16	1346	14	0	0
T17	186235	16489	0	0
T18	4850	39	0	0
T19	395	11	0	0
T20	75480	601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3615205	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3615205	0	0
T1	26270	387	0	0
T2	436006	2010	0	0
T3	24476	150	0	0
T4	27515	188	0	0
T13	77376	8	0	0
T16	1346	14	0	0
T17	186235	9058	0	0
T18	4850	54	0	0
T19	395	11	0	0
T20	75480	648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1421158	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1421158	0	0
T1	26270	356	0	0
T2	436006	5158	0	0
T3	24476	206	0	0
T4	27515	241	0	0
T13	77376	19	0	0
T16	1346	9	0	0
T17	186235	17795	0	0
T18	4850	21	0	0
T19	395	4	0	0
T20	75480	610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3139612	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3139612	0	0
T1	26270	356	0	0
T2	436006	3192	0	0
T3	24476	161	0	0
T4	27515	117	0	0
T13	77376	4	0	0
T16	1346	9	0	0
T17	186235	8306	0	0
T18	4850	9	0	0
T19	395	4	0	0
T20	75480	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1393070	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1393070	0	0
T1	26270	396	0	0
T2	436006	6017	0	0
T3	24476	166	0	0
T4	27515	194	0	0
T13	77376	17	0	0
T16	1346	16	0	0
T17	186235	21379	0	0
T18	4850	51	0	0
T19	395	9	0	0
T20	75480	516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2621664	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2621664	0	0
T1	26270	396	0	0
T2	436006	3927	0	0
T3	24476	158	0	0
T4	27515	54	0	0
T13	77376	4	0	0
T16	1346	16	0	0
T17	186235	9984	0	0
T18	4850	46	0	0
T19	395	9	0	0
T20	75480	530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1438924	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1438924	0	0
T1	26270	539	0	0
T2	436006	4333	0	0
T3	24476	150	0	0
T4	27515	249	0	0
T13	77376	40	0	0
T16	1346	15	0	0
T17	186235	19285	0	0
T18	4850	58	0	0
T19	395	6	0	0
T20	75480	639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3393080	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3393080	0	0
T1	26270	538	0	0
T2	436006	1126	0	0
T3	24476	146	0	0
T4	27515	132	0	0
T13	77376	7	0	0
T16	1346	15	0	0
T17	186235	3691	0	0
T18	4850	47	0	0
T19	395	6	0	0
T20	75480	756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1427135	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1427135	0	0
T1	26270	399	0	0
T2	436006	5193	0	0
T3	24476	165	0	0
T4	27515	266	0	0
T13	77376	20	0	0
T16	1346	15	0	0
T17	186235	19670	0	0
T18	4850	66	0	0
T19	395	11	0	0
T20	75480	523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	2849209	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	2849209	0	0
T1	26270	399	0	0
T2	436006	2101	0	0
T3	24476	155	0	0
T4	27515	114	0	0
T13	77376	3	0	0
T16	1346	15	0	0
T17	186235	5543	0	0
T18	4850	74	0	0
T19	395	11	0	0
T20	75480	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1418656	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1418656	0	0
T1	26270	402	0	0
T2	436006	3948	0	0
T3	24476	173	0	0
T4	27515	251	0	0
T13	77376	51	0	0
T16	1346	13	0	0
T17	186235	14962	0	0
T18	4850	111	0	0
T19	395	8	0	0
T20	75480	528	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3343223	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3343223	0	0
T1	26270	401	0	0
T2	436006	1562	0	0
T3	24476	148	0	0
T4	27515	102	0	0
T13	77376	10	0	0
T16	1346	13	0	0
T17	186235	6432	0	0
T18	4850	132	0	0
T19	395	8	0	0
T20	75480	622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	1423042	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	1423042	0	0
T1	26270	371	0	0
T2	436006	5398	0	0
T3	24476	248	0	0
T4	27515	316	0	0
T13	77376	63	0	0
T16	1346	19	0	0
T17	186235	25356	0	0
T18	4850	44	0	0
T19	395	4	0	0
T20	75480	669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308146919	3788537	0	0
DepthKnown_A	308146919	308022279	0	0
RvalidKnown_A	308146919	308022279	0	0
WreadyKnown_A	308146919	308022279	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	3788537	0	0
T1	26270	371	0	0
T2	436006	2166	0	0
T3	24476	190	0	0
T4	27515	121	0	0
T13	77376	16	0	0
T16	1346	19	0	0
T17	186235	11275	0	0
T18	4850	58	0	0
T19	395	4	0	0
T20	75480	726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308146919	308022279	0	0
T1	26270	25471	0	0
T2	436006	435982	0	0
T3	24476	24426	0	0
T4	27515	27500	0	0
T13	77376	77334	0	0
T16	1346	1262	0	0
T17	186235	186230	0	0
T18	4850	4843	0	0
T19	395	378	0	0
T20	75480	75394	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0