Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1766137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

278787

1

T1

5

T2

212

T3

4136

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	691301	1			T1	22		T2	473		T3	10008
values[0x0]	660418	1			T1	5		T2	533		T3	9945
values[0x1]	693205	1			T1	36		T2	509		T3	10138

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1367193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

677731

1

T1

21

T2

512

T3

9968

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7841	1			T3	132		T4	1		T14	2
valid_sources[0x01]	7801	1			T3	70		T4	19		T14	1
valid_sources[0x02]	7348	1			T3	119		T4	17		T15	1
valid_sources[0x03]	8226	1			T3	109		T4	4		T14	2
valid_sources[0x04]	7684	1			T3	123		T4	3		T14	1
valid_sources[0x05]	8735	1			T3	101		T4	21		T12	1
valid_sources[0x06]	7852	1			T3	119		T4	28		T14	2
valid_sources[0x07]	7838	1			T3	105		T4	22		T15	4
valid_sources[0x08]	7624	1			T3	118		T4	3		T15	1
valid_sources[0x09]	8524	1			T3	104		T4	3		T15	3
valid_sources[0x0a]	8071	1			T3	102		T4	9		T15	1
valid_sources[0x0b]	7751	1			T2	82		T3	118		T4	1
valid_sources[0x0c]	7541	1			T3	121		T4	4		T14	1
valid_sources[0x0d]	8012	1			T3	115		T4	35		T15	4
valid_sources[0x0e]	7968	1			T3	107		T4	17		T12	1
valid_sources[0x0f]	8252	1			T3	180		T4	13		T14	1
valid_sources[0x10]	8161	1			T3	115		T4	18		T15	1
valid_sources[0x11]	7686	1			T2	59		T3	153		T4	17
valid_sources[0x12]	7980	1			T3	122		T4	22		T12	1
valid_sources[0x13]	8450	1			T3	129		T4	21		T14	2
valid_sources[0x14]	9626	1			T3	107		T4	22		T14	1
valid_sources[0x15]	7383	1			T3	99		T4	1		T15	5
valid_sources[0x16]	8623	1			T3	148		T4	24		T15	3
valid_sources[0x17]	7614	1			T3	118		T4	32		T14	2
valid_sources[0x18]	7851	1			T3	135		T4	29		T15	2
valid_sources[0x19]	7350	1			T3	74		T4	17		T15	5
valid_sources[0x1a]	7585	1			T3	92		T4	5		T14	1
valid_sources[0x1b]	7871	1			T3	127		T4	3		T14	3
valid_sources[0x1c]	7984	1			T3	141		T4	4		T14	1
valid_sources[0x1d]	8061	1			T3	104		T4	10		T14	1
valid_sources[0x1e]	7522	1			T3	107		T4	9		T15	1
valid_sources[0x1f]	7444	1			T3	103		T4	7		T14	2
valid_sources[0x20]	8089	1			T3	94		T4	13		T14	1
valid_sources[0x21]	7497	1			T3	146		T4	10		T15	2
valid_sources[0x22]	8018	1			T2	142		T3	110		T4	4
valid_sources[0x23]	7866	1			T3	167		T4	15		T14	1
valid_sources[0x24]	7474	1			T3	118		T4	11		T15	4
valid_sources[0x25]	7957	1			T3	118		T4	1		T18	11
valid_sources[0x26]	8899	1			T3	100		T4	1		T17	3
valid_sources[0x27]	8385	1			T3	115		T4	4		T15	3
valid_sources[0x28]	7484	1			T3	95		T4	25		T15	6
valid_sources[0x29]	8051	1			T3	114		T4	46		T13	1
valid_sources[0x2a]	7882	1			T3	124		T4	20		T14	1
valid_sources[0x2b]	8461	1			T3	116		T4	26		T13	1
valid_sources[0x2c]	10162	1			T3	103		T4	45		T14	1
valid_sources[0x2d]	7560	1			T3	86		T4	6		T14	1
valid_sources[0x2e]	8009	1			T3	145		T4	3		T15	1
valid_sources[0x2f]	8103	1			T3	102		T4	22		T12	1
valid_sources[0x30]	8527	1			T3	119		T4	29		T14	3
valid_sources[0x31]	8324	1			T3	99		T4	14		T14	1
valid_sources[0x32]	8285	1			T3	100		T4	4		T13	2
valid_sources[0x33]	8000	1			T3	150		T4	6		T15	1
valid_sources[0x34]	8179	1			T3	105		T4	19		T15	4
valid_sources[0x35]	7290	1			T3	107		T4	27		T14	2
valid_sources[0x36]	7704	1			T3	93		T4	27		T15	4
valid_sources[0x37]	7466	1			T3	120		T4	36		T15	1
valid_sources[0x38]	7946	1			T2	365		T3	106		T4	18
valid_sources[0x39]	8682	1			T3	171		T4	15		T14	1
valid_sources[0x3a]	8232	1			T3	137		T4	2		T14	2
valid_sources[0x3b]	7453	1			T3	134		T4	21		T15	1
valid_sources[0x3c]	7495	1			T3	126		T4	5		T14	1
valid_sources[0x3d]	7932	1			T3	109		T4	20		T14	3
valid_sources[0x3e]	8763	1			T3	105		T4	24		T15	4
valid_sources[0x3f]	8419	1			T1	4		T3	94		T4	4
valid_sources[0x40]	8515	1			T3	116		T4	9		T15	1
valid_sources[0x41]	8088	1			T3	121		T4	3		T14	2
valid_sources[0x42]	7688	1			T3	116		T4	30		T14	2
valid_sources[0x43]	8283	1			T3	148		T4	3		T15	1
valid_sources[0x44]	8036	1			T3	118		T4	23		T14	2
valid_sources[0x45]	7377	1			T3	105		T4	4		T17	37
valid_sources[0x46]	8906	1			T3	144		T4	6		T15	3
valid_sources[0x47]	8255	1			T3	149		T4	13		T15	1
valid_sources[0x48]	8064	1			T3	109		T4	27		T17	4
valid_sources[0x49]	8477	1			T3	102		T4	6		T17	1
valid_sources[0x4a]	8093	1			T3	106		T4	13		T15	3
valid_sources[0x4b]	8038	1			T3	87		T4	1		T15	6
valid_sources[0x4c]	9027	1			T3	110		T4	39		T14	2
valid_sources[0x4d]	8774	1			T3	152		T4	16		T14	1
valid_sources[0x4e]	10135	1			T3	96		T4	27		T14	1
valid_sources[0x4f]	7356	1			T1	11		T3	107		T4	34
valid_sources[0x50]	8665	1			T3	107		T4	8		T14	2
valid_sources[0x51]	7775	1			T3	116		T4	5		T15	1
valid_sources[0x52]	8471	1			T3	87		T4	31		T14	3
valid_sources[0x53]	8107	1			T3	109		T4	2		T14	3
valid_sources[0x54]	7666	1			T3	102		T14	3		T13	2
valid_sources[0x55]	7400	1			T3	129		T4	5		T15	4
valid_sources[0x56]	7277	1			T3	119		T4	3		T14	1
valid_sources[0x57]	7736	1			T3	93		T4	14		T17	8
valid_sources[0x58]	7548	1			T3	133		T4	29		T14	2
valid_sources[0x59]	8351	1			T3	118		T4	7		T15	2
valid_sources[0x5a]	7984	1			T3	162		T4	2		T14	2
valid_sources[0x5b]	8010	1			T3	114		T4	20		T15	4
valid_sources[0x5c]	7720	1			T3	120		T4	13		T15	1
valid_sources[0x5d]	7258	1			T3	101		T4	4		T14	2
valid_sources[0x5e]	7090	1			T3	114		T4	18		T15	2
valid_sources[0x5f]	7153	1			T3	107		T4	12		T15	3
valid_sources[0x60]	7287	1			T3	101		T4	64		T14	3
valid_sources[0x61]	8525	1			T3	101		T4	18		T12	1
valid_sources[0x62]	8052	1			T3	107		T4	24		T14	2
valid_sources[0x63]	7431	1			T3	98		T4	11		T15	8
valid_sources[0x64]	7526	1			T2	94		T3	139		T4	5
valid_sources[0x65]	8200	1			T3	110		T4	4		T14	1
valid_sources[0x66]	7545	1			T3	129		T4	12		T16	5
valid_sources[0x67]	7903	1			T3	123		T4	26		T15	2
valid_sources[0x68]	7774	1			T3	108		T4	21		T14	1
valid_sources[0x69]	7731	1			T3	140		T4	5		T13	1
valid_sources[0x6a]	7655	1			T3	101		T4	1		T14	2
valid_sources[0x6b]	8006	1			T3	113		T4	61		T14	1
valid_sources[0x6c]	7715	1			T3	138		T4	17		T14	1
valid_sources[0x6d]	8180	1			T3	131		T4	18		T14	2
valid_sources[0x6e]	7313	1			T3	114		T4	21		T15	3
valid_sources[0x6f]	8055	1			T3	122		T4	4		T15	2
valid_sources[0x70]	7724	1			T3	101		T4	2		T12	1
valid_sources[0x71]	8604	1			T3	103		T4	12		T14	1
valid_sources[0x72]	8600	1			T3	115		T4	10		T14	1
valid_sources[0x73]	7727	1			T3	137		T4	21		T15	1
valid_sources[0x74]	9262	1			T3	111		T4	7		T12	1
valid_sources[0x75]	7795	1			T3	132		T4	5		T14	2
valid_sources[0x76]	8075	1			T2	178		T3	164		T4	22
valid_sources[0x77]	7742	1			T3	95		T4	19		T15	1
valid_sources[0x78]	7048	1			T3	108		T4	52		T15	3
valid_sources[0x79]	8123	1			T3	102		T4	2		T15	7
valid_sources[0x7a]	8019	1			T3	172		T4	8		T15	1
valid_sources[0x7b]	7746	1			T1	1		T3	92		T4	19
valid_sources[0x7c]	8677	1			T3	146		T4	3		T12	1
valid_sources[0x7d]	7793	1			T3	135		T4	21		T12	1
valid_sources[0x7e]	7304	1			T1	4		T3	113		T4	1
valid_sources[0x7f]	7385	1			T3	134		T4	23		T14	1
valid_sources[0x80]	8750	1			T3	130		T4	4		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29480

1

T1

1

T2

13

T3

413

values[0x0]

all_enables

biggest_size

220152

1

T1

3

T2

180

T3

3311

values[0x1]

all_enables

biggest_size

29155

1

T1

1

T2

19

T3

412