Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	355047031	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355047031	0	0
T1	1222032	17640	0	0
T2	172200	7430	0	0
T3	34819680	728650	0	0
T4	475776	16913	0	0
T12	518784	13265	0	0
T13	325472	10766	0	0
T14	13196344	331903	0	0
T15	937888	23619	0	0
T16	11140808	341082	0	0
T17	1957088	98137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1222032	1221752	0	0
T2	172200	170576	0	0
T3	34819680	34806240	0	0
T4	475776	450464	0	0
T12	518784	517944	0	0
T13	325472	322000	0	0
T14	13196344	13192816	0	0
T15	937888	934192	0	0
T16	11140808	11138792	0	0
T17	1957088	1941408	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1222032	1221752	0	0
T2	172200	170576	0	0
T3	34819680	34806240	0	0
T4	475776	450464	0	0
T12	518784	517944	0	0
T13	325472	322000	0	0
T14	13196344	13192816	0	0
T15	937888	934192	0	0
T16	11140808	11138792	0	0
T17	1957088	1941408	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1222032	1221752	0	0
T2	172200	170576	0	0
T3	34819680	34806240	0	0
T4	475776	450464	0	0
T12	518784	517944	0	0
T13	325472	322000	0	0
T14	13196344	13192816	0	0
T15	937888	934192	0	0
T16	11140808	11138792	0	0
T17	1957088	1941408	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	129709273	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	129709273	0	0
T1	21822	7842	0	0
T2	3075	2889	0	0
T3	621780	308916	0	0
T4	8496	5589	0	0
T12	9264	5861	0	0
T13	5812	5332	0	0
T14	235649	132918	0	0
T15	16748	10134	0	0
T16	198943	195877	0	0
T17	34948	32194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	93159441	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	93159441	0	0
T1	21822	2869	0	0
T2	3075	1515	0	0
T3	621780	102420	0	0
T4	8496	3968	0	0
T12	9264	2402	0	0
T13	5812	2724	0	0
T14	235649	69608	0	0
T15	16748	4611	0	0
T16	198943	72179	0	0
T17	34948	22807	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1478056	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1478056	0	0
T1	21822	119	0	0
T2	3075	61	0	0
T3	621780	5786	0	0
T4	8496	120	0	0
T12	9264	75	0	0
T13	5812	43	0	0
T14	235649	2121	0	0
T15	16748	271	0	0
T16	198943	37	0	0
T17	34948	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3022679	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3022679	0	0
T1	21822	99	0	0
T2	3075	61	0	0
T3	621780	2613	0	0
T4	8496	120	0	0
T12	9264	69	0	0
T13	5812	43	0	0
T14	235649	2413	0	0
T15	16748	247	0	0
T16	198943	4601	0	0
T17	34948	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1455631	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1455631	0	0
T1	21822	196	0	0
T2	3075	46	0	0
T3	621780	12674	0	0
T4	8496	393	0	0
T12	9264	69	0	0
T13	5812	42	0	0
T14	235649	2790	0	0
T15	16748	90	0	0
T16	198943	52	0	0
T17	34948	743	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	4290179	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	4290179	0	0
T1	21822	75	0	0
T2	3075	46	0	0
T3	621780	6245	0	0
T4	8496	393	0	0
T12	9264	59	0	0
T13	5812	42	0	0
T14	235649	3147	0	0
T15	16748	102	0	0
T16	198943	2535	0	0
T17	34948	743	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1489913	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1489913	0	0
T1	21822	198	0	0
T2	3075	66	0	0
T3	621780	7313	0	0
T4	8496	119	0	0
T12	9264	124	0	0
T13	5812	58	0	0
T14	235649	3908	0	0
T15	16748	145	0	0
T16	198943	16	0	0
T17	34948	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3315799	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3315799	0	0
T1	21822	80	0	0
T2	3075	66	0	0
T3	621780	3513	0	0
T4	8496	119	0	0
T12	9264	81	0	0
T13	5812	58	0	0
T14	235649	6533	0	0
T15	16748	190	0	0
T16	198943	1016	0	0
T17	34948	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1484940	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1484940	0	0
T1	21822	168	0	0
T2	3075	52	0	0
T3	621780	14860	0	0
T4	8496	140	0	0
T12	9264	116	0	0
T13	5812	41	0	0
T14	235649	2037	0	0
T15	16748	102	0	0
T16	198943	26	0	0
T17	34948	299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3207886	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3207886	0	0
T1	21822	115	0	0
T2	3075	52	0	0
T3	621780	6823	0	0
T4	8496	140	0	0
T12	9264	107	0	0
T13	5812	41	0	0
T14	235649	1696	0	0
T15	16748	124	0	0
T16	198943	2353	0	0
T17	34948	299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1500090	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1500090	0	0
T1	21822	114	0	0
T2	3075	54	0	0
T3	621780	9080	0	0
T4	8496	122	0	0
T12	9264	33	0	0
T13	5812	45	0	0
T14	235649	2241	0	0
T15	16748	146	0	0
T16	198943	35	0	0
T17	34948	1139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3335374	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3335374	0	0
T1	21822	103	0	0
T2	3075	54	0	0
T3	621780	4399	0	0
T4	8496	122	0	0
T12	9264	49	0	0
T13	5812	45	0	0
T14	235649	1614	0	0
T15	16748	176	0	0
T16	198943	1076	0	0
T17	34948	1139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1510713	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1510713	0	0
T1	21822	164	0	0
T2	3075	52	0	0
T3	621780	9265	0	0
T4	8496	128	0	0
T12	9264	81	0	0
T13	5812	51	0	0
T14	235649	2294	0	0
T15	16748	81	0	0
T16	198943	13	0	0
T17	34948	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3725570	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3725570	0	0
T1	21822	102	0	0
T2	3075	52	0	0
T3	621780	4232	0	0
T4	8496	128	0	0
T12	9264	82	0	0
T13	5812	51	0	0
T14	235649	3122	0	0
T15	16748	164	0	0
T16	198943	699	0	0
T17	34948	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1440610	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1440610	0	0
T1	21822	111	0	0
T2	3075	53	0	0
T3	621780	15025	0	0
T4	8496	174	0	0
T12	9264	115	0	0
T13	5812	41	0	0
T14	235649	3071	0	0
T15	16748	164	0	0
T16	198943	23	0	0
T17	34948	1571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3110895	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3110895	0	0
T1	21822	54	0	0
T2	3075	53	0	0
T3	621780	6544	0	0
T4	8496	174	0	0
T12	9264	138	0	0
T13	5812	41	0	0
T14	235649	3507	0	0
T15	16748	122	0	0
T16	198943	2228	0	0
T17	34948	1571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1444413	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1444413	0	0
T1	21822	255	0	0
T2	3075	62	0	0
T3	621780	4721	0	0
T4	8496	120	0	0
T12	9264	142	0	0
T13	5812	60	0	0
T14	235649	1424	0	0
T15	16748	215	0	0
T16	198943	40	0	0
T17	34948	842	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3260761	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3260761	0	0
T1	21822	89	0	0
T2	3075	62	0	0
T3	621780	2074	0	0
T4	8496	120	0	0
T12	9264	136	0	0
T13	5812	60	0	0
T14	235649	1962	0	0
T15	16748	215	0	0
T16	198943	2872	0	0
T17	34948	842	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1499202	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1499202	0	0
T1	21822	136	0	0
T2	3075	73	0	0
T3	621780	9911	0	0
T4	8496	158	0	0
T12	9264	67	0	0
T13	5812	59	0	0
T14	235649	2393	0	0
T15	16748	185	0	0
T16	198943	60	0	0
T17	34948	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3566687	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3566687	0	0
T1	21822	35	0	0
T2	3075	73	0	0
T3	621780	4966	0	0
T4	8496	158	0	0
T12	9264	68	0	0
T13	5812	59	0	0
T14	235649	4168	0	0
T15	16748	225	0	0
T16	198943	4729	0	0
T17	34948	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1528775	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1528775	0	0
T1	21822	154	0	0
T2	3075	53	0	0
T3	621780	6813	0	0
T4	8496	139	0	0
T12	9264	115	0	0
T13	5812	54	0	0
T14	235649	582	0	0
T15	16748	180	0	0
T16	198943	17	0	0
T17	34948	1041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3895953	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3895953	0	0
T1	21822	64	0	0
T2	3075	53	0	0
T3	621780	3151	0	0
T4	8496	139	0	0
T12	9264	164	0	0
T13	5812	54	0	0
T14	235649	1917	0	0
T15	16748	248	0	0
T16	198943	1710	0	0
T17	34948	1041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1487452	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1487452	0	0
T1	21822	140	0	0
T2	3075	51	0	0
T3	621780	5230	0	0
T4	8496	116	0	0
T12	9264	113	0	0
T13	5812	52	0	0
T14	235649	4244	0	0
T15	16748	157	0	0
T16	198943	20	0	0
T17	34948	275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3295333	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3295333	0	0
T1	21822	37	0	0
T2	3075	51	0	0
T3	621780	2276	0	0
T4	8496	116	0	0
T12	9264	73	0	0
T13	5812	52	0	0
T14	235649	5236	0	0
T15	16748	157	0	0
T16	198943	1297	0	0
T17	34948	275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1466468	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1466468	0	0
T1	21822	217	0	0
T2	3075	49	0	0
T3	621780	4730	0	0
T4	8496	118	0	0
T12	9264	83	0	0
T13	5812	54	0	0
T14	235649	3006	0	0
T15	16748	76	0	0
T16	198943	33	0	0
T17	34948	789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3506072	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3506072	0	0
T1	21822	88	0	0
T2	3075	49	0	0
T3	621780	2473	0	0
T4	8496	118	0	0
T12	9264	59	0	0
T13	5812	54	0	0
T14	235649	1850	0	0
T15	16748	58	0	0
T16	198943	2652	0	0
T17	34948	789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1515576	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1515576	0	0
T1	21822	204	0	0
T2	3075	56	0	0
T3	621780	13443	0	0
T4	8496	134	0	0
T12	9264	66	0	0
T13	5812	56	0	0
T14	235649	1131	0	0
T15	16748	148	0	0
T16	198943	28	0	0
T17	34948	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3649779	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3649779	0	0
T1	21822	105	0	0
T2	3075	56	0	0
T3	621780	6003	0	0
T4	8496	134	0	0
T12	9264	51	0	0
T13	5812	56	0	0
T14	235649	2025	0	0
T15	16748	170	0	0
T16	198943	2451	0	0
T17	34948	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1477815	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1477815	0	0
T1	21822	198	0	0
T2	3075	69	0	0
T3	621780	4690	0	0
T4	8496	124	0	0
T12	9264	66	0	0
T13	5812	54	0	0
T14	235649	3619	0	0
T15	16748	193	0	0
T16	198943	42	0	0
T17	34948	1103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3457497	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3457497	0	0
T1	21822	77	0	0
T2	3075	69	0	0
T3	621780	2091	0	0
T4	8496	124	0	0
T12	9264	53	0	0
T13	5812	54	0	0
T14	235649	4123	0	0
T15	16748	200	0	0
T16	198943	3576	0	0
T17	34948	1103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1480591	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1480591	0	0
T1	21822	200	0	0
T2	3075	45	0	0
T3	621780	7301	0	0
T4	8496	111	0	0
T12	9264	87	0	0
T13	5812	48	0	0
T14	235649	732	0	0
T15	16748	159	0	0
T16	198943	23	0	0
T17	34948	821	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3225254	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3225254	0	0
T1	21822	81	0	0
T2	3075	45	0	0
T3	621780	3419	0	0
T4	8496	111	0	0
T12	9264	108	0	0
T13	5812	48	0	0
T14	235649	1266	0	0
T15	16748	197	0	0
T16	198943	2605	0	0
T17	34948	821	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1452169	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1452169	0	0
T1	21822	221	0	0
T2	3075	46	0	0
T3	621780	7634	0	0
T4	8496	136	0	0
T12	9264	57	0	0
T13	5812	50	0	0
T14	235649	2215	0	0
T15	16748	187	0	0
T16	198943	5	0	0
T17	34948	1064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3288429	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3288429	0	0
T1	21822	101	0	0
T2	3075	46	0	0
T3	621780	3353	0	0
T4	8496	136	0	0
T12	9264	37	0	0
T13	5812	50	0	0
T14	235649	1695	0	0
T15	16748	158	0	0
T16	198943	1414	0	0
T17	34948	1064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1478913	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1478913	0	0
T1	21822	164	0	0
T2	3075	56	0	0
T3	621780	6875	0	0
T4	8496	122	0	0
T12	9264	75	0	0
T13	5812	39	0	0
T14	235649	2552	0	0
T15	16748	184	0	0
T16	198943	23	0	0
T17	34948	1032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3285541	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3285541	0	0
T1	21822	75	0	0
T2	3075	56	0	0
T3	621780	2954	0	0
T4	8496	121	0	0
T12	9264	105	0	0
T13	5812	39	0	0
T14	235649	2010	0	0
T15	16748	185	0	0
T16	198943	1085	0	0
T17	34948	1032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1448118	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1448118	0	0
T1	21822	203	0	0
T2	3075	56	0	0
T3	621780	5268	0	0
T4	8496	143	0	0
T12	9264	86	0	0
T13	5812	51	0	0
T14	235649	3580	0	0
T15	16748	216	0	0
T16	198943	35	0	0
T17	34948	749	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	4178534	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	4178534	0	0
T1	21822	98	0	0
T2	3075	56	0	0
T3	621780	2594	0	0
T4	8496	143	0	0
T12	9264	84	0	0
T13	5812	51	0	0
T14	235649	2712	0	0
T15	16748	238	0	0
T16	198943	3653	0	0
T17	34948	749	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1513195	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1513195	0	0
T1	21822	159	0	0
T2	3075	70	0	0
T3	621780	4941	0	0
T4	8496	114	0	0
T12	9264	107	0	0
T13	5812	60	0	0
T14	235649	1231	0	0
T15	16748	121	0	0
T16	198943	59	0	0
T17	34948	723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3569305	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3569305	0	0
T1	21822	71	0	0
T2	3075	70	0	0
T3	621780	2325	0	0
T4	8496	114	0	0
T12	9264	114	0	0
T13	5812	60	0	0
T14	235649	846	0	0
T15	16748	177	0	0
T16	198943	4181	0	0
T17	34948	723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1483833	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1483833	0	0
T1	21822	102	0	0
T2	3075	64	0	0
T3	621780	9836	0	0
T4	8496	125	0	0
T12	9264	184	0	0
T13	5812	41	0	0
T14	235649	3160	0	0
T15	16748	151	0	0
T16	198943	13	0	0
T17	34948	1216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3324596	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3324596	0	0
T1	21822	69	0	0
T2	3075	64	0	0
T3	621780	4463	0	0
T4	8496	124	0	0
T12	9264	137	0	0
T13	5812	41	0	0
T14	235649	2212	0	0
T15	16748	118	0	0
T16	198943	377	0	0
T17	34948	1216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1489924	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1489924	0	0
T1	21822	93	0	0
T2	3075	59	0	0
T3	621780	7170	0	0
T4	8496	110	0	0
T12	9264	109	0	0
T13	5812	54	0	0
T14	235649	1470	0	0
T15	16748	120	0	0
T16	198943	62	0	0
T17	34948	816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3223016	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3223016	0	0
T1	21822	38	0	0
T2	3075	59	0	0
T3	621780	3371	0	0
T4	8496	110	0	0
T12	9264	75	0	0
T13	5812	54	0	0
T14	235649	621	0	0
T15	16748	95	0	0
T16	198943	4677	0	0
T17	34948	816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1428009	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1428009	0	0
T1	21822	121	0	0
T2	3075	52	0	0
T3	621780	11187	0	0
T4	8496	105	0	0
T12	9264	105	0	0
T13	5812	63	0	0
T14	235649	1890	0	0
T15	16748	158	0	0
T16	198943	21	0	0
T17	34948	516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	2834946	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	2834946	0	0
T1	21822	118	0	0
T2	3075	52	0	0
T3	621780	4906	0	0
T4	8496	105	0	0
T12	9264	106	0	0
T13	5812	63	0	0
T14	235649	2156	0	0
T15	16748	170	0	0
T16	198943	2117	0	0
T17	34948	516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1486939	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1486939	0	0
T1	21822	178	0	0
T2	3075	57	0	0
T3	621780	7574	0	0
T4	8496	117	0	0
T12	9264	168	0	0
T13	5812	33	0	0
T14	235649	273	0	0
T15	16748	131	0	0
T16	198943	28	0	0
T17	34948	875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3298089	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3298089	0	0
T1	21822	102	0	0
T2	3075	57	0	0
T3	621780	3353	0	0
T4	8496	117	0	0
T12	9264	136	0	0
T13	5812	33	0	0
T14	235649	1521	0	0
T15	16748	159	0	0
T16	198943	2416	0	0
T17	34948	875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1472273	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1472273	0	0
T1	21822	265	0	0
T2	3075	47	0	0
T3	621780	4863	0	0
T4	8496	129	0	0
T12	9264	79	0	0
T13	5812	48	0	0
T14	235649	1165	0	0
T15	16748	165	0	0
T16	198943	17	0	0
T17	34948	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	2843668	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	2843668	0	0
T1	21822	118	0	0
T2	3075	47	0	0
T3	621780	2686	0	0
T4	8496	129	0	0
T12	9264	97	0	0
T13	5812	48	0	0
T14	235649	1424	0	0
T15	16748	189	0	0
T16	198943	2513	0	0
T17	34948	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1468780	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1468780	0	0
T1	21822	243	0	0
T2	3075	61	0	0
T3	621780	7656	0	0
T4	8496	124	0	0
T12	9264	95	0	0
T13	5812	59	0	0
T14	235649	1997	0	0
T15	16748	189	0	0
T16	198943	40	0	0
T17	34948	696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3826149	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3826149	0	0
T1	21822	68	0	0
T2	3075	61	0	0
T3	621780	3532	0	0
T4	8496	124	0	0
T12	9264	63	0	0
T13	5812	59	0	0
T14	235649	2660	0	0
T15	16748	195	0	0
T16	198943	3670	0	0
T17	34948	696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1532833	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1532833	0	0
T1	21822	105	0	0
T2	3075	54	0	0
T3	621780	7326	0	0
T4	8496	117	0	0
T12	9264	105	0	0
T13	5812	47	0	0
T14	235649	2130	0	0
T15	16748	153	0	0
T16	198943	23	0	0
T17	34948	771	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	3756533	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	3756533	0	0
T1	21822	66	0	0
T2	3075	54	0	0
T3	621780	3444	0	0
T4	8496	117	0	0
T12	9264	98	0	0
T13	5812	47	0	0
T14	235649	4606	0	0
T15	16748	129	0	0
T16	198943	3523	0	0
T17	34948	771	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	1508164	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	1508164	0	0
T1	21822	249	0	0
T2	3075	49	0	0
T3	621780	5669	0	0
T4	8496	121	0	0
T12	9264	78	0	0
T13	5812	52	0	0
T14	235649	2513	0	0
T15	16748	176	0	0
T16	198943	56	0	0
T17	34948	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320847481	2860398	0	0
DepthKnown_A	320847481	320715120	0	0
RvalidKnown_A	320847481	320715120	0	0
WreadyKnown_A	320847481	320715120	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	2860398	0	0
T1	21822	124	0	0
T2	3075	49	0	0
T3	621780	2670	0	0
T4	8496	121	0	0
T12	9264	53	0	0
T13	5812	52	0	0
T14	235649	2566	0	0
T15	16748	203	0	0
T16	198943	6153	0	0
T17	34948	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320847481	320715120	0	0
T1	21822	21817	0	0
T2	3075	3046	0	0
T3	621780	621540	0	0
T4	8496	8044	0	0
T12	9264	9249	0	0
T13	5812	5750	0	0
T14	235649	235586	0	0
T15	16748	16682	0	0
T16	198943	198907	0	0
T17	34948	34668	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0