Unified Coverage Report :: Group :: tl_agent_pkg::pending_req_on_rst_cg

Group : tl_agent_pkg::pending_req_on_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T6

1

T196

1

T197

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1093

1

T5

5

T40

4

T45

1

values[0x1]

10

1

T38

1

T198

1

T199

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1088

1

T5

4

T40

4

T45

1

values[0x1]

15

1

T5

1

T115

1

T200

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T132

1

T201

1

T202

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1083

1

T5

4

T40

4

T45

1

values[0x1]

20

1

T5

1

T192

1

T196

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1085

1

T5

5

T40

4

T45

1

values[0x1]

18

1

T38

1

T132

1

T172

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1084

1

T5

5

T40

4

T45

1

values[0x1]

19

1

T7

1

T191

1

T196

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1085

1

T5

5

T40

4

T45

1

values[0x1]

18

1

T172

1

T203

1

T6

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T198

1

T100

1

T204

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1088

1

T5

5

T40

4

T45

1

values[0x1]

15

1

T29

1

T199

1

T6

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

642

1

T5

2

T40

4

T45

1

values[0x1]

461

1

T5

3

T29

5

T38

7

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1081

1

T5

5

T40

4

T45

1

values[0x1]

22

1

T7

1

T205

1

T206

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1087

1

T5

4

T40

4

T45

1

values[0x1]

16

1

T5

1

T199

1

T6

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1075

1

T5

5

T40

4

T45

1

values[0x1]

28

1

T29

1

T7

1

T198

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1091

1

T5

5

T40

4

T45

1

values[0x1]

12

1

T29

1

T172

1

T100

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1092

1

T5

5

T40

4

T45

1

values[0x1]

11

1

T38

1

T207

1

T197

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1088

1

T5

5

T40

4

T45

1

values[0x1]

15

1

T7

1

T200

1

T192

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1092

1

T5

5

T40

4

T45

1

values[0x1]

11

1

T38

1

T207

1

T197

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1089

1

T5

5

T40

4

T45

1

values[0x1]

14

1

T198

1

T208

1

T209

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1081

1

T5

5

T40

4

T45

1

values[0x1]

22

1

T132

1

T115

1

T199

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1087

1

T5

5

T40

4

T45

1

values[0x1]

16

1

T210

1

T211

1

T212

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T199

1

T192

1

T201

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1078

1

T5

5

T40

4

T45

1

values[0x1]

25

1

T38

1

T172

1

T115

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1086

1

T5

5

T40

4

T45

1

values[0x1]

17

1

T29

1

T206

1

T213

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T29

1

T7

1

T206

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1089

1

T5

5

T40

4

T45

1

values[0x1]

14

1

T7

1

T192

2

T206

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1085

1

T5

5

T40

4

T45

1

values[0x1]

18

1

T38

1

T6

1

T191

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1090

1

T5

5

T40

4

T45

1

values[0x1]

13

1

T172

1

T198

1

T206

1