Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1676355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263355

1

T1

371

T2

34

T3

208

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	657382	1			T1	1076		T2	63		T3	547
values[0x0]	625178	1			T1	999		T2	62		T3	480
values[0x1]	657150	1			T1	963		T2	59		T3	523

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1299198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640512

1

T1

945

T2

74

T3

521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8165	1			T1	10		T3	8		T4	1
valid_sources[0x01]	7409	1			T1	3		T2	3		T3	8
valid_sources[0x02]	7618	1			T1	7		T3	7		T4	3
valid_sources[0x03]	7809	1			T1	7		T2	3		T3	11
valid_sources[0x04]	7530	1			T1	14		T3	3		T5	14
valid_sources[0x05]	7864	1			T1	1		T3	6		T5	6
valid_sources[0x06]	6921	1			T1	20		T2	2		T3	3
valid_sources[0x07]	7372	1			T1	6		T3	4		T5	1
valid_sources[0x08]	7352	1			T1	29		T3	4		T4	1
valid_sources[0x09]	7446	1			T1	18		T2	2		T3	3
valid_sources[0x0a]	7254	1			T1	16		T3	4		T4	5
valid_sources[0x0b]	7484	1			T1	13		T2	3		T3	8
valid_sources[0x0c]	8014	1			T1	6		T3	3		T5	1
valid_sources[0x0d]	7738	1			T1	2		T2	1		T3	8
valid_sources[0x0e]	7441	1			T1	7		T3	8		T5	39
valid_sources[0x0f]	8830	1			T1	38		T2	2		T3	9
valid_sources[0x10]	6894	1			T1	12		T3	13		T5	29
valid_sources[0x11]	6934	1			T1	9		T3	6		T4	1
valid_sources[0x12]	7125	1			T1	17		T2	1		T3	4
valid_sources[0x13]	7802	1			T1	9		T3	6		T5	19
valid_sources[0x14]	7805	1			T1	5		T3	7		T5	1
valid_sources[0x15]	7090	1			T1	8		T3	6		T4	1
valid_sources[0x16]	7445	1			T1	16		T3	9		T5	36
valid_sources[0x17]	7551	1			T1	15		T2	1		T3	10
valid_sources[0x18]	7601	1			T1	1		T2	2		T3	4
valid_sources[0x19]	7646	1			T1	2		T2	1		T3	11
valid_sources[0x1a]	7179	1			T1	24		T2	3		T3	7
valid_sources[0x1b]	7542	1			T1	16		T2	1		T3	6
valid_sources[0x1c]	8185	1			T1	18		T2	2		T3	4
valid_sources[0x1d]	7695	1			T1	10		T2	1		T3	5
valid_sources[0x1e]	6982	1			T1	11		T3	4		T5	44
valid_sources[0x1f]	7323	1			T1	7		T2	1		T3	5
valid_sources[0x20]	7123	1			T1	1		T3	9		T16	1
valid_sources[0x21]	8111	1			T1	11		T3	8		T4	2
valid_sources[0x22]	7214	1			T1	8		T2	1		T3	1
valid_sources[0x23]	7573	1			T1	5		T3	6		T5	58
valid_sources[0x24]	6946	1			T1	31		T3	9		T4	1
valid_sources[0x25]	7639	1			T1	3		T2	1		T3	2
valid_sources[0x26]	8082	1			T1	1		T2	3		T3	5
valid_sources[0x27]	7496	1			T1	9		T2	1		T3	5
valid_sources[0x28]	7557	1			T1	13		T2	2		T3	5
valid_sources[0x29]	7252	1			T1	7		T2	1		T3	3
valid_sources[0x2a]	7244	1			T1	4		T2	1		T3	8
valid_sources[0x2b]	7460	1			T1	34		T2	1		T3	6
valid_sources[0x2c]	7455	1			T1	4		T2	1		T3	5
valid_sources[0x2d]	7225	1			T1	2		T2	1		T3	8
valid_sources[0x2e]	7769	1			T1	10		T3	8		T4	2
valid_sources[0x2f]	8612	1			T1	20		T3	5		T5	24
valid_sources[0x30]	6990	1			T1	14		T3	6		T5	4
valid_sources[0x31]	7690	1			T1	4		T3	7		T4	2
valid_sources[0x32]	7413	1			T1	10		T2	1		T3	6
valid_sources[0x33]	7239	1			T1	2		T3	7		T5	37
valid_sources[0x34]	7410	1			T1	7		T2	1		T3	2
valid_sources[0x35]	6972	1			T1	21		T3	1		T15	19
valid_sources[0x36]	6803	1			T1	46		T3	11		T5	65
valid_sources[0x37]	7120	1			T1	4		T3	4		T5	63
valid_sources[0x38]	7666	1			T1	8		T3	9		T5	20
valid_sources[0x39]	8341	1			T1	14		T3	9		T5	38
valid_sources[0x3a]	7029	1			T1	8		T3	2		T4	2
valid_sources[0x3b]	7072	1			T1	28		T3	5		T4	2
valid_sources[0x3c]	8344	1			T1	11		T3	9		T5	1
valid_sources[0x3d]	7625	1			T1	2		T2	1		T3	8
valid_sources[0x3e]	7657	1			T1	5		T3	4		T4	2
valid_sources[0x3f]	7758	1			T1	37		T2	2		T3	3
valid_sources[0x40]	8192	1			T1	9		T3	3		T5	10
valid_sources[0x41]	7434	1			T1	7		T2	1		T3	9
valid_sources[0x42]	8178	1			T1	34		T2	1		T3	5
valid_sources[0x43]	7102	1			T1	15		T3	10		T4	3
valid_sources[0x44]	7631	1			T1	11		T3	10		T5	9
valid_sources[0x45]	8331	1			T3	7		T5	45		T14	9
valid_sources[0x46]	7134	1			T1	15		T2	1		T3	6
valid_sources[0x47]	8021	1			T1	4		T2	1		T3	7
valid_sources[0x48]	8077	1			T1	19		T3	4		T4	2
valid_sources[0x49]	7327	1			T1	22		T3	2		T4	2
valid_sources[0x4a]	7611	1			T1	4		T2	1		T3	5
valid_sources[0x4b]	7798	1			T2	2		T3	5		T5	36
valid_sources[0x4c]	8125	1			T1	10		T2	3		T3	9
valid_sources[0x4d]	7454	1			T1	12		T2	2		T3	6
valid_sources[0x4e]	7927	1			T1	8		T2	2		T3	4
valid_sources[0x4f]	7339	1			T1	8		T3	5		T5	14
valid_sources[0x50]	7273	1			T1	9		T3	3		T5	1
valid_sources[0x51]	8035	1			T1	8		T2	1		T3	7
valid_sources[0x52]	7619	1			T1	3		T2	2		T3	7
valid_sources[0x53]	7174	1			T1	12		T2	1		T14	3
valid_sources[0x54]	7286	1			T3	7		T5	32		T15	40
valid_sources[0x55]	7804	1			T1	35		T3	7		T4	1
valid_sources[0x56]	7920	1			T1	15		T2	1		T3	7
valid_sources[0x57]	7892	1			T1	3		T2	4		T3	5
valid_sources[0x58]	7395	1			T1	17		T2	1		T3	4
valid_sources[0x59]	7927	1			T1	10		T2	3		T3	6
valid_sources[0x5a]	7287	1			T1	28		T2	1		T3	7
valid_sources[0x5b]	7726	1			T1	3		T3	3		T5	26
valid_sources[0x5c]	6963	1			T1	33		T3	2		T4	1
valid_sources[0x5d]	7294	1			T1	14		T2	1		T3	5
valid_sources[0x5e]	7259	1			T1	16		T3	3		T5	30
valid_sources[0x5f]	8576	1			T1	13		T3	9		T5	18
valid_sources[0x60]	7819	1			T1	21		T3	11		T4	2
valid_sources[0x61]	7379	1			T1	19		T3	3		T14	13
valid_sources[0x62]	6936	1			T2	2		T3	8		T5	23
valid_sources[0x63]	8353	1			T3	7		T5	62		T16	1
valid_sources[0x64]	7558	1			T1	12		T3	7		T4	7
valid_sources[0x65]	7426	1			T1	9		T3	13		T14	5
valid_sources[0x66]	8114	1			T1	7		T3	1		T5	8
valid_sources[0x67]	8209	1			T1	16		T2	2		T3	10
valid_sources[0x68]	7983	1			T1	10		T2	5		T3	3
valid_sources[0x69]	7616	1			T1	11		T3	9		T5	16
valid_sources[0x6a]	7965	1			T1	4		T3	7		T5	25
valid_sources[0x6b]	7620	1			T3	4		T5	12		T17	1
valid_sources[0x6c]	7813	1			T1	25		T3	1		T4	2
valid_sources[0x6d]	7249	1			T1	20		T3	3		T5	30
valid_sources[0x6e]	7547	1			T1	20		T3	5		T16	1
valid_sources[0x6f]	8530	1			T1	28		T3	5		T4	1
valid_sources[0x70]	8338	1			T1	18		T2	1		T3	9
valid_sources[0x71]	6844	1			T1	1		T2	1		T3	3
valid_sources[0x72]	7781	1			T1	4		T3	5		T5	5
valid_sources[0x73]	7102	1			T1	23		T2	1		T3	2
valid_sources[0x74]	7106	1			T1	26		T3	6		T4	1
valid_sources[0x75]	7846	1			T1	7		T2	1		T3	10
valid_sources[0x76]	7262	1			T1	14		T2	1		T3	10
valid_sources[0x77]	7979	1			T1	9		T3	5		T14	4
valid_sources[0x78]	7357	1			T1	20		T2	1		T3	9
valid_sources[0x79]	7968	1			T1	32		T2	3		T3	4
valid_sources[0x7a]	7335	1			T1	21		T3	6		T4	2
valid_sources[0x7b]	7044	1			T1	29		T3	4		T5	2
valid_sources[0x7c]	6958	1			T3	6		T4	1		T5	9
valid_sources[0x7d]	8738	1			T1	6		T2	1		T3	3
valid_sources[0x7e]	7017	1			T1	24		T2	2		T3	6
valid_sources[0x7f]	8132	1			T1	11		T3	7		T5	10
valid_sources[0x80]	7173	1			T1	16		T3	3		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27973

1

T1

44

T2

6

T3

21

values[0x0]

all_enables

biggest_size

207515

1

T1

284

T2

23

T3

167

values[0x1]

all_enables

biggest_size

27867

1

T1

43

T2

5

T3

20