Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	370726464	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	370726464	0	0
T1	1151060	68518	0	0
T2	15561056	319760	0	0
T3	1892408	34762	0	0
T4	19488	706	0	0
T5	9840432	220800	0	0
T14	1930656	28736	0	0
T15	72296	2008	0	0
T16	41496	551	0	0
T17	3280648	80998	0	0
T18	8239000	191113	0	0
T19	951912	7373	0	0
T20	0	173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3222968	3219440	0	0
T2	15561056	15556128	0	0
T3	1892408	1891064	0	0
T4	19488	19096	0	0
T5	9840432	9824808	0	0
T14	1930656	1927856	0	0
T15	72296	70224	0	0
T16	41496	37744	0	0
T17	3280648	3278576	0	0
T18	8239000	8238328	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3222968	3219440	0	0
T2	15561056	15556128	0	0
T3	1892408	1891064	0	0
T4	19488	19096	0	0
T5	9840432	9824808	0	0
T14	1930656	1927856	0	0
T15	72296	70224	0	0
T16	41496	37744	0	0
T17	3280648	3278576	0	0
T18	8239000	8238328	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3222968	3219440	0	0
T2	15561056	15556128	0	0
T3	1892408	1891064	0	0
T4	19488	19096	0	0
T5	9840432	9824808	0	0
T14	1930656	1927856	0	0
T15	72296	70224	0	0
T16	41496	37744	0	0
T17	3280648	3278576	0	0
T18	8239000	8238328	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	133864836	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	133864836	0	0
T1	57553	21531	0	0
T2	277876	132088	0	0
T3	33793	14397	0	0
T4	348	274	0	0
T5	175722	86254	0	0
T14	34476	13317	0	0
T15	1291	504	0	0
T16	741	217	0	0
T17	58583	35857	0	0
T18	147125	76483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	98789750	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	98789750	0	0
T1	57553	12728	0	0
T2	277876	61219	0	0
T3	33793	8948	0	0
T4	348	144	0	0
T5	175722	45520	0	0
T14	34476	4419	0	0
T15	1291	504	0	0
T16	741	112	0	0
T17	58583	14342	0	0
T18	147125	39872	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1466455	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1466455	0	0
T2	277876	364	0	0
T3	33793	210	0	0
T4	348	5	0	0
T5	175722	1478	0	0
T14	34476	375	0	0
T15	1291	13	0	0
T16	741	6	0	0
T17	58583	638	0	0
T18	147125	1074	0	0
T19	26442	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3779617	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3779617	0	0
T2	277876	1101	0	0
T3	33793	178	0	0
T4	348	5	0	0
T5	175722	1660	0	0
T14	34476	171	0	0
T15	1291	13	0	0
T16	741	6	0	0
T17	58583	446	0	0
T18	147125	2102	0	0
T19	26442	169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1480146	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1480146	0	0
T1	57553	2343	0	0
T2	277876	1328	0	0
T3	33793	280	0	0
T4	348	7	0	0
T5	175722	1439	0	0
T14	34476	270	0	0
T15	1291	28	0	0
T16	741	3	0	0
T17	58583	551	0	0
T18	147125	1279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	2665037	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	2665037	0	0
T1	57553	1112	0	0
T2	277876	813	0	0
T3	33793	207	0	0
T4	348	7	0	0
T5	175722	1642	0	0
T14	34476	128	0	0
T15	1291	28	0	0
T16	741	3	0	0
T17	58583	482	0	0
T18	147125	2710	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1459027	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1459027	0	0
T1	57553	1827	0	0
T2	277876	520	0	0
T3	33793	253	0	0
T4	348	8	0	0
T5	175722	1721	0	0
T14	34476	286	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	660	0	0
T18	147125	1501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3238713	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3238713	0	0
T1	57553	973	0	0
T2	277876	478	0	0
T3	33793	195	0	0
T4	348	8	0	0
T5	175722	1788	0	0
T14	34476	144	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	556	0	0
T18	147125	1008	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1458988	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1458988	0	0
T2	277876	2854	0	0
T3	33793	230	0	0
T4	348	8	0	0
T5	175722	1608	0	0
T14	34476	259	0	0
T15	1291	19	0	0
T16	741	5	0	0
T17	58583	663	0	0
T18	147125	1199	0	0
T19	26442	214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3957591	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3957591	0	0
T2	277876	2672	0	0
T3	33793	163	0	0
T4	348	8	0	0
T5	175722	1725	0	0
T14	34476	141	0	0
T15	1291	19	0	0
T16	741	5	0	0
T17	58583	601	0	0
T18	147125	1236	0	0
T19	26442	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1476676	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1476676	0	0
T2	277876	2633	0	0
T3	33793	259	0	0
T4	348	6	0	0
T5	175722	1472	0	0
T14	34476	219	0	0
T15	1291	21	0	0
T16	741	5	0	0
T17	58583	609	0	0
T18	147125	846	0	0
T19	26442	172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3371950	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3371950	0	0
T2	277876	1185	0	0
T3	33793	279	0	0
T4	348	6	0	0
T5	175722	1482	0	0
T14	34476	114	0	0
T15	1291	21	0	0
T16	741	5	0	0
T17	58583	539	0	0
T18	147125	2329	0	0
T19	26442	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1474772	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1474772	0	0
T2	277876	6264	0	0
T3	33793	255	0	0
T4	348	9	0	0
T5	175722	1514	0	0
T14	34476	253	0	0
T15	1291	11	0	0
T16	741	2	0	0
T17	58583	666	0	0
T18	147125	339	0	0
T19	26442	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3522325	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3522325	0	0
T2	277876	4004	0	0
T3	33793	162	0	0
T4	348	9	0	0
T5	175722	1505	0	0
T14	34476	144	0	0
T15	1291	11	0	0
T16	741	2	0	0
T17	58583	626	0	0
T18	147125	225	0	0
T19	26442	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1471091	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1471091	0	0
T2	277876	2496	0	0
T3	33793	210	0	0
T4	348	6	0	0
T5	175722	1701	0	0
T14	34476	231	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	575	0	0
T18	147125	1141	0	0
T19	26442	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	4242856	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	4242856	0	0
T2	277876	1330	0	0
T3	33793	167	0	0
T4	348	6	0	0
T5	175722	1671	0	0
T14	34476	89	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	507	0	0
T18	147125	672	0	0
T19	26442	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1452349	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1452349	0	0
T1	57553	1611	0	0
T2	277876	3467	0	0
T3	33793	342	0	0
T4	348	5	0	0
T5	175722	1885	0	0
T14	34476	260	0	0
T15	1291	16	0	0
T16	741	5	0	0
T17	58583	448	0	0
T18	147125	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3739147	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3739147	0	0
T1	57553	1091	0	0
T2	277876	3333	0	0
T3	33793	213	0	0
T4	348	5	0	0
T5	175722	1764	0	0
T14	34476	92	0	0
T15	1291	16	0	0
T16	741	5	0	0
T17	58583	468	0	0
T18	147125	852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1482478	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1482478	0	0
T1	57553	4587	0	0
T2	277876	3445	0	0
T3	33793	216	0	0
T4	348	0	0	0
T5	175722	1769	0	0
T14	34476	223	0	0
T15	1291	15	0	0
T16	741	2	0	0
T17	58583	572	0	0
T18	147125	1661	0	0
T19	0	309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	2746578	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	2746578	0	0
T1	57553	2311	0	0
T2	277876	3146	0	0
T3	33793	211	0	0
T4	348	0	0	0
T5	175722	1718	0	0
T14	34476	78	0	0
T15	1291	15	0	0
T16	741	2	0	0
T17	58583	586	0	0
T18	147125	1746	0	0
T19	0	249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1500815	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1500815	0	0
T1	57553	2132	0	0
T2	277876	2777	0	0
T3	33793	268	0	0
T4	348	4	0	0
T5	175722	1680	0	0
T14	34476	300	0	0
T15	1291	17	0	0
T16	741	9	0	0
T17	58583	546	0	0
T18	147125	1003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3600727	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3600727	0	0
T1	57553	973	0	0
T2	277876	3678	0	0
T3	33793	236	0	0
T4	348	4	0	0
T5	175722	1734	0	0
T14	34476	94	0	0
T15	1291	17	0	0
T16	741	9	0	0
T17	58583	647	0	0
T18	147125	1964	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1485999	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1485999	0	0
T1	57553	2509	0	0
T2	277876	4799	0	0
T3	33793	207	0	0
T4	348	7	0	0
T5	175722	1549	0	0
T14	34476	353	0	0
T15	1291	13	0	0
T16	741	7	0	0
T17	58583	625	0	0
T18	147125	2188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	4817640	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	4817640	0	0
T1	57553	1268	0	0
T2	277876	4378	0	0
T3	33793	155	0	0
T4	348	7	0	0
T5	175722	1556	0	0
T14	34476	113	0	0
T15	1291	13	0	0
T16	741	7	0	0
T17	58583	603	0	0
T18	147125	1268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1467253	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1467253	0	0
T2	277876	1405	0	0
T3	33793	286	0	0
T4	348	2	0	0
T5	175722	1606	0	0
T14	34476	245	0	0
T15	1291	22	0	0
T16	741	4	0	0
T17	58583	577	0	0
T18	147125	0	0	0
T19	26442	117	0	0
T20	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3579415	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3579415	0	0
T2	277876	1131	0	0
T3	33793	217	0	0
T4	348	2	0	0
T5	175722	1774	0	0
T14	34476	101	0	0
T15	1291	22	0	0
T16	741	4	0	0
T17	58583	408	0	0
T18	147125	0	0	0
T19	26442	125	0	0
T20	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1553834	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1553834	0	0
T2	277876	1005	0	0
T3	33793	199	0	0
T4	348	6	0	0
T5	175722	1704	0	0
T14	34476	314	0	0
T15	1291	17	0	0
T16	741	2	0	0
T17	58583	827	0	0
T18	147125	242	0	0
T19	26442	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	4057780	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	4057780	0	0
T2	277876	2203	0	0
T3	33793	191	0	0
T4	348	6	0	0
T5	175722	1785	0	0
T14	34476	166	0	0
T15	1291	17	0	0
T16	741	2	0	0
T17	58583	583	0	0
T18	147125	1460	0	0
T19	26442	183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1524802	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1524802	0	0
T2	277876	727	0	0
T3	33793	208	0	0
T4	348	2	0	0
T5	175722	2007	0	0
T14	34476	250	0	0
T15	1291	18	0	0
T16	741	3	0	0
T17	58583	727	0	0
T18	147125	148	0	0
T19	26442	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3595478	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3595478	0	0
T2	277876	464	0	0
T3	33793	164	0	0
T4	348	2	0	0
T5	175722	2038	0	0
T14	34476	86	0	0
T15	1291	18	0	0
T16	741	3	0	0
T17	58583	621	0	0
T18	147125	313	0	0
T19	26442	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1485554	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1485554	0	0
T2	277876	1374	0	0
T3	33793	218	0	0
T4	348	2	0	0
T5	175722	1528	0	0
T14	34476	253	0	0
T15	1291	16	0	0
T16	741	2	0	0
T17	58583	458	0	0
T18	147125	2846	0	0
T19	26442	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3950874	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3950874	0	0
T2	277876	2502	0	0
T3	33793	209	0	0
T4	348	2	0	0
T5	175722	1635	0	0
T14	34476	109	0	0
T15	1291	16	0	0
T16	741	2	0	0
T17	58583	406	0	0
T18	147125	4235	0	0
T19	26442	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1489418	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1489418	0	0
T1	57553	969	0	0
T2	277876	4823	0	0
T3	33793	200	0	0
T4	348	4	0	0
T5	175722	1453	0	0
T14	34476	207	0	0
T15	1291	16	0	0
T16	741	0	0	0
T17	58583	609	0	0
T18	147125	1068	0	0
T19	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3729625	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3729625	0	0
T1	57553	1018	0	0
T2	277876	5556	0	0
T3	33793	197	0	0
T4	348	4	0	0
T5	175722	1431	0	0
T14	34476	125	0	0
T15	1291	16	0	0
T16	741	0	0	0
T17	58583	574	0	0
T18	147125	1106	0	0
T19	0	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1475431	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1475431	0	0
T2	277876	2702	0	0
T3	33793	244	0	0
T4	348	3	0	0
T5	175722	1836	0	0
T14	34476	239	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	618	0	0
T18	147125	2098	0	0
T19	26442	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3685964	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3685964	0	0
T2	277876	2578	0	0
T3	33793	192	0	0
T4	348	3	0	0
T5	175722	1886	0	0
T14	34476	125	0	0
T15	1291	17	0	0
T16	741	6	0	0
T17	58583	407	0	0
T18	147125	2184	0	0
T19	26442	167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1491957	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1491957	0	0
T2	277876	2700	0	0
T3	33793	217	0	0
T4	348	5	0	0
T5	175722	1449	0	0
T14	34476	292	0	0
T15	1291	16	0	0
T16	741	5	0	0
T17	58583	602	0	0
T18	147125	1508	0	0
T19	26442	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3771729	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3771729	0	0
T2	277876	3075	0	0
T3	33793	168	0	0
T4	348	5	0	0
T5	175722	1660	0	0
T14	34476	110	0	0
T15	1291	16	0	0
T16	741	5	0	0
T17	58583	466	0	0
T18	147125	1213	0	0
T19	26442	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1461711	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1461711	0	0
T2	277876	1041	0	0
T3	33793	193	0	0
T4	348	5	0	0
T5	175722	1884	0	0
T14	34476	402	0	0
T15	1291	20	0	0
T16	741	6	0	0
T17	58583	597	0	0
T18	147125	1333	0	0
T19	26442	140	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3326207	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3326207	0	0
T2	277876	862	0	0
T3	33793	164	0	0
T4	348	5	0	0
T5	175722	1638	0	0
T14	34476	185	0	0
T15	1291	20	0	0
T16	741	6	0	0
T17	58583	491	0	0
T18	147125	270	0	0
T19	26442	172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1539020	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1539020	0	0
T2	277876	4235	0	0
T3	33793	235	0	0
T4	348	7	0	0
T5	175722	1599	0	0
T14	34476	305	0	0
T15	1291	22	0	0
T16	741	1	0	0
T17	58583	634	0	0
T18	147125	1019	0	0
T19	26442	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3280536	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3280536	0	0
T2	277876	2878	0	0
T3	33793	168	0	0
T4	348	7	0	0
T5	175722	1698	0	0
T14	34476	107	0	0
T15	1291	22	0	0
T16	741	1	0	0
T17	58583	655	0	0
T18	147125	1596	0	0
T19	26442	173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1484238	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1484238	0	0
T2	277876	1984	0	0
T3	33793	288	0	0
T4	348	4	0	0
T5	175722	1384	0	0
T14	34476	328	0	0
T15	1291	19	0	0
T16	741	2	0	0
T17	58583	564	0	0
T18	147125	1743	0	0
T19	26442	264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3886105	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3886105	0	0
T2	277876	1527	0	0
T3	33793	185	0	0
T4	348	4	0	0
T5	175722	1527	0	0
T14	34476	130	0	0
T15	1291	19	0	0
T16	741	2	0	0
T17	58583	422	0	0
T18	147125	1825	0	0
T19	26442	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1495530	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1495530	0	0
T1	57553	1692	0	0
T2	277876	2801	0	0
T3	33793	281	0	0
T4	348	6	0	0
T5	175722	1620	0	0
T14	34476	193	0	0
T15	1291	24	0	0
T16	741	4	0	0
T17	58583	613	0	0
T18	147125	1775	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3664343	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3664343	0	0
T1	57553	1128	0	0
T2	277876	2796	0	0
T3	33793	177	0	0
T4	348	6	0	0
T5	175722	1556	0	0
T14	34476	111	0	0
T15	1291	24	0	0
T16	741	4	0	0
T17	58583	563	0	0
T18	147125	1465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1470177	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1470177	0	0
T2	277876	2258	0	0
T3	33793	194	0	0
T4	348	4	0	0
T5	175722	1339	0	0
T14	34476	334	0	0
T15	1291	16	0	0
T16	741	3	0	0
T17	58583	538	0	0
T18	147125	1566	0	0
T19	26442	193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3414693	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3414693	0	0
T2	277876	1861	0	0
T3	33793	187	0	0
T4	348	4	0	0
T5	175722	1520	0	0
T14	34476	125	0	0
T15	1291	16	0	0
T16	741	3	0	0
T17	58583	392	0	0
T18	147125	1715	0	0
T19	26442	155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1462004	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1462004	0	0
T2	277876	2578	0	0
T3	33793	151	0	0
T4	348	8	0	0
T5	175722	1910	0	0
T14	34476	200	0	0
T15	1291	35	0	0
T16	741	5	0	0
T17	58583	613	0	0
T18	147125	1598	0	0
T19	26442	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	4237714	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	4237714	0	0
T2	277876	2001	0	0
T3	33793	111	0	0
T4	348	8	0	0
T5	175722	1887	0	0
T14	34476	111	0	0
T15	1291	35	0	0
T16	741	5	0	0
T17	58583	532	0	0
T18	147125	1481	0	0
T19	26442	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1445690	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1445690	0	0
T2	277876	792	0	0
T3	33793	194	0	0
T4	348	3	0	0
T5	175722	1324	0	0
T14	34476	297	0	0
T15	1291	17	0	0
T16	741	1	0	0
T17	58583	667	0	0
T18	147125	1741	0	0
T19	26442	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	2653252	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	2653252	0	0
T2	277876	1256	0	0
T3	33793	150	0	0
T4	348	3	0	0
T5	175722	1419	0	0
T14	34476	180	0	0
T15	1291	17	0	0
T16	741	1	0	0
T17	58583	647	0	0
T18	147125	2033	0	0
T19	26442	153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1546377	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1546377	0	0
T2	277876	1830	0	0
T3	33793	244	0	0
T4	348	10	0	0
T5	175722	1655	0	0
T14	34476	232	0	0
T15	1291	20	0	0
T16	741	3	0	0
T17	58583	621	0	0
T18	147125	1813	0	0
T19	26442	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3752628	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3752628	0	0
T2	277876	917	0	0
T3	33793	230	0	0
T4	348	10	0	0
T5	175722	1554	0	0
T14	34476	117	0	0
T15	1291	20	0	0
T16	741	3	0	0
T17	58583	498	0	0
T18	147125	1294	0	0
T19	26442	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	1454960	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	1454960	0	0
T1	57553	3861	0	0
T2	277876	2032	0	0
T3	33793	228	0	0
T4	348	8	0	0
T5	175722	1885	0	0
T14	34476	473	0	0
T15	1291	18	0	0
T16	741	8	0	0
T17	58583	640	0	0
T18	147125	1565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329497270	3746602	0	0
DepthKnown_A	329497270	329369510	0	0
RvalidKnown_A	329497270	329369510	0	0
WreadyKnown_A	329497270	329369510	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	3746602	0	0
T1	57553	2854	0	0
T2	277876	3494	0	0
T3	33793	231	0	0
T4	348	8	0	0
T5	175722	1774	0	0
T14	34476	211	0	0
T15	1291	18	0	0
T16	741	8	0	0
T17	58583	615	0	0
T18	147125	1570	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329497270	329369510	0	0
T1	57553	57490	0	0
T2	277876	277788	0	0
T3	33793	33769	0	0
T4	348	341	0	0
T5	175722	175443	0	0
T14	34476	34426	0	0
T15	1291	1254	0	0
T16	741	674	0	0
T17	58583	58546	0	0
T18	147125	147113	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0