Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1673930	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262689

1

T1

12

T2

291

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	656327	1			T1	29		T2	685		T3	15
values[0x0]	623391	1			T1	8		T2	682		T3	3
values[0x1]	656901	1			T1	31		T2	716		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1297199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639420

1

T1

29

T2

720

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7629	1			T2	10		T14	32		T4	7
valid_sources[0x01]	7135	1			T2	5		T14	63		T15	3
valid_sources[0x02]	7383	1			T1	1		T2	6		T14	77
valid_sources[0x03]	6777	1			T2	6		T14	38		T4	6
valid_sources[0x04]	7192	1			T2	5		T14	38		T4	1
valid_sources[0x05]	8885	1			T1	1		T2	10		T14	21
valid_sources[0x06]	8322	1			T2	8		T3	1		T14	24
valid_sources[0x07]	6986	1			T2	10		T14	26		T4	4
valid_sources[0x08]	7019	1			T2	8		T14	26		T4	13
valid_sources[0x09]	6999	1			T2	5		T14	27		T4	4
valid_sources[0x0a]	6785	1			T2	7		T14	24		T4	4
valid_sources[0x0b]	7286	1			T2	4		T14	40		T4	3
valid_sources[0x0c]	6856	1			T1	2		T2	6		T14	32
valid_sources[0x0d]	8326	1			T2	4		T14	31		T4	6
valid_sources[0x0e]	6998	1			T2	6		T14	22		T4	2
valid_sources[0x0f]	6853	1			T2	7		T14	45		T4	2
valid_sources[0x10]	7180	1			T2	7		T14	35		T4	5
valid_sources[0x11]	7889	1			T2	9		T14	68		T4	4
valid_sources[0x12]	7291	1			T1	1		T2	8		T14	60
valid_sources[0x13]	7407	1			T1	2		T2	3		T14	25
valid_sources[0x14]	7573	1			T2	11		T14	51		T4	9
valid_sources[0x15]	7106	1			T2	10		T3	1		T14	26
valid_sources[0x16]	7224	1			T2	8		T14	36		T4	4
valid_sources[0x17]	7469	1			T2	18		T14	46		T4	8
valid_sources[0x18]	7285	1			T2	14		T14	24		T4	5
valid_sources[0x19]	7507	1			T2	9		T14	57		T4	5
valid_sources[0x1a]	7222	1			T1	1		T2	7		T14	33
valid_sources[0x1b]	7555	1			T2	12		T14	23		T4	15
valid_sources[0x1c]	7410	1			T2	13		T14	24		T4	4
valid_sources[0x1d]	8178	1			T2	7		T14	66		T4	10
valid_sources[0x1e]	7877	1			T2	9		T14	45		T4	5
valid_sources[0x1f]	7347	1			T2	8		T14	24		T4	8
valid_sources[0x20]	7656	1			T1	1		T2	12		T14	41
valid_sources[0x21]	7593	1			T2	9		T14	31		T4	2
valid_sources[0x22]	7446	1			T1	1		T2	8		T14	28
valid_sources[0x23]	6893	1			T1	1		T2	6		T14	32
valid_sources[0x24]	6608	1			T2	13		T14	36		T4	1
valid_sources[0x25]	8088	1			T2	4		T14	21		T15	5
valid_sources[0x26]	7753	1			T2	6		T14	35		T4	3
valid_sources[0x27]	7387	1			T1	1		T2	7		T14	40
valid_sources[0x28]	6861	1			T2	8		T14	23		T4	2
valid_sources[0x29]	7705	1			T2	9		T14	45		T4	2
valid_sources[0x2a]	7378	1			T2	12		T14	30		T4	3
valid_sources[0x2b]	6669	1			T2	13		T14	27		T4	2
valid_sources[0x2c]	7223	1			T2	6		T14	51		T4	1
valid_sources[0x2d]	8169	1			T1	2		T2	5		T14	23
valid_sources[0x2e]	7741	1			T2	11		T14	23		T15	10
valid_sources[0x2f]	7204	1			T2	8		T14	19		T4	11
valid_sources[0x30]	7678	1			T2	5		T14	39		T4	1
valid_sources[0x31]	7693	1			T2	6		T14	27		T4	4
valid_sources[0x32]	7397	1			T2	3		T14	41		T4	7
valid_sources[0x33]	7352	1			T2	8		T14	30		T4	8
valid_sources[0x34]	7525	1			T2	15		T14	27		T4	11
valid_sources[0x35]	7764	1			T2	10		T3	1		T14	24
valid_sources[0x36]	7083	1			T2	12		T14	46		T4	3
valid_sources[0x37]	7190	1			T1	1		T2	2		T14	28
valid_sources[0x38]	7413	1			T2	4		T14	24		T4	11
valid_sources[0x39]	8258	1			T1	1		T2	4		T14	33
valid_sources[0x3a]	8894	1			T14	41		T4	6		T15	18
valid_sources[0x3b]	8150	1			T1	1		T2	6		T14	68
valid_sources[0x3c]	6730	1			T2	11		T3	1		T14	46
valid_sources[0x3d]	7085	1			T2	7		T14	56		T4	5
valid_sources[0x3e]	7706	1			T1	1		T2	11		T14	27
valid_sources[0x3f]	7567	1			T2	5		T14	61		T4	2
valid_sources[0x40]	6906	1			T2	9		T14	25		T4	10
valid_sources[0x41]	7592	1			T2	9		T14	47		T4	12
valid_sources[0x42]	7797	1			T2	10		T14	29		T4	4
valid_sources[0x43]	8309	1			T2	6		T14	55		T4	3
valid_sources[0x44]	7588	1			T2	9		T14	24		T4	2
valid_sources[0x45]	7327	1			T2	5		T14	39		T4	8
valid_sources[0x46]	7857	1			T2	3		T14	56		T4	10
valid_sources[0x47]	7445	1			T2	3		T14	30		T4	13
valid_sources[0x48]	7167	1			T2	8		T14	25		T4	8
valid_sources[0x49]	7228	1			T2	6		T14	27		T4	7
valid_sources[0x4a]	7213	1			T2	7		T14	35		T15	10
valid_sources[0x4b]	7493	1			T2	11		T14	18		T4	5
valid_sources[0x4c]	9937	1			T2	2		T14	24		T4	5
valid_sources[0x4d]	8428	1			T1	1		T2	12		T14	28
valid_sources[0x4e]	7328	1			T2	8		T14	43		T4	7
valid_sources[0x4f]	8286	1			T2	7		T14	30		T4	2
valid_sources[0x50]	7746	1			T2	7		T14	38		T4	6
valid_sources[0x51]	8091	1			T2	13		T14	37		T4	2
valid_sources[0x52]	7672	1			T2	12		T14	35		T4	4
valid_sources[0x53]	7059	1			T1	1		T2	2		T14	37
valid_sources[0x54]	7489	1			T2	11		T14	22		T4	3
valid_sources[0x55]	6935	1			T2	9		T14	37		T4	1
valid_sources[0x56]	7586	1			T2	9		T14	53		T4	5
valid_sources[0x57]	6844	1			T2	6		T14	46		T4	5
valid_sources[0x58]	7739	1			T1	1		T2	8		T14	18
valid_sources[0x59]	7225	1			T2	8		T14	63		T4	4
valid_sources[0x5a]	7706	1			T2	10		T14	47		T4	6
valid_sources[0x5b]	7661	1			T2	11		T14	42		T4	12
valid_sources[0x5c]	7574	1			T1	1		T2	5		T3	1
valid_sources[0x5d]	7689	1			T2	8		T14	36		T4	2
valid_sources[0x5e]	8135	1			T1	3		T2	13		T14	27
valid_sources[0x5f]	8373	1			T2	11		T14	25		T4	10
valid_sources[0x60]	8032	1			T1	2		T2	15		T3	1
valid_sources[0x61]	7718	1			T2	9		T14	34		T4	3
valid_sources[0x62]	7486	1			T2	9		T14	30		T4	3
valid_sources[0x63]	8663	1			T1	1		T2	7		T14	32
valid_sources[0x64]	7604	1			T2	6		T14	26		T4	3
valid_sources[0x65]	7520	1			T2	2		T14	37		T15	11
valid_sources[0x66]	7519	1			T2	9		T14	47		T4	6
valid_sources[0x67]	7132	1			T2	4		T14	51		T4	12
valid_sources[0x68]	7658	1			T2	5		T14	54		T15	1
valid_sources[0x69]	8304	1			T1	1		T2	4		T14	50
valid_sources[0x6a]	7351	1			T1	1		T2	9		T14	26
valid_sources[0x6b]	7689	1			T2	7		T14	40		T4	4
valid_sources[0x6c]	7130	1			T1	1		T2	12		T3	1
valid_sources[0x6d]	7350	1			T2	13		T14	26		T4	3
valid_sources[0x6e]	6965	1			T2	11		T3	1		T14	45
valid_sources[0x6f]	7733	1			T2	7		T14	29		T4	6
valid_sources[0x70]	6980	1			T2	6		T14	51		T4	5
valid_sources[0x71]	7233	1			T2	6		T14	38		T4	5
valid_sources[0x72]	7183	1			T2	5		T14	25		T4	16
valid_sources[0x73]	7262	1			T2	12		T14	27		T4	2
valid_sources[0x74]	7374	1			T1	1		T2	14		T3	1
valid_sources[0x75]	7135	1			T2	12		T14	26		T4	4
valid_sources[0x76]	8555	1			T2	9		T14	36		T4	4
valid_sources[0x77]	6853	1			T1	1		T2	9		T14	31
valid_sources[0x78]	6864	1			T2	10		T14	35		T4	3
valid_sources[0x79]	7023	1			T2	4		T3	1		T14	29
valid_sources[0x7a]	7320	1			T2	4		T14	28		T4	9
valid_sources[0x7b]	7419	1			T2	9		T14	23		T4	4
valid_sources[0x7c]	7454	1			T2	5		T14	33		T4	3
valid_sources[0x7d]	7412	1			T1	2		T2	6		T14	47
valid_sources[0x7e]	6951	1			T1	2		T2	4		T14	80
valid_sources[0x7f]	7204	1			T2	17		T14	27		T4	7
valid_sources[0x80]	7281	1			T1	1		T2	3		T14	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27798

1

T1

4

T2

18

T3

2

values[0x0]

all_enables

biggest_size

206651

1

T1

4

T2

241

T3

1

values[0x1]

all_enables

biggest_size

28240

1

T1

4

T2

32

T14

134