Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	329087213	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329087213	0	0
T1	1508864	22347	0	0
T2	241416	8268	0	0
T3	754992	10518	0	0
T4	1784552	36606	0	0
T14	1029280	43329	0	0
T15	250040	10520	0	0
T16	2897440	67392	0	0
T17	296856	12240	0	0
T18	3052896	43915	0	0
T19	1280608	36562	0	0
T20	0	9870	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1508864	1505616	0	0
T2	241416	239456	0	0
T3	754992	749840	0	0
T4	1784552	1781024	0	0
T14	1029280	1024072	0	0
T15	250040	247912	0	0
T16	2897440	2895928	0	0
T17	296856	292712	0	0
T18	3052896	3048696	0	0
T19	1280608	1278536	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1508864	1505616	0	0
T2	241416	239456	0	0
T3	754992	749840	0	0
T4	1784552	1781024	0	0
T14	1029280	1024072	0	0
T15	250040	247912	0	0
T16	2897440	2895928	0	0
T17	296856	292712	0	0
T18	3052896	3048696	0	0
T19	1280608	1278536	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1508864	1505616	0	0
T2	241416	239456	0	0
T3	754992	749840	0	0
T4	1784552	1781024	0	0
T14	1029280	1024072	0	0
T15	250040	247912	0	0
T16	2897440	2895928	0	0
T17	296856	292712	0	0
T18	3052896	3048696	0	0
T19	1280608	1278536	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	120379334	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	120379334	0	0
T1	26944	10099	0	0
T2	4311	4081	0	0
T3	13482	4601	0	0
T4	31867	16586	0	0
T14	18380	17667	0	0
T15	4465	4094	0	0
T16	51740	27056	0	0
T17	5301	4761	0	0
T18	54516	10862	0	0
T19	22868	8925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	85926023	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	85926023	0	0
T1	26944	3584	0	0
T2	4311	2083	0	0
T3	13482	1700	0	0
T4	31867	4795	0	0
T14	18380	9388	0	0
T15	4465	2142	0	0
T16	51740	21298	0	0
T17	5301	2493	0	0
T18	54516	11124	0	0
T19	22868	9356	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1373184	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1373184	0	0
T1	26944	230	0	0
T2	4311	38	0	0
T3	13482	140	0	0
T4	31867	302	0	0
T14	18380	220	0	0
T15	4465	92	0	0
T16	51740	403	0	0
T17	5301	91	0	0
T18	54516	405	0	0
T19	22868	0	0	0
T20	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3309191	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3309191	0	0
T1	26944	119	0	0
T2	4311	38	0	0
T3	13482	73	0	0
T4	31867	162	0	0
T14	18380	220	0	0
T15	4465	92	0	0
T16	51740	351	0	0
T17	5301	91	0	0
T18	54516	403	0	0
T19	22868	0	0	0
T20	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1468325	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1468325	0	0
T1	26944	186	0	0
T2	4311	55	0	0
T3	13482	87	0	0
T4	31867	361	0	0
T14	18380	236	0	0
T15	4465	72	0	0
T16	51740	281	0	0
T17	5301	102	0	0
T18	54516	452	0	0
T19	22868	0	0	0
T20	0	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2404842	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2404842	0	0
T1	26944	166	0	0
T2	4311	55	0	0
T3	13482	45	0	0
T4	31867	165	0	0
T14	18380	236	0	0
T15	4465	72	0	0
T16	51740	310	0	0
T17	5301	102	0	0
T18	54516	454	0	0
T19	22868	0	0	0
T20	0	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1375310	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1375310	0	0
T1	26944	273	0	0
T2	4311	31	0	0
T3	13482	127	0	0
T4	31867	379	0	0
T14	18380	225	0	0
T15	4465	70	0	0
T16	51740	401	0	0
T17	5301	89	0	0
T18	54516	377	0	0
T19	22868	0	0	0
T20	0	296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2746133	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2746133	0	0
T1	26944	115	0	0
T2	4311	31	0	0
T3	13482	69	0	0
T4	31867	178	0	0
T14	18380	225	0	0
T15	4465	70	0	0
T16	51740	390	0	0
T17	5301	89	0	0
T18	54516	401	0	0
T19	22868	0	0	0
T20	0	214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1405921	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1405921	0	0
T1	26944	254	0	0
T2	4311	35	0	0
T3	13482	127	0	0
T4	31867	310	0	0
T14	18380	514	0	0
T15	4465	84	0	0
T16	51740	351	0	0
T17	5301	89	0	0
T18	54516	373	0	0
T19	22868	2145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3416083	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3416083	0	0
T1	26944	137	0	0
T2	4311	35	0	0
T3	13482	32	0	0
T4	31867	136	0	0
T14	18380	514	0	0
T15	4465	84	0	0
T16	51740	278	0	0
T17	5301	89	0	0
T18	54516	347	0	0
T19	22868	2366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1402852	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1402852	0	0
T1	26944	260	0	0
T2	4311	39	0	0
T3	13482	66	0	0
T4	31867	361	0	0
T14	18380	233	0	0
T15	4465	71	0	0
T16	51740	248	0	0
T17	5301	101	0	0
T18	54516	351	0	0
T19	22868	0	0	0
T20	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2817416	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2817416	0	0
T1	26944	103	0	0
T2	4311	39	0	0
T3	13482	42	0	0
T4	31867	208	0	0
T14	18380	233	0	0
T15	4465	71	0	0
T16	51740	289	0	0
T17	5301	101	0	0
T18	54516	379	0	0
T19	22868	0	0	0
T20	0	207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1422453	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1422453	0	0
T1	26944	302	0	0
T2	4311	35	0	0
T3	13482	38	0	0
T4	31867	415	0	0
T14	18380	493	0	0
T15	4465	79	0	0
T16	51740	320	0	0
T17	5301	86	0	0
T18	54516	440	0	0
T19	22868	0	0	0
T20	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	4016322	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	4016322	0	0
T1	26944	210	0	0
T2	4311	35	0	0
T3	13482	19	0	0
T4	31867	212	0	0
T14	18380	493	0	0
T15	4465	79	0	0
T16	51740	341	0	0
T17	5301	86	0	0
T18	54516	402	0	0
T19	22868	0	0	0
T20	0	157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1376755	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1376755	0	0
T1	26944	190	0	0
T2	4311	37	0	0
T3	13482	78	0	0
T4	31867	404	0	0
T14	18380	228	0	0
T15	4465	67	0	0
T16	51740	367	0	0
T17	5301	100	0	0
T18	54516	364	0	0
T19	22868	0	0	0
T20	0	150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3468256	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3468256	0	0
T1	26944	75	0	0
T2	4311	37	0	0
T3	13482	41	0	0
T4	31867	187	0	0
T14	18380	228	0	0
T15	4465	67	0	0
T16	51740	365	0	0
T17	5301	100	0	0
T18	54516	384	0	0
T19	22868	0	0	0
T20	0	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1449511	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1449511	0	0
T1	26944	160	0	0
T2	4311	39	0	0
T3	13482	85	0	0
T4	31867	373	0	0
T14	18380	473	0	0
T15	4465	90	0	0
T16	51740	284	0	0
T17	5301	78	0	0
T18	54516	402	0	0
T19	22868	0	0	0
T20	0	198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2664299	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2664299	0	0
T1	26944	39	0	0
T2	4311	39	0	0
T3	13482	67	0	0
T4	31867	180	0	0
T14	18380	473	0	0
T15	4465	90	0	0
T16	51740	299	0	0
T17	5301	78	0	0
T18	54516	440	0	0
T19	22868	0	0	0
T20	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1397849	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1397849	0	0
T1	26944	267	0	0
T2	4311	49	0	0
T3	13482	97	0	0
T4	31867	420	0	0
T14	18380	191	0	0
T15	4465	59	0	0
T16	51740	465	0	0
T17	5301	96	0	0
T18	54516	460	0	0
T19	22868	0	0	0
T20	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2897994	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2897994	0	0
T1	26944	111	0	0
T2	4311	49	0	0
T3	13482	56	0	0
T4	31867	150	0	0
T14	18380	191	0	0
T15	4465	59	0	0
T16	51740	396	0	0
T17	5301	96	0	0
T18	54516	439	0	0
T19	22868	0	0	0
T20	0	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1361940	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1361940	0	0
T1	26944	279	0	0
T2	4311	39	0	0
T3	13482	157	0	0
T4	31867	409	0	0
T14	18380	663	0	0
T15	4465	96	0	0
T16	51740	375	0	0
T17	5301	80	0	0
T18	54516	462	0	0
T19	22868	0	0	0
T20	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3639693	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3639693	0	0
T1	26944	118	0	0
T2	4311	39	0	0
T3	13482	50	0	0
T4	31867	221	0	0
T14	18380	663	0	0
T15	4465	96	0	0
T16	51740	375	0	0
T17	5301	80	0	0
T18	54516	398	0	0
T19	22868	0	0	0
T20	0	211	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1385285	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1385285	0	0
T1	26944	215	0	0
T2	4311	39	0	0
T3	13482	103	0	0
T4	31867	405	0	0
T14	18380	210	0	0
T15	4465	79	0	0
T16	51740	313	0	0
T17	5301	106	0	0
T18	54516	358	0	0
T19	22868	0	0	0
T20	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3302008	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3302008	0	0
T1	26944	111	0	0
T2	4311	39	0	0
T3	13482	20	0	0
T4	31867	169	0	0
T14	18380	210	0	0
T15	4465	79	0	0
T16	51740	340	0	0
T17	5301	106	0	0
T18	54516	386	0	0
T19	22868	0	0	0
T20	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1391066	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1391066	0	0
T1	26944	226	0	0
T2	4311	52	0	0
T3	13482	155	0	0
T4	31867	339	0	0
T14	18380	219	0	0
T15	4465	81	0	0
T16	51740	406	0	0
T17	5301	90	0	0
T18	54516	229	0	0
T19	22868	0	0	0
T20	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3198837	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3198837	0	0
T1	26944	120	0	0
T2	4311	52	0	0
T3	13482	91	0	0
T4	31867	128	0	0
T14	18380	219	0	0
T15	4465	81	0	0
T16	51740	474	0	0
T17	5301	90	0	0
T18	54516	307	0	0
T19	22868	0	0	0
T20	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1396747	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1396747	0	0
T1	26944	216	0	0
T2	4311	39	0	0
T3	13482	101	0	0
T4	31867	444	0	0
T14	18380	207	0	0
T15	4465	95	0	0
T16	51740	408	0	0
T17	5301	101	0	0
T18	54516	460	0	0
T19	22868	2266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3211961	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3211961	0	0
T1	26944	126	0	0
T2	4311	39	0	0
T3	13482	80	0	0
T4	31867	169	0	0
T14	18380	207	0	0
T15	4465	95	0	0
T16	51740	375	0	0
T17	5301	101	0	0
T18	54516	437	0	0
T19	22868	2477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1391817	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1391817	0	0
T1	26944	216	0	0
T2	4311	30	0	0
T3	13482	149	0	0
T4	31867	344	0	0
T14	18380	196	0	0
T15	4465	65	0	0
T16	51740	367	0	0
T17	5301	93	0	0
T18	54516	435	0	0
T19	22868	0	0	0
T20	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3485517	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3485517	0	0
T1	26944	75	0	0
T2	4311	30	0	0
T3	13482	35	0	0
T4	31867	188	0	0
T14	18380	196	0	0
T15	4465	65	0	0
T16	51740	353	0	0
T17	5301	93	0	0
T18	54516	452	0	0
T19	22868	0	0	0
T20	0	233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1406124	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1406124	0	0
T1	26944	228	0	0
T2	4311	42	0	0
T3	13482	110	0	0
T4	31867	296	0	0
T14	18380	228	0	0
T15	4465	80	0	0
T16	51740	446	0	0
T17	5301	103	0	0
T18	54516	473	0	0
T19	22868	0	0	0
T20	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2947315	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2947315	0	0
T1	26944	93	0	0
T2	4311	42	0	0
T3	13482	71	0	0
T4	31867	114	0	0
T14	18380	228	0	0
T15	4465	80	0	0
T16	51740	422	0	0
T17	5301	103	0	0
T18	54516	420	0	0
T19	22868	0	0	0
T20	0	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1382302	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1382302	0	0
T1	26944	196	0	0
T2	4311	33	0	0
T3	13482	57	0	0
T4	31867	335	0	0
T14	18380	202	0	0
T15	4465	84	0	0
T16	51740	306	0	0
T17	5301	94	0	0
T18	54516	410	0	0
T19	22868	0	0	0
T20	0	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2597108	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2597108	0	0
T1	26944	109	0	0
T2	4311	33	0	0
T3	13482	20	0	0
T4	31867	211	0	0
T14	18380	202	0	0
T15	4465	84	0	0
T16	51740	380	0	0
T17	5301	94	0	0
T18	54516	331	0	0
T19	22868	0	0	0
T20	0	235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1439209	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1439209	0	0
T1	26944	147	0	0
T2	4311	39	0	0
T3	13482	127	0	0
T4	31867	476	0	0
T14	18380	472	0	0
T15	4465	80	0	0
T16	51740	364	0	0
T17	5301	103	0	0
T18	54516	438	0	0
T19	22868	0	0	0
T20	0	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2992787	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2992787	0	0
T1	26944	44	0	0
T2	4311	39	0	0
T3	13482	52	0	0
T4	31867	206	0	0
T14	18380	472	0	0
T15	4465	80	0	0
T16	51740	392	0	0
T17	5301	103	0	0
T18	54516	498	0	0
T19	22868	0	0	0
T20	0	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1394354	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1394354	0	0
T1	26944	160	0	0
T2	4311	31	0	0
T3	13482	137	0	0
T4	31867	495	0	0
T14	18380	199	0	0
T15	4465	76	0	0
T16	51740	466	0	0
T17	5301	90	0	0
T18	54516	372	0	0
T19	22868	0	0	0
T20	0	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3668983	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3668983	0	0
T1	26944	62	0	0
T2	4311	31	0	0
T3	13482	51	0	0
T4	31867	183	0	0
T14	18380	199	0	0
T15	4465	76	0	0
T16	51740	384	0	0
T17	5301	90	0	0
T18	54516	390	0	0
T19	22868	0	0	0
T20	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1405187	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1405187	0	0
T1	26944	233	0	0
T2	4311	43	0	0
T3	13482	121	0	0
T4	31867	498	0	0
T14	18380	508	0	0
T15	4465	76	0	0
T16	51740	334	0	0
T17	5301	68	0	0
T18	54516	266	0	0
T19	22868	0	0	0
T20	0	200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3692627	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3692627	0	0
T1	26944	127	0	0
T2	4311	43	0	0
T3	13482	38	0	0
T4	31867	174	0	0
T14	18380	508	0	0
T15	4465	76	0	0
T16	51740	319	0	0
T17	5301	68	0	0
T18	54516	336	0	0
T19	22868	0	0	0
T20	0	218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1384039	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1384039	0	0
T1	26944	117	0	0
T2	4311	31	0	0
T3	13482	69	0	0
T4	31867	357	0	0
T14	18380	429	0	0
T15	4465	84	0	0
T16	51740	398	0	0
T17	5301	82	0	0
T18	54516	357	0	0
T19	22868	0	0	0
T20	0	296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2946925	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2946925	0	0
T1	26944	71	0	0
T2	4311	31	0	0
T3	13482	35	0	0
T4	31867	155	0	0
T14	18380	429	0	0
T15	4465	84	0	0
T16	51740	383	0	0
T17	5301	82	0	0
T18	54516	382	0	0
T19	22868	0	0	0
T20	0	277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1456797	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1456797	0	0
T1	26944	144	0	0
T2	4311	39	0	0
T3	13482	104	0	0
T4	31867	379	0	0
T14	18380	238	0	0
T15	4465	76	0	0
T16	51740	349	0	0
T17	5301	86	0	0
T18	54516	425	0	0
T19	22868	0	0	0
T20	0	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3157735	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3157735	0	0
T1	26944	61	0	0
T2	4311	39	0	0
T3	13482	53	0	0
T4	31867	219	0	0
T14	18380	238	0	0
T15	4465	76	0	0
T16	51740	386	0	0
T17	5301	86	0	0
T18	54516	460	0	0
T19	22868	0	0	0
T20	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1384446	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1384446	0	0
T1	26944	221	0	0
T2	4311	35	0	0
T3	13482	92	0	0
T4	31867	407	0	0
T14	18380	246	0	0
T15	4465	70	0	0
T16	51740	382	0	0
T17	5301	86	0	0
T18	54516	359	0	0
T19	22868	0	0	0
T20	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3492410	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3492410	0	0
T1	26944	111	0	0
T2	4311	35	0	0
T3	13482	62	0	0
T4	31867	260	0	0
T14	18380	246	0	0
T15	4465	70	0	0
T16	51740	434	0	0
T17	5301	86	0	0
T18	54516	317	0	0
T19	22868	0	0	0
T20	0	291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1451791	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1451791	0	0
T1	26944	142	0	0
T2	4311	46	0	0
T3	13482	136	0	0
T4	31867	457	0	0
T14	18380	185	0	0
T15	4465	74	0	0
T16	51740	207	0	0
T17	5301	81	0	0
T18	54516	480	0	0
T19	22868	2390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3555211	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3555211	0	0
T1	26944	78	0	0
T2	4311	46	0	0
T3	13482	26	0	0
T4	31867	156	0	0
T14	18380	185	0	0
T15	4465	74	0	0
T16	51740	204	0	0
T17	5301	81	0	0
T18	54516	553	0	0
T19	22868	2380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1385682	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1385682	0	0
T1	26944	224	0	0
T2	4311	41	0	0
T3	13482	100	0	0
T4	31867	270	0	0
T14	18380	194	0	0
T15	4465	102	0	0
T16	51740	307	0	0
T17	5301	86	0	0
T18	54516	443	0	0
T19	22868	2124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2916275	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2916275	0	0
T1	26944	110	0	0
T2	4311	41	0	0
T3	13482	70	0	0
T4	31867	141	0	0
T14	18380	194	0	0
T15	4465	102	0	0
T16	51740	344	0	0
T17	5301	86	0	0
T18	54516	441	0	0
T19	22868	2133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1406606	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1406606	0	0
T1	26944	248	0	0
T2	4311	38	0	0
T3	13482	119	0	0
T4	31867	359	0	0
T14	18380	213	0	0
T15	4465	77	0	0
T16	51740	409	0	0
T17	5301	99	0	0
T18	54516	506	0	0
T19	22868	0	0	0
T20	0	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	3228781	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	3228781	0	0
T1	26944	109	0	0
T2	4311	38	0	0
T3	13482	47	0	0
T4	31867	192	0	0
T14	18380	213	0	0
T15	4465	77	0	0
T16	51740	363	0	0
T17	5301	99	0	0
T18	54516	513	0	0
T19	22868	0	0	0
T20	0	195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1364952	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1364952	0	0
T1	26944	286	0	0
T2	4311	43	0	0
T3	13482	92	0	0
T4	31867	409	0	0
T14	18380	492	0	0
T15	4465	82	0	0
T16	51740	293	0	0
T17	5301	106	0	0
T18	54516	403	0	0
T19	22868	0	0	0
T20	0	204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2450628	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2450628	0	0
T1	26944	133	0	0
T2	4311	43	0	0
T3	13482	50	0	0
T4	31867	139	0	0
T14	18380	492	0	0
T15	4465	82	0	0
T16	51740	265	0	0
T17	5301	106	0	0
T18	54516	408	0	0
T19	22868	0	0	0
T20	0	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	1374665	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	1374665	0	0
T1	26944	245	0	0
T2	4311	34	0	0
T3	13482	97	0	0
T4	31867	426	0	0
T14	18380	223	0	0
T15	4465	81	0	0
T16	51740	271	0	0
T17	5301	107	0	0
T18	54516	354	0	0
T19	22868	0	0	0
T20	0	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302133300	2721350	0	0
DepthKnown_A	302133300	302005662	0	0
RvalidKnown_A	302133300	302005662	0	0
WreadyKnown_A	302133300	302005662	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	2721350	0	0
T1	26944	66	0	0
T2	4311	34	0	0
T3	13482	51	0	0
T4	31867	192	0	0
T14	18380	223	0	0
T15	4465	81	0	0
T16	51740	305	0	0
T17	5301	107	0	0
T18	54516	397	0	0
T19	22868	0	0	0
T20	0	250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302133300	302005662	0	0
T1	26944	26886	0	0
T2	4311	4276	0	0
T3	13482	13390	0	0
T4	31867	31804	0	0
T14	18380	18287	0	0
T15	4465	4427	0	0
T16	51740	51713	0	0
T17	5301	5227	0	0
T18	54516	54441	0	0
T19	22868	22831	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0