Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1607544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253463

1

T1

181

T2

12

T3

884

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628081	1			T1	409		T2	38		T3	2255
values[0x0]	604030	1			T1	457		T2	40		T3	2154
values[0x1]	628896	1			T1	407		T2	43		T3	2236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1246175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

614832

1

T1

406

T2

39

T3

2190

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6553	1			T1	7		T3	52		T10	4
valid_sources[0x01]	8092	1			T1	5		T3	6		T11	7
valid_sources[0x02]	7469	1			T1	6		T3	43		T11	17
valid_sources[0x03]	8064	1			T1	3		T3	16		T11	11
valid_sources[0x04]	7620	1			T1	8		T3	24		T10	1
valid_sources[0x05]	7363	1			T1	10		T3	27		T15	18
valid_sources[0x06]	6794	1			T1	6		T3	9		T10	1
valid_sources[0x07]	7840	1			T1	1		T3	14		T10	1
valid_sources[0x08]	7642	1			T1	2		T3	28		T11	11
valid_sources[0x09]	7422	1			T1	3		T3	16		T10	3
valid_sources[0x0a]	6885	1			T1	8		T3	18		T10	4
valid_sources[0x0b]	6410	1			T1	8		T3	19		T11	10
valid_sources[0x0c]	7139	1			T1	2		T3	83		T11	5
valid_sources[0x0d]	6602	1			T1	5		T3	17		T10	1
valid_sources[0x0e]	7565	1			T1	9		T3	9		T10	3
valid_sources[0x0f]	6947	1			T1	10		T3	63		T10	8
valid_sources[0x10]	6985	1			T1	3		T3	12		T10	8
valid_sources[0x11]	6998	1			T1	10		T3	2		T11	11
valid_sources[0x12]	8077	1			T1	9		T3	16		T11	17
valid_sources[0x13]	7122	1			T1	4		T3	19		T10	2
valid_sources[0x14]	6850	1			T1	8		T3	40		T10	7
valid_sources[0x15]	7254	1			T1	12		T3	10		T10	2
valid_sources[0x16]	9666	1			T1	1		T3	7		T11	18
valid_sources[0x17]	8405	1			T1	6		T3	22		T10	2
valid_sources[0x18]	6994	1			T1	7		T3	30		T10	7
valid_sources[0x19]	7141	1			T1	5		T3	11		T11	14
valid_sources[0x1a]	7035	1			T1	7		T3	12		T10	2
valid_sources[0x1b]	7338	1			T1	2		T3	32		T10	3
valid_sources[0x1c]	7882	1			T1	8		T3	24		T10	1
valid_sources[0x1d]	6825	1			T1	4		T3	24		T11	16
valid_sources[0x1e]	7600	1			T1	3		T3	16		T10	1
valid_sources[0x1f]	7181	1			T1	1		T3	3		T10	1
valid_sources[0x20]	6924	1			T1	11		T3	74		T10	3
valid_sources[0x21]	7732	1			T1	5		T3	9		T10	10
valid_sources[0x22]	7118	1			T1	6		T3	7		T15	20
valid_sources[0x23]	7932	1			T1	2		T3	12		T10	2
valid_sources[0x24]	6221	1			T1	4		T3	3		T10	3
valid_sources[0x25]	6684	1			T1	9		T3	27		T10	2
valid_sources[0x26]	7571	1			T1	7		T3	41		T11	5
valid_sources[0x27]	6964	1			T1	3		T3	7		T15	18
valid_sources[0x28]	6790	1			T1	1		T3	6		T10	4
valid_sources[0x29]	7527	1			T1	4		T3	12		T11	7
valid_sources[0x2a]	6918	1			T1	5		T3	21		T10	1
valid_sources[0x2b]	7079	1			T1	6		T3	9		T10	2
valid_sources[0x2c]	7086	1			T3	31		T15	21		T8	27
valid_sources[0x2d]	7419	1			T3	17		T10	5		T15	18
valid_sources[0x2e]	7018	1			T1	2		T3	58		T15	20
valid_sources[0x2f]	8545	1			T1	7		T3	11		T10	3
valid_sources[0x30]	6615	1			T1	6		T3	11		T10	2
valid_sources[0x31]	7081	1			T1	5		T3	11		T15	19
valid_sources[0x32]	6813	1			T1	3		T3	8		T10	2
valid_sources[0x33]	6867	1			T1	6		T3	48		T10	4
valid_sources[0x34]	7039	1			T1	5		T3	6		T11	11
valid_sources[0x35]	7174	1			T1	5		T3	10		T10	4
valid_sources[0x36]	6857	1			T1	3		T15	19		T8	11
valid_sources[0x37]	6567	1			T1	2		T3	42		T10	7
valid_sources[0x38]	7034	1			T1	9		T3	29		T10	1
valid_sources[0x39]	8192	1			T1	4		T3	20		T11	16
valid_sources[0x3a]	7056	1			T1	3		T3	28		T10	4
valid_sources[0x3b]	8115	1			T1	3		T3	21		T10	4
valid_sources[0x3c]	7260	1			T1	7		T3	13		T10	3
valid_sources[0x3d]	6659	1			T1	3		T3	25		T10	2
valid_sources[0x3e]	6786	1			T1	10		T3	3		T10	2
valid_sources[0x3f]	6456	1			T1	5		T2	61		T3	10
valid_sources[0x40]	6837	1			T1	13		T3	3		T10	6
valid_sources[0x41]	7897	1			T1	3		T3	22		T11	9
valid_sources[0x42]	7651	1			T1	5		T3	40		T11	11
valid_sources[0x43]	7091	1			T1	4		T3	16		T11	15
valid_sources[0x44]	8016	1			T1	7		T3	20		T12	17
valid_sources[0x45]	8094	1			T1	6		T3	19		T11	8
valid_sources[0x46]	6936	1			T1	8		T3	16		T10	3
valid_sources[0x47]	7623	1			T1	7		T3	2		T10	5
valid_sources[0x48]	8026	1			T1	3		T3	12		T10	6
valid_sources[0x49]	7697	1			T1	3		T3	59		T10	8
valid_sources[0x4a]	7463	1			T1	5		T3	19		T10	6
valid_sources[0x4b]	7212	1			T1	4		T3	88		T10	11
valid_sources[0x4c]	7651	1			T1	7		T3	11		T15	18
valid_sources[0x4d]	8939	1			T1	4		T3	22		T10	1
valid_sources[0x4e]	7229	1			T1	5		T3	21		T10	2
valid_sources[0x4f]	6934	1			T1	5		T3	44		T4	3
valid_sources[0x50]	8005	1			T1	6		T3	9		T10	1
valid_sources[0x51]	7220	1			T1	6		T3	8		T10	3
valid_sources[0x52]	6837	1			T1	6		T3	8		T10	6
valid_sources[0x53]	7253	1			T1	7		T3	69		T15	18
valid_sources[0x54]	7157	1			T1	6		T3	53		T10	5
valid_sources[0x55]	7377	1			T1	9		T3	9		T15	20
valid_sources[0x56]	7318	1			T1	4		T3	4		T11	13
valid_sources[0x57]	7213	1			T1	4		T3	23		T10	2
valid_sources[0x58]	7053	1			T1	6		T3	53		T10	5
valid_sources[0x59]	7281	1			T1	5		T3	13		T12	7
valid_sources[0x5a]	7028	1			T1	2		T3	45		T10	1
valid_sources[0x5b]	7593	1			T1	1		T3	3		T10	6
valid_sources[0x5c]	6788	1			T1	4		T3	31		T10	4
valid_sources[0x5d]	6957	1			T1	4		T3	44		T15	19
valid_sources[0x5e]	8098	1			T1	5		T3	8		T10	1
valid_sources[0x5f]	7066	1			T1	7		T3	7		T11	7
valid_sources[0x60]	7159	1			T1	2		T3	26		T10	1
valid_sources[0x61]	7293	1			T1	3		T3	14		T10	4
valid_sources[0x62]	8567	1			T1	3		T3	7		T10	3
valid_sources[0x63]	7549	1			T1	8		T3	1		T10	5
valid_sources[0x64]	7113	1			T1	3		T3	16		T10	6
valid_sources[0x65]	7409	1			T1	7		T3	28		T10	4
valid_sources[0x66]	7291	1			T1	5		T3	28		T11	13
valid_sources[0x67]	7276	1			T1	5		T3	40		T15	20
valid_sources[0x68]	6926	1			T1	4		T3	5		T10	4
valid_sources[0x69]	7548	1			T1	6		T3	46		T10	2
valid_sources[0x6a]	7405	1			T1	1		T3	31		T13	86
valid_sources[0x6b]	6998	1			T1	7		T3	5		T10	3
valid_sources[0x6c]	8138	1			T1	5		T3	4		T15	19
valid_sources[0x6d]	8202	1			T1	1		T3	1		T12	10
valid_sources[0x6e]	6710	1			T1	4		T3	8		T10	2
valid_sources[0x6f]	6607	1			T1	6		T3	11		T15	19
valid_sources[0x70]	6335	1			T1	5		T3	50		T10	1
valid_sources[0x71]	6940	1			T1	5		T3	21		T10	3
valid_sources[0x72]	6801	1			T1	5		T3	57		T11	8
valid_sources[0x73]	6747	1			T1	4		T3	27		T15	19
valid_sources[0x74]	7018	1			T1	1		T3	23		T10	3
valid_sources[0x75]	7630	1			T1	4		T3	52		T15	20
valid_sources[0x76]	6902	1			T1	16		T3	35		T10	4
valid_sources[0x77]	6959	1			T1	7		T3	59		T10	3
valid_sources[0x78]	7547	1			T1	2		T3	26		T10	3
valid_sources[0x79]	7265	1			T1	4		T3	94		T15	16
valid_sources[0x7a]	7682	1			T1	7		T3	17		T15	17
valid_sources[0x7b]	7333	1			T1	3		T3	8		T10	1
valid_sources[0x7c]	7490	1			T1	4		T3	21		T11	9
valid_sources[0x7d]	7220	1			T1	9		T3	23		T10	5
valid_sources[0x7e]	6583	1			T1	6		T3	5		T15	19
valid_sources[0x7f]	7607	1			T1	8		T3	49		T10	5
valid_sources[0x80]	7020	1			T1	7		T3	22		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26493

1

T1

12

T3

92

T11

5

values[0x0]

all_enables

biggest_size

200611

1

T1

159

T2

11

T3

702

values[0x1]

all_enables

biggest_size

26359

1

T1

10

T2

1

T3

90