Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	326539020	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	326539020	0	0
T1	156408	6256	0	0
T2	23968	597	0	0
T3	8292592	164715	0	0
T4	5248824	175814	0	0
T8	0	5064	0	0
T10	101024	3127	0	0
T11	118216	3120	0	0
T12	91056	3094	0	0
T13	43960	849	0	0
T14	42504	609	0	0
T15	22659336	1912713	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	156408	153440	0	0
T2	23968	22456	0	0
T3	8292592	8250928	0	0
T4	5248824	5244960	0	0
T10	101024	99680	0	0
T11	118216	113960	0	0
T12	91056	90608	0	0
T13	43960	41552	0	0
T14	42504	38864	0	0
T15	22659336	22659280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	156408	153440	0	0
T2	23968	22456	0	0
T3	8292592	8250928	0	0
T4	5248824	5244960	0	0
T10	101024	99680	0	0
T11	118216	113960	0	0
T12	91056	90608	0	0
T13	43960	41552	0	0
T14	42504	38864	0	0
T15	22659336	22659280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	156408	153440	0	0
T2	23968	22456	0	0
T3	8292592	8250928	0	0
T4	5248824	5244960	0	0
T10	101024	99680	0	0
T11	118216	113960	0	0
T12	91056	90608	0	0
T13	43960	41552	0	0
T14	42504	38864	0	0
T15	22659336	22659280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	124028472	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	124028472	0	0
T1	2793	2437	0	0
T2	428	234	0	0
T3	148082	62844	0	0
T4	93729	92470	0	0
T10	1804	1533	0	0
T11	2111	782	0	0
T12	1626	774	0	0
T13	785	333	0	0
T14	759	237	0	0
T15	404631	21658	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	82326570	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	82326570	0	0
T1	2793	1273	0	0
T2	428	121	0	0
T3	148082	25422	0	0
T4	93729	41457	0	0
T10	1804	784	0	0
T11	2111	782	0	0
T12	1626	774	0	0
T13	785	172	0	0
T14	759	124	0	0
T15	404631	169961	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1385380	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1385380	0	0
T1	2793	33	0	0
T2	428	3	0	0
T3	148082	2485	0	0
T4	93729	13	0	0
T10	1804	20	0	0
T11	2111	30	0	0
T12	1626	35	0	0
T13	785	10	0	0
T14	759	4	0	0
T15	404631	925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2565814	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2565814	0	0
T1	2793	33	0	0
T2	428	3	0	0
T3	148082	1263	0	0
T4	93729	2203	0	0
T10	1804	20	0	0
T11	2111	30	0	0
T12	1626	35	0	0
T13	785	10	0	0
T14	759	4	0	0
T15	404631	67686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1413569	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1413569	0	0
T1	2793	42	0	0
T2	428	8	0	0
T3	148082	604	0	0
T4	93729	16	0	0
T10	1804	18	0	0
T11	2111	25	0	0
T12	1626	34	0	0
T13	785	6	0	0
T14	759	4	0	0
T15	404631	1152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2895178	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2895178	0	0
T1	2793	42	0	0
T2	428	8	0	0
T3	148082	311	0	0
T4	93729	733	0	0
T10	1804	18	0	0
T11	2111	25	0	0
T12	1626	34	0	0
T13	785	6	0	0
T14	759	4	0	0
T15	404631	87757	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1461954	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1461954	0	0
T1	2793	43	0	0
T2	428	1	0	0
T3	148082	2276	0	0
T4	93729	6	0	0
T10	1804	10	0	0
T11	2111	34	0	0
T12	1626	19	0	0
T13	785	5	0	0
T14	759	3	0	0
T15	404631	2292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3420515	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3420515	0	0
T1	2793	43	0	0
T2	428	1	0	0
T3	148082	1032	0	0
T4	93729	1755	0	0
T10	1804	10	0	0
T11	2111	34	0	0
T12	1626	19	0	0
T13	785	5	0	0
T14	759	3	0	0
T15	404631	185959	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1397293	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1397293	0	0
T1	2793	47	0	0
T2	428	6	0	0
T3	148082	548	0	0
T4	93729	4	0	0
T8	0	161	0	0
T10	1804	14	0	0
T11	2111	39	0	0
T12	1626	31	0	0
T13	785	7	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2751997	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2751997	0	0
T1	2793	47	0	0
T2	428	6	0	0
T3	148082	234	0	0
T4	93729	798	0	0
T8	0	161	0	0
T10	1804	14	0	0
T11	2111	39	0	0
T12	1626	31	0	0
T13	785	7	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1399601	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1399601	0	0
T1	2793	46	0	0
T2	428	4	0	0
T3	148082	761	0	0
T4	93729	8	0	0
T10	1804	12	0	0
T11	2111	28	0	0
T12	1626	30	0	0
T13	785	8	0	0
T14	759	9	0	0
T15	404631	2150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3119472	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3119472	0	0
T1	2793	46	0	0
T2	428	4	0	0
T3	148082	279	0	0
T4	93729	1070	0	0
T10	1804	12	0	0
T11	2111	28	0	0
T12	1626	30	0	0
T13	785	8	0	0
T14	759	9	0	0
T15	404631	167897	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1428347	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1428347	0	0
T1	2793	36	0	0
T2	428	5	0	0
T3	148082	3082	0	0
T4	93729	18	0	0
T8	0	156	0	0
T10	1804	12	0	0
T11	2111	37	0	0
T12	1626	24	0	0
T13	785	8	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2752605	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2752605	0	0
T1	2793	36	0	0
T2	428	5	0	0
T3	148082	1463	0	0
T4	93729	1026	0	0
T8	0	156	0	0
T10	1804	12	0	0
T11	2111	37	0	0
T12	1626	24	0	0
T13	785	8	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1400984	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1400984	0	0
T1	2793	48	0	0
T2	428	6	0	0
T3	148082	630	0	0
T4	93729	18	0	0
T8	0	165	0	0
T10	1804	15	0	0
T11	2111	28	0	0
T12	1626	25	0	0
T13	785	10	0	0
T14	759	3	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2599637	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2599637	0	0
T1	2793	48	0	0
T2	428	6	0	0
T3	148082	322	0	0
T4	93729	2604	0	0
T8	0	165	0	0
T10	1804	15	0	0
T11	2111	28	0	0
T12	1626	25	0	0
T13	785	10	0	0
T14	759	3	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1419729	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1419729	0	0
T1	2793	47	0	0
T2	428	7	0	0
T3	148082	568	0	0
T4	93729	8	0	0
T10	1804	18	0	0
T11	2111	22	0	0
T12	1626	26	0	0
T13	785	10	0	0
T14	759	8	0	0
T15	404631	984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3197930	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3197930	0	0
T1	2793	47	0	0
T2	428	7	0	0
T3	148082	244	0	0
T4	93729	444	0	0
T10	1804	18	0	0
T11	2111	22	0	0
T12	1626	26	0	0
T13	785	10	0	0
T14	759	8	0	0
T15	404631	83725	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1462122	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1462122	0	0
T1	2793	53	0	0
T2	428	1	0	0
T3	148082	3002	0	0
T4	93729	39	0	0
T8	0	167	0	0
T10	1804	16	0	0
T11	2111	23	0	0
T12	1626	41	0	0
T13	785	0	0	0
T14	759	2	0	0
T15	404631	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3499027	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3499027	0	0
T1	2793	53	0	0
T2	428	1	0	0
T3	148082	1277	0	0
T4	93729	1620	0	0
T8	0	167	0	0
T10	1804	16	0	0
T11	2111	23	0	0
T12	1626	41	0	0
T13	785	0	0	0
T14	759	2	0	0
T15	404631	81042	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1396100	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1396100	0	0
T1	2793	50	0	0
T2	428	6	0	0
T3	148082	3373	0	0
T4	93729	10	0	0
T8	0	152	0	0
T10	1804	15	0	0
T11	2111	32	0	0
T12	1626	26	0	0
T13	785	6	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3169843	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3169843	0	0
T1	2793	50	0	0
T2	428	6	0	0
T3	148082	1462	0	0
T4	93729	820	0	0
T8	0	152	0	0
T10	1804	15	0	0
T11	2111	32	0	0
T12	1626	26	0	0
T13	785	6	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1432078	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1432078	0	0
T1	2793	55	0	0
T2	428	4	0	0
T3	148082	984	0	0
T4	93729	10	0	0
T8	0	168	0	0
T10	1804	9	0	0
T11	2111	25	0	0
T12	1626	34	0	0
T13	785	4	0	0
T14	759	5	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3431488	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3431488	0	0
T1	2793	55	0	0
T2	428	4	0	0
T3	148082	405	0	0
T4	93729	538	0	0
T8	0	168	0	0
T10	1804	9	0	0
T11	2111	25	0	0
T12	1626	34	0	0
T13	785	4	0	0
T14	759	5	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1480023	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1480023	0	0
T1	2793	58	0	0
T2	428	3	0	0
T3	148082	6738	0	0
T4	93729	28	0	0
T8	0	187	0	0
T10	1804	9	0	0
T11	2111	35	0	0
T12	1626	30	0	0
T13	785	8	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3024470	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3024470	0	0
T1	2793	58	0	0
T2	428	3	0	0
T3	148082	3306	0	0
T4	93729	2862	0	0
T8	0	187	0	0
T10	1804	9	0	0
T11	2111	35	0	0
T12	1626	30	0	0
T13	785	8	0	0
T14	759	1	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1454238	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1454238	0	0
T1	2793	51	0	0
T2	428	6	0	0
T3	148082	2556	0	0
T4	93729	10	0	0
T8	0	142	0	0
T10	1804	16	0	0
T11	2111	23	0	0
T12	1626	38	0	0
T13	785	5	0	0
T14	759	9	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2171059	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2171059	0	0
T1	2793	51	0	0
T2	428	6	0	0
T3	148082	1355	0	0
T4	93729	1159	0	0
T8	0	142	0	0
T10	1804	16	0	0
T11	2111	23	0	0
T12	1626	38	0	0
T13	785	5	0	0
T14	759	9	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1469742	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1469742	0	0
T1	2793	59	0	0
T2	428	6	0	0
T3	148082	2761	0	0
T4	93729	29	0	0
T8	0	421	0	0
T10	1804	15	0	0
T11	2111	34	0	0
T12	1626	30	0	0
T13	785	4	0	0
T14	759	2	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3228477	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3228477	0	0
T1	2793	59	0	0
T2	428	6	0	0
T3	148082	1365	0	0
T4	93729	3125	0	0
T8	0	421	0	0
T10	1804	15	0	0
T11	2111	34	0	0
T12	1626	30	0	0
T13	785	4	0	0
T14	759	2	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1433592	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1433592	0	0
T1	2793	51	0	0
T2	428	1	0	0
T3	148082	697	0	0
T4	93729	22	0	0
T8	0	169	0	0
T10	1804	13	0	0
T11	2111	27	0	0
T12	1626	30	0	0
T13	785	5	0	0
T14	759	4	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3269917	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3269917	0	0
T1	2793	51	0	0
T2	428	1	0	0
T3	148082	392	0	0
T4	93729	3541	0	0
T8	0	169	0	0
T10	1804	13	0	0
T11	2111	27	0	0
T12	1626	30	0	0
T13	785	5	0	0
T14	759	4	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1450703	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1450703	0	0
T1	2793	36	0	0
T2	428	3	0	0
T3	148082	649	0	0
T4	93729	7	0	0
T10	1804	11	0	0
T11	2111	34	0	0
T12	1626	25	0	0
T13	785	9	0	0
T14	759	7	0	0
T15	404631	1137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3039067	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3039067	0	0
T1	2793	36	0	0
T2	428	3	0	0
T3	148082	307	0	0
T4	93729	1561	0	0
T10	1804	11	0	0
T11	2111	34	0	0
T12	1626	25	0	0
T13	785	9	0	0
T14	759	7	0	0
T15	404631	92515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1398590	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1398590	0	0
T1	2793	38	0	0
T2	428	7	0	0
T3	148082	563	0	0
T4	93729	21	0	0
T10	1804	24	0	0
T11	2111	27	0	0
T12	1626	25	0	0
T13	785	7	0	0
T14	759	5	0	0
T15	404631	1255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3083270	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3083270	0	0
T1	2793	38	0	0
T2	428	7	0	0
T3	148082	290	0	0
T4	93729	1541	0	0
T10	1804	24	0	0
T11	2111	27	0	0
T12	1626	25	0	0
T13	785	7	0	0
T14	759	5	0	0
T15	404631	99164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1427640	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1427640	0	0
T1	2793	56	0	0
T2	428	3	0	0
T3	148082	3319	0	0
T4	93729	18	0	0
T10	1804	15	0	0
T11	2111	25	0	0
T12	1626	37	0	0
T13	785	4	0	0
T14	759	6	0	0
T15	404631	1067	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3585878	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3585878	0	0
T1	2793	56	0	0
T2	428	3	0	0
T3	148082	2001	0	0
T4	93729	1678	0	0
T10	1804	15	0	0
T11	2111	25	0	0
T12	1626	37	0	0
T13	785	4	0	0
T14	759	6	0	0
T15	404631	89143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1393120	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1393120	0	0
T1	2793	54	0	0
T2	428	3	0	0
T3	148082	3000	0	0
T4	93729	24	0	0
T8	0	160	0	0
T10	1804	20	0	0
T11	2111	27	0	0
T12	1626	15	0	0
T13	785	4	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2304112	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2304112	0	0
T1	2793	54	0	0
T2	428	3	0	0
T3	148082	1347	0	0
T4	93729	1633	0	0
T8	0	160	0	0
T10	1804	20	0	0
T11	2111	27	0	0
T12	1626	15	0	0
T13	785	4	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1442751	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1442751	0	0
T1	2793	47	0	0
T2	428	6	0	0
T3	148082	461	0	0
T4	93729	8	0	0
T8	0	174	0	0
T10	1804	13	0	0
T11	2111	28	0	0
T12	1626	27	0	0
T13	785	5	0	0
T14	759	4	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2830654	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2830654	0	0
T1	2793	47	0	0
T2	428	6	0	0
T3	148082	223	0	0
T4	93729	282	0	0
T8	0	174	0	0
T10	1804	13	0	0
T11	2111	28	0	0
T12	1626	27	0	0
T13	785	5	0	0
T14	759	4	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1448192	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1448192	0	0
T1	2793	49	0	0
T2	428	5	0	0
T3	148082	605	0	0
T4	93729	6	0	0
T10	1804	14	0	0
T11	2111	36	0	0
T12	1626	31	0	0
T13	785	8	0	0
T14	759	3	0	0
T15	404631	1310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3176084	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3176084	0	0
T1	2793	49	0	0
T2	428	5	0	0
T3	148082	251	0	0
T4	93729	588	0	0
T10	1804	14	0	0
T11	2111	36	0	0
T12	1626	31	0	0
T13	785	8	0	0
T14	759	3	0	0
T15	404631	97841	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1411256	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1411256	0	0
T1	2793	44	0	0
T2	428	6	0	0
T3	148082	601	0	0
T4	93729	16	0	0
T10	1804	19	0	0
T11	2111	19	0	0
T12	1626	20	0	0
T13	785	7	0	0
T14	759	7	0	0
T15	404631	1259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3322324	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3322324	0	0
T1	2793	44	0	0
T2	428	6	0	0
T3	148082	342	0	0
T4	93729	803	0	0
T10	1804	19	0	0
T11	2111	19	0	0
T12	1626	20	0	0
T13	785	7	0	0
T14	759	7	0	0
T15	404631	98848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1410878	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1410878	0	0
T1	2793	45	0	0
T2	428	6	0	0
T3	148082	464	0	0
T4	93729	10	0	0
T10	1804	17	0	0
T11	2111	22	0	0
T12	1626	28	0	0
T13	785	8	0	0
T14	759	6	0	0
T15	404631	2340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2884651	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2884651	0	0
T1	2793	45	0	0
T2	428	6	0	0
T3	148082	295	0	0
T4	93729	880	0	0
T10	1804	17	0	0
T11	2111	22	0	0
T12	1626	28	0	0
T13	785	8	0	0
T14	759	6	0	0
T15	404631	173787	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1409361	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1409361	0	0
T1	2793	54	0	0
T2	428	2	0	0
T3	148082	2978	0	0
T4	93729	19	0	0
T10	1804	14	0	0
T11	2111	34	0	0
T12	1626	28	0	0
T13	785	3	0	0
T14	759	1	0	0
T15	404631	2229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2901133	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2901133	0	0
T1	2793	54	0	0
T2	428	2	0	0
T3	148082	1357	0	0
T4	93729	369	0	0
T10	1804	14	0	0
T11	2111	34	0	0
T12	1626	28	0	0
T13	785	3	0	0
T14	759	1	0	0
T15	404631	178896	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1436116	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1436116	0	0
T1	2793	47	0	0
T2	428	4	0	0
T3	148082	2518	0	0
T4	93729	15	0	0
T8	0	151	0	0
T10	1804	18	0	0
T11	2111	27	0	0
T12	1626	34	0	0
T13	785	3	0	0
T14	759	7	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3268511	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3268511	0	0
T1	2793	47	0	0
T2	428	4	0	0
T3	148082	1291	0	0
T4	93729	4477	0	0
T8	0	151	0	0
T10	1804	18	0	0
T11	2111	27	0	0
T12	1626	34	0	0
T13	785	3	0	0
T14	759	7	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1487952	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1487952	0	0
T1	2793	40	0	0
T2	428	8	0	0
T3	148082	4597	0	0
T4	93729	39	0	0
T10	1804	14	0	0
T11	2111	33	0	0
T12	1626	26	0	0
T13	785	11	0	0
T14	759	4	0	0
T15	404631	2468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	3657034	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	3657034	0	0
T1	2793	40	0	0
T2	428	8	0	0
T3	148082	2375	0	0
T4	93729	2370	0	0
T10	1804	14	0	0
T11	2111	33	0	0
T12	1626	26	0	0
T13	785	11	0	0
T14	759	4	0	0
T15	404631	195266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	1495131	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	1495131	0	0
T1	2793	44	0	0
T2	428	1	0	0
T3	148082	545	0	0
T4	93729	8	0	0
T8	0	159	0	0
T10	1804	14	0	0
T11	2111	24	0	0
T12	1626	24	0	0
T13	785	7	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292971291	2387389	0	0
DepthKnown_A	292971291	292864504	0	0
RvalidKnown_A	292971291	292864504	0	0
WreadyKnown_A	292971291	292864504	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	2387389	0	0
T1	2793	44	0	0
T2	428	1	0	0
T3	148082	295	0	0
T4	93729	977	0	0
T8	0	159	0	0
T10	1804	14	0	0
T11	2111	24	0	0
T12	1626	24	0	0
T13	785	7	0	0
T14	759	6	0	0
T15	404631	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292971291	292864504	0	0
T1	2793	2740	0	0
T2	428	401	0	0
T3	148082	147338	0	0
T4	93729	93660	0	0
T10	1804	1780	0	0
T11	2111	2035	0	0
T12	1626	1618	0	0
T13	785	742	0	0
T14	759	694	0	0
T15	404631	404630	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0