Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2003509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

316324

1

T1

2

T2

13

T3

223

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	782182	1			T1	14		T2	48		T3	535
values[0x0]	754829	1			T2	4		T3	585		T4	961
values[0x1]	782822	1			T1	13		T2	47		T3	545

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1554588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

765245

1

T1

10

T2

34

T3

551

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8946	1			T4	4		T20	5		T21	4
valid_sources[0x01]	9080	1			T1	1		T4	53		T20	8
valid_sources[0x02]	8719	1			T19	1		T20	11		T21	5
valid_sources[0x03]	7951	1			T20	7		T21	4		T18	7
valid_sources[0x04]	9094	1			T4	98		T21	4		T18	15
valid_sources[0x05]	9578	1			T16	1		T20	7		T21	4
valid_sources[0x06]	8522	1			T4	1		T20	7		T21	5
valid_sources[0x07]	9410	1			T20	7		T21	4		T18	6
valid_sources[0x08]	8506	1			T4	16		T16	1		T20	4
valid_sources[0x09]	8407	1			T16	2		T20	9		T21	4
valid_sources[0x0a]	8429	1			T16	1		T20	7		T21	3
valid_sources[0x0b]	9149	1			T19	1		T20	6		T21	3
valid_sources[0x0c]	8480	1			T4	11		T16	1		T20	5
valid_sources[0x0d]	9437	1			T20	5		T21	5		T18	27
valid_sources[0x0e]	9417	1			T20	2		T21	3		T18	11
valid_sources[0x0f]	8397	1			T4	1		T19	2		T16	1
valid_sources[0x10]	7979	1			T16	1		T20	5		T21	4
valid_sources[0x11]	8683	1			T4	1		T19	1		T16	1
valid_sources[0x12]	9664	1			T1	1		T4	58		T20	4
valid_sources[0x13]	9548	1			T19	2		T20	6		T21	3
valid_sources[0x14]	9623	1			T4	3		T20	9		T21	4
valid_sources[0x15]	9023	1			T4	14		T19	1		T20	3
valid_sources[0x16]	8857	1			T4	33		T20	10		T21	4
valid_sources[0x17]	9136	1			T20	9		T21	4		T17	1
valid_sources[0x18]	7802	1			T19	1		T20	7		T21	4
valid_sources[0x19]	8130	1			T4	1		T19	2		T20	6
valid_sources[0x1a]	11162	1			T19	2		T20	8		T21	3
valid_sources[0x1b]	9084	1			T20	5		T21	3		T17	2
valid_sources[0x1c]	9604	1			T19	4		T20	7		T21	3
valid_sources[0x1d]	9525	1			T3	218		T19	1		T20	4
valid_sources[0x1e]	9501	1			T2	18		T3	5		T20	14
valid_sources[0x1f]	9409	1			T4	30		T19	1		T20	9
valid_sources[0x20]	8627	1			T19	3		T16	1		T20	11
valid_sources[0x21]	8608	1			T4	53		T19	1		T20	3
valid_sources[0x22]	9579	1			T19	2		T20	10		T21	3
valid_sources[0x23]	8594	1			T4	18		T16	1		T20	7
valid_sources[0x24]	8562	1			T4	24		T20	8		T21	5
valid_sources[0x25]	8350	1			T20	10		T21	4		T17	1
valid_sources[0x26]	8645	1			T3	53		T19	2		T20	9
valid_sources[0x27]	9003	1			T4	19		T20	8		T21	4
valid_sources[0x28]	8435	1			T20	12		T21	4		T24	2
valid_sources[0x29]	8390	1			T20	6		T21	3		T18	1
valid_sources[0x2a]	8852	1			T1	2		T3	42		T4	8
valid_sources[0x2b]	9932	1			T4	15		T19	1		T20	6
valid_sources[0x2c]	8440	1			T4	15		T20	10		T21	4
valid_sources[0x2d]	7947	1			T19	3		T20	7		T21	5
valid_sources[0x2e]	8983	1			T19	1		T20	8		T21	3
valid_sources[0x2f]	8883	1			T4	2		T16	1		T20	6
valid_sources[0x30]	8945	1			T16	1		T20	4		T21	5
valid_sources[0x31]	10429	1			T4	19		T19	1		T20	5
valid_sources[0x32]	9645	1			T4	4		T20	6		T21	5
valid_sources[0x33]	8662	1			T2	5		T19	1		T20	8
valid_sources[0x34]	9485	1			T1	1		T19	2		T16	1
valid_sources[0x35]	7978	1			T4	19		T20	5		T21	4
valid_sources[0x36]	8858	1			T19	1		T20	4		T21	4
valid_sources[0x37]	9208	1			T20	6		T21	4		T18	2
valid_sources[0x38]	8586	1			T20	8		T21	4		T18	25
valid_sources[0x39]	9105	1			T4	14		T20	5		T21	4
valid_sources[0x3a]	9550	1			T4	11		T19	2		T20	10
valid_sources[0x3b]	8675	1			T20	5		T21	4		T18	16
valid_sources[0x3c]	9131	1			T1	1		T4	28		T20	3
valid_sources[0x3d]	8570	1			T19	2		T20	8		T21	4
valid_sources[0x3e]	7979	1			T1	1		T19	3		T16	1
valid_sources[0x3f]	9546	1			T4	6		T16	2		T20	4
valid_sources[0x40]	8061	1			T21	4		T23	1		T27	7
valid_sources[0x41]	8666	1			T4	4		T16	1		T20	2
valid_sources[0x42]	8889	1			T19	1		T20	6		T21	3
valid_sources[0x43]	7992	1			T4	13		T20	4		T21	4
valid_sources[0x44]	9407	1			T1	1		T20	13		T21	4
valid_sources[0x45]	8655	1			T4	2		T19	2		T20	4
valid_sources[0x46]	9566	1			T4	6		T19	2		T20	9
valid_sources[0x47]	8345	1			T20	6		T21	4		T18	2
valid_sources[0x48]	10890	1			T4	6		T19	1		T16	1
valid_sources[0x49]	8723	1			T4	2		T19	4		T16	2
valid_sources[0x4a]	8803	1			T4	9		T19	1		T20	6
valid_sources[0x4b]	10094	1			T20	4		T21	4		T18	4
valid_sources[0x4c]	9352	1			T16	1		T20	8		T21	4
valid_sources[0x4d]	8719	1			T4	9		T19	1		T20	5
valid_sources[0x4e]	8454	1			T1	1		T20	2		T21	6
valid_sources[0x4f]	8838	1			T1	1		T20	10		T21	4
valid_sources[0x50]	8219	1			T16	1		T20	5		T21	4
valid_sources[0x51]	9739	1			T4	20		T20	14		T21	4
valid_sources[0x52]	8262	1			T4	14		T20	5		T21	4
valid_sources[0x53]	9196	1			T4	7		T20	7		T21	4
valid_sources[0x54]	8076	1			T2	2		T4	22		T19	1
valid_sources[0x55]	9364	1			T4	35		T19	1		T16	1
valid_sources[0x56]	9223	1			T19	1		T16	1		T20	9
valid_sources[0x57]	8900	1			T19	1		T20	4		T21	5
valid_sources[0x58]	8678	1			T4	5		T19	1		T16	1
valid_sources[0x59]	11244	1			T20	6		T21	3		T25	5
valid_sources[0x5a]	8554	1			T4	4		T20	6		T21	4
valid_sources[0x5b]	9092	1			T19	1		T20	10		T21	5
valid_sources[0x5c]	8777	1			T4	5		T16	2		T20	9
valid_sources[0x5d]	8212	1			T20	8		T21	4		T18	13
valid_sources[0x5e]	8915	1			T19	2		T20	1		T21	3
valid_sources[0x5f]	9572	1			T2	6		T4	16		T20	8
valid_sources[0x60]	9004	1			T4	4		T19	1		T20	7
valid_sources[0x61]	8805	1			T19	2		T16	2		T20	11
valid_sources[0x62]	9433	1			T2	2		T20	5		T21	3
valid_sources[0x63]	8165	1			T4	4		T19	1		T20	12
valid_sources[0x64]	9371	1			T4	20		T16	1		T20	9
valid_sources[0x65]	11092	1			T20	11		T21	3		T18	3
valid_sources[0x66]	11020	1			T4	35		T20	8		T21	4
valid_sources[0x67]	8382	1			T4	41		T20	10		T21	3
valid_sources[0x68]	8472	1			T4	33		T20	8		T21	3
valid_sources[0x69]	10092	1			T4	20		T16	1		T20	9
valid_sources[0x6a]	8266	1			T2	4		T4	3		T20	11
valid_sources[0x6b]	8899	1			T4	8		T20	4		T21	4
valid_sources[0x6c]	11161	1			T4	1		T20	9		T21	4
valid_sources[0x6d]	9379	1			T2	12		T19	1		T20	6
valid_sources[0x6e]	9329	1			T1	1		T20	6		T21	4
valid_sources[0x6f]	9344	1			T16	1		T20	6		T21	4
valid_sources[0x70]	8720	1			T4	6		T19	4		T16	1
valid_sources[0x71]	10856	1			T4	6		T16	1		T20	4
valid_sources[0x72]	8844	1			T20	13		T21	4		T18	9
valid_sources[0x73]	10049	1			T20	8		T21	4		T18	1
valid_sources[0x74]	8354	1			T1	1		T19	2		T20	6
valid_sources[0x75]	9017	1			T4	57		T16	1		T20	7
valid_sources[0x76]	9307	1			T20	7		T21	4		T22	8
valid_sources[0x77]	8406	1			T20	8		T21	4		T25	19
valid_sources[0x78]	10208	1			T20	8		T21	5		T17	1
valid_sources[0x79]	8111	1			T4	4		T20	8		T21	3
valid_sources[0x7a]	9018	1			T4	27		T20	8		T21	4
valid_sources[0x7b]	11853	1			T20	5		T21	4		T18	13
valid_sources[0x7c]	9594	1			T1	1		T4	1		T20	4
valid_sources[0x7d]	7878	1			T4	7		T19	1		T20	5
valid_sources[0x7e]	7801	1			T20	14		T21	4		T18	9
valid_sources[0x7f]	10020	1			T20	9		T21	4		T18	15
valid_sources[0x80]	8510	1			T1	1		T4	58		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

32925

1

T1

1

T2

9

T3

27

values[0x0]

all_enables

biggest_size

250267

1

T3

179

T4

317

T19

16

values[0x1]

all_enables

biggest_size

33132

1

T1

1

T2

4

T3

17