Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328876419	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328876419	0	0
T1	80472	3279	0	0
T2	227192	10065	0	0
T3	185416	8169	0	0
T4	4494056	112664	0	0
T16	185416	6326	0	0
T17	1217440	17900	0	0
T18	0	20576	0	0
T19	4217864	74722	0	0
T20	2035768	43924	0	0
T21	51931600	753197	0	0
T22	10572912	188946	0	0
T23	0	7486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	80472	79520	0	0
T2	227192	226072	0	0
T3	185416	184688	0	0
T4	4494056	4493664	0	0
T16	185416	184576	0	0
T17	1217440	1213968	0	0
T19	4217864	4216688	0	0
T20	2035768	2035040	0	0
T21	51931600	51929080	0	0
T22	10572912	10570056	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	80472	79520	0	0
T2	227192	226072	0	0
T3	185416	184688	0	0
T4	4494056	4493664	0	0
T16	185416	184576	0	0
T17	1217440	1213968	0	0
T19	4217864	4216688	0	0
T20	2035768	2035040	0	0
T21	51931600	51929080	0	0
T22	10572912	10570056	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	80472	79520	0	0
T2	227192	226072	0	0
T3	185416	184688	0	0
T4	4494056	4493664	0	0
T16	185416	184576	0	0
T17	1217440	1213968	0	0
T19	4217864	4216688	0	0
T20	2035768	2035040	0	0
T21	51931600	51929080	0	0
T22	10572912	10570056	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	118984994	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	118984994	0	0
T1	1437	1272	0	0
T2	4057	3921	0	0
T3	3311	3178	0	0
T4	80251	49417	0	0
T16	3311	3138	0	0
T17	21740	7923	0	0
T19	75319	72734	0	0
T20	36353	14428	0	0
T21	927350	5271	0	0
T22	188802	90741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	87496600	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	87496600	0	0
T1	1437	669	0	0
T2	4057	2048	0	0
T3	3311	1665	0	0
T4	80251	20273	0	0
T16	3311	1604	0	0
T17	21740	2747	0	0
T19	75319	668	0	0
T20	36353	7534	0	0
T21	927350	372183	0	0
T22	188802	19139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1334285	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1334285	0	0
T1	1437	19	0	0
T2	4057	55	0	0
T3	3311	58	0	0
T4	80251	835	0	0
T16	3311	28	0	0
T17	21740	206	0	0
T18	0	389	0	0
T19	75319	30	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1602	0	0
T23	0	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2890509	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2890509	0	0
T1	1437	19	0	0
T2	4057	55	0	0
T3	3311	58	0	0
T4	80251	753	0	0
T16	3311	28	0	0
T17	21740	84	0	0
T18	0	173	0	0
T19	75319	9	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	401	0	0
T23	0	150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1328555	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1328555	0	0
T1	1437	24	0	0
T2	4057	75	0	0
T3	3311	78	0	0
T4	80251	874	0	0
T16	3311	24	0	0
T17	21740	173	0	0
T18	0	445	0	0
T19	75319	21	0	0
T20	36353	1966	0	0
T21	927350	0	0	0
T22	188802	3011	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2896050	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2896050	0	0
T1	1437	24	0	0
T2	4057	75	0	0
T3	3311	78	0	0
T4	80251	758	0	0
T16	3311	24	0	0
T17	21740	87	0	0
T18	0	253	0	0
T19	75319	4	0	0
T20	36353	983	0	0
T21	927350	0	0	0
T22	188802	409	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1360075	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1360075	0	0
T1	1437	19	0	0
T2	4057	75	0	0
T3	3311	47	0	0
T4	80251	984	0	0
T16	3311	30	0	0
T17	21740	176	0	0
T18	0	705	0	0
T19	75319	40	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	792	0	0
T23	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3582759	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3582759	0	0
T1	1437	19	0	0
T2	4057	75	0	0
T3	3311	47	0	0
T4	80251	836	0	0
T16	3311	30	0	0
T17	21740	53	0	0
T18	0	276	0	0
T19	75319	7	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	706	0	0
T23	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1307577	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1307577	0	0
T1	1437	28	0	0
T2	4057	77	0	0
T3	3311	63	0	0
T4	80251	892	0	0
T16	3311	30	0	0
T17	21740	160	0	0
T18	0	419	0	0
T19	75319	35	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1455	0	0
T23	0	204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3574977	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3574977	0	0
T1	1437	28	0	0
T2	4057	77	0	0
T3	3311	63	0	0
T4	80251	674	0	0
T16	3311	30	0	0
T17	21740	76	0	0
T18	0	203	0	0
T19	75319	7	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	660	0	0
T23	0	211	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1317048	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1317048	0	0
T1	1437	28	0	0
T2	4057	73	0	0
T3	3311	70	0	0
T4	80251	874	0	0
T16	3311	29	0	0
T17	21740	214	0	0
T18	0	440	0	0
T19	75319	6	0	0
T20	36353	2228	0	0
T21	927350	0	0	0
T22	188802	2271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3007713	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3007713	0	0
T1	1437	28	0	0
T2	4057	73	0	0
T3	3311	70	0	0
T4	80251	698	0	0
T16	3311	29	0	0
T17	21740	76	0	0
T18	0	194	0	0
T19	75319	2	0	0
T20	36353	1199	0	0
T21	927350	0	0	0
T22	188802	614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1326813	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1326813	0	0
T1	1437	21	0	0
T2	4057	86	0	0
T3	3311	69	0	0
T4	80251	885	0	0
T16	3311	30	0	0
T17	21740	133	0	0
T18	0	564	0	0
T19	75319	16	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2835	0	0
T23	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2735371	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2735371	0	0
T1	1437	21	0	0
T2	4057	86	0	0
T3	3311	69	0	0
T4	80251	931	0	0
T16	3311	30	0	0
T17	21740	39	0	0
T18	0	225	0	0
T19	75319	4	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	652	0	0
T23	0	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1311676	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1311676	0	0
T1	1437	23	0	0
T2	4057	75	0	0
T3	3311	60	0	0
T4	80251	860	0	0
T16	3311	33	0	0
T17	21740	213	0	0
T18	0	402	0	0
T19	75319	31	0	0
T20	36353	0	0	0
T21	927350	1089	0	0
T22	188802	2902	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3139954	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3139954	0	0
T1	1437	23	0	0
T2	4057	75	0	0
T3	3311	60	0	0
T4	80251	755	0	0
T16	3311	33	0	0
T17	21740	61	0	0
T18	0	183	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	94770	0	0
T22	188802	1298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1347480	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1347480	0	0
T1	1437	20	0	0
T2	4057	65	0	0
T3	3311	76	0	0
T4	80251	758	0	0
T16	3311	33	0	0
T17	21740	262	0	0
T18	0	481	0	0
T19	75319	33	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	886	0	0
T23	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3462178	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3462178	0	0
T1	1437	20	0	0
T2	4057	65	0	0
T3	3311	76	0	0
T4	80251	647	0	0
T16	3311	33	0	0
T17	21740	95	0	0
T18	0	218	0	0
T19	75319	7	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	561	0	0
T23	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1312289	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1312289	0	0
T1	1437	24	0	0
T2	4057	81	0	0
T3	3311	65	0	0
T4	80251	964	0	0
T16	3311	31	0	0
T17	21740	208	0	0
T18	0	681	0	0
T19	75319	12	0	0
T20	36353	0	0	0
T21	927350	1236	0	0
T22	188802	4252	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3750836	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3750836	0	0
T1	1437	24	0	0
T2	4057	81	0	0
T3	3311	65	0	0
T4	80251	797	0	0
T16	3311	31	0	0
T17	21740	72	0	0
T18	0	318	0	0
T19	75319	4	0	0
T20	36353	0	0	0
T21	927350	105159	0	0
T22	188802	1018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1304557	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1304557	0	0
T1	1437	29	0	0
T2	4057	78	0	0
T3	3311	62	0	0
T4	80251	835	0	0
T16	3311	33	0	0
T17	21740	155	0	0
T18	0	534	0	0
T19	75319	17	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2694	0	0
T23	0	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2920821	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2920821	0	0
T1	1437	29	0	0
T2	4057	78	0	0
T3	3311	62	0	0
T4	80251	683	0	0
T16	3311	33	0	0
T17	21740	119	0	0
T18	0	263	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2239	0	0
T23	0	298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1384385	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1384385	0	0
T1	1437	28	0	0
T2	4057	66	0	0
T3	3311	52	0	0
T4	80251	832	0	0
T16	3311	29	0	0
T17	21740	187	0	0
T18	0	360	0	0
T19	75319	16	0	0
T20	36353	0	0	0
T21	927350	983	0	0
T22	188802	3111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	4044371	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	4044371	0	0
T1	1437	28	0	0
T2	4057	66	0	0
T3	3311	52	0	0
T4	80251	665	0	0
T16	3311	29	0	0
T17	21740	79	0	0
T18	0	201	0	0
T19	75319	4	0	0
T20	36353	0	0	0
T21	927350	84168	0	0
T22	188802	785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1339314	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1339314	0	0
T1	1437	28	0	0
T2	4057	83	0	0
T3	3311	65	0	0
T4	80251	1063	0	0
T16	3311	24	0	0
T17	21740	270	0	0
T18	0	512	0	0
T19	75319	29	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2695	0	0
T23	0	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3173513	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3173513	0	0
T1	1437	28	0	0
T2	4057	83	0	0
T3	3311	65	0	0
T4	80251	927	0	0
T16	3311	24	0	0
T17	21740	101	0	0
T18	0	186	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1652	0	0
T23	0	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1285789	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1285789	0	0
T1	1437	23	0	0
T2	4057	75	0	0
T3	3311	55	0	0
T4	80251	814	0	0
T16	3311	28	0	0
T17	21740	164	0	0
T18	0	546	0	0
T19	75319	19	0	0
T20	36353	1360	0	0
T21	927350	0	0	0
T22	188802	2658	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2475726	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2475726	0	0
T1	1437	23	0	0
T2	4057	75	0	0
T3	3311	55	0	0
T4	80251	904	0	0
T16	3311	28	0	0
T17	21740	91	0	0
T18	0	186	0	0
T19	75319	4	0	0
T20	36353	1004	0	0
T21	927350	0	0	0
T22	188802	1569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1263995	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1263995	0	0
T1	1437	18	0	0
T2	4057	67	0	0
T3	3311	68	0	0
T4	80251	791	0	0
T16	3311	30	0	0
T17	21740	154	0	0
T18	0	479	0	0
T19	75319	39	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	520	0	0
T23	0	187	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2928928	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2928928	0	0
T1	1437	18	0	0
T2	4057	67	0	0
T3	3311	68	0	0
T4	80251	654	0	0
T16	3311	30	0	0
T17	21740	78	0	0
T18	0	238	0	0
T19	75319	9	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	355	0	0
T23	0	201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1321429	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1321429	0	0
T1	1437	23	0	0
T2	4057	73	0	0
T3	3311	50	0	0
T4	80251	827	0	0
T16	3311	28	0	0
T17	21740	107	0	0
T18	0	492	0	0
T19	75319	16	0	0
T20	36353	2128	0	0
T21	927350	0	0	0
T22	188802	1298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3337572	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3337572	0	0
T1	1437	23	0	0
T2	4057	73	0	0
T3	3311	50	0	0
T4	80251	812	0	0
T16	3311	28	0	0
T17	21740	53	0	0
T18	0	245	0	0
T19	75319	5	0	0
T20	36353	1087	0	0
T21	927350	0	0	0
T22	188802	382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1274638	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1274638	0	0
T1	1437	20	0	0
T2	4057	75	0	0
T3	3311	69	0	0
T4	80251	777	0	0
T16	3311	23	0	0
T17	21740	146	0	0
T18	0	512	0	0
T19	75319	30	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2080	0	0
T23	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3586153	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3586153	0	0
T1	1437	20	0	0
T2	4057	75	0	0
T3	3311	69	0	0
T4	80251	581	0	0
T16	3311	23	0	0
T17	21740	52	0	0
T18	0	263	0	0
T19	75319	5	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	836	0	0
T23	0	193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1295267	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1295267	0	0
T1	1437	22	0	0
T2	4057	58	0	0
T3	3311	59	0	0
T4	80251	959	0	0
T16	3311	23	0	0
T17	21740	114	0	0
T18	0	474	0	0
T19	75319	28	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2463	0	0
T23	0	168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2858294	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2858294	0	0
T1	1437	22	0	0
T2	4057	58	0	0
T3	3311	59	0	0
T4	80251	737	0	0
T16	3311	23	0	0
T17	21740	88	0	0
T18	0	254	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	615	0	0
T23	0	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1368401	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1368401	0	0
T1	1437	27	0	0
T2	4057	79	0	0
T3	3311	54	0	0
T4	80251	761	0	0
T16	3311	40	0	0
T17	21740	166	0	0
T18	0	526	0	0
T19	75319	31	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	4488	0	0
T23	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3518536	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3518536	0	0
T1	1437	27	0	0
T2	4057	79	0	0
T3	3311	54	0	0
T4	80251	591	0	0
T16	3311	40	0	0
T17	21740	63	0	0
T18	0	279	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	859	0	0
T23	0	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1350599	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1350599	0	0
T1	1437	20	0	0
T2	4057	79	0	0
T3	3311	57	0	0
T4	80251	813	0	0
T16	3311	34	0	0
T17	21740	197	0	0
T18	0	337	0	0
T19	75319	19	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1850	0	0
T23	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	4729567	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	4729567	0	0
T1	1437	20	0	0
T2	4057	79	0	0
T3	3311	57	0	0
T4	80251	608	0	0
T16	3311	34	0	0
T17	21740	67	0	0
T18	0	130	0	0
T19	75319	4	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	525	0	0
T23	0	209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1295864	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1295864	0	0
T1	1437	15	0	0
T2	4057	84	0	0
T3	3311	76	0	0
T4	80251	822	0	0
T16	3311	25	0	0
T17	21740	107	0	0
T18	0	460	0	0
T19	75319	6	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2989	0	0
T23	0	211	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3170305	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3170305	0	0
T1	1437	15	0	0
T2	4057	84	0	0
T3	3311	76	0	0
T4	80251	785	0	0
T16	3311	25	0	0
T17	21740	58	0	0
T18	0	173	0	0
T19	75319	1	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1149	0	0
T23	0	198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1374033	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1374033	0	0
T1	1437	23	0	0
T2	4057	84	0	0
T3	3311	50	0	0
T4	80251	841	0	0
T16	3311	27	0	0
T17	21740	179	0	0
T18	0	423	0	0
T19	75319	14	0	0
T20	36353	2184	0	0
T21	927350	0	0	0
T22	188802	899	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3146206	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3146206	0	0
T1	1437	23	0	0
T2	4057	84	0	0
T3	3311	50	0	0
T4	80251	913	0	0
T16	3311	27	0	0
T17	21740	39	0	0
T18	0	191	0	0
T19	75319	3	0	0
T20	36353	1183	0	0
T21	927350	0	0	0
T22	188802	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1323241	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1323241	0	0
T1	1437	34	0	0
T2	4057	81	0	0
T3	3311	58	0	0
T4	80251	700	0	0
T16	3311	22	0	0
T17	21740	242	0	0
T19	75319	18	0	0
T20	36353	4562	0	0
T21	927350	1109	0	0
T22	188802	1939	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3536922	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3536922	0	0
T1	1437	34	0	0
T2	4057	81	0	0
T3	3311	58	0	0
T4	80251	712	0	0
T16	3311	22	0	0
T17	21740	123	0	0
T19	75319	523	0	0
T20	36353	2078	0	0
T21	927350	87229	0	0
T22	188802	648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1380613	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1380613	0	0
T1	1437	33	0	0
T2	4057	79	0	0
T3	3311	56	0	0
T4	80251	686	0	0
T16	3311	37	0	0
T17	21740	207	0	0
T18	0	700	0	0
T19	75319	9	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2402	0	0
T23	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	3322870	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	3322870	0	0
T1	1437	33	0	0
T2	4057	79	0	0
T3	3311	56	0	0
T4	80251	623	0	0
T16	3311	37	0	0
T17	21740	77	0	0
T18	0	362	0	0
T19	75319	3	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	161	0	0
T23	0	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1309340	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1309340	0	0
T1	1437	29	0	0
T2	4057	79	0	0
T3	3311	54	0	0
T4	80251	636	0	0
T16	3311	27	0	0
T17	21740	254	0	0
T18	0	1573	0	0
T19	75319	17	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	1548	0	0
T23	0	218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2699599	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2699599	0	0
T1	1437	29	0	0
T2	4057	79	0	0
T3	3311	54	0	0
T4	80251	611	0	0
T16	3311	27	0	0
T17	21740	177	0	0
T18	0	738	0	0
T19	75319	4	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	96	0	0
T23	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1295417	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1295417	0	0
T1	1437	22	0	0
T2	4057	74	0	0
T3	3311	65	0	0
T4	80251	965	0	0
T16	3311	39	0	0
T17	21740	201	0	0
T18	0	473	0	0
T19	75319	38	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	2171	0	0
T23	0	479	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2983920	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2983920	0	0
T1	1437	22	0	0
T2	4057	74	0	0
T3	3311	65	0	0
T4	80251	947	0	0
T16	3311	39	0	0
T17	21740	146	0	0
T18	0	271	0	0
T19	75319	9	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	168	0	0
T23	0	424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1313173	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1313173	0	0
T1	1437	37	0	0
T2	4057	90	0	0
T3	3311	61	0	0
T4	80251	946	0	0
T16	3311	25	0	0
T17	21740	205	0	0
T18	0	505	0	0
T19	75319	32	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	725	0	0
T23	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2465321	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2465321	0	0
T1	1437	37	0	0
T2	4057	90	0	0
T3	3311	61	0	0
T4	80251	898	0	0
T16	3311	25	0	0
T17	21740	79	0	0
T18	0	270	0	0
T19	75319	11	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	303	0	0
T23	0	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	1358800	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	1358800	0	0
T1	1437	32	0	0
T2	4057	82	0	0
T3	3311	66	0	0
T4	80251	715	0	0
T16	3311	30	0	0
T17	21740	221	0	0
T18	0	609	0	0
T19	75319	50	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	3391	0	0
T23	0	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296642157	2671201	0	0
DepthKnown_A	296642157	296522254	0	0
RvalidKnown_A	296642157	296522254	0	0
WreadyKnown_A	296642157	296522254	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	2671201	0	0
T1	1437	32	0	0
T2	4057	82	0	0
T3	3311	66	0	0
T4	80251	765	0	0
T16	3311	30	0	0
T17	21740	76	0	0
T18	0	242	0	0
T19	75319	9	0	0
T20	36353	0	0	0
T21	927350	0	0	0
T22	188802	385	0	0
T23	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296642157	296522254	0	0
T1	1437	1420	0	0
T2	4057	4037	0	0
T3	3311	3298	0	0
T4	80251	80244	0	0
T16	3311	3296	0	0
T17	21740	21678	0	0
T19	75319	75298	0	0
T20	36353	36340	0	0
T21	927350	927305	0	0
T22	188802	188751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0