Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1703911	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268108

1

T1

5

T4

354

T2

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	666598	1			T1	40		T4	810		T2	24
values[0x0]	638000	1			T1	1		T4	781		T2	9
values[0x1]	667421	1			T1	37		T4	763		T2	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1321490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

650529

1

T1

32

T4

796

T2

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7606	1			T2	1		T3	17		T5	2
valid_sources[0x01]	7785	1			T3	5		T5	6		T21	5
valid_sources[0x02]	7415	1			T3	11		T21	5		T20	10
valid_sources[0x03]	8261	1			T3	14		T5	7		T21	3
valid_sources[0x04]	7146	1			T3	21		T5	5		T21	12
valid_sources[0x05]	7372	1			T3	17		T5	1		T21	7
valid_sources[0x06]	7358	1			T3	7		T5	1		T21	8
valid_sources[0x07]	7323	1			T3	28		T5	4		T21	5
valid_sources[0x08]	7699	1			T5	4		T21	11		T20	18
valid_sources[0x09]	8091	1			T3	12		T5	1		T21	5
valid_sources[0x0a]	7667	1			T1	1		T3	5		T5	5
valid_sources[0x0b]	7322	1			T3	14		T5	7		T21	5
valid_sources[0x0c]	8217	1			T2	1		T3	14		T5	1
valid_sources[0x0d]	7268	1			T3	27		T5	4		T21	8
valid_sources[0x0e]	6989	1			T1	7		T3	11		T21	8
valid_sources[0x0f]	7616	1			T2	1		T3	5		T5	9
valid_sources[0x10]	7412	1			T2	1		T3	9		T5	6
valid_sources[0x11]	7641	1			T3	7		T5	9		T20	170
valid_sources[0x12]	7483	1			T2	1		T3	27		T5	1
valid_sources[0x13]	7176	1			T3	14		T5	1		T21	3
valid_sources[0x14]	7593	1			T3	13		T5	2		T21	5
valid_sources[0x15]	6773	1			T3	13		T5	1		T21	5
valid_sources[0x16]	7825	1			T2	2		T3	19		T5	1
valid_sources[0x17]	7536	1			T3	3		T5	2		T21	3
valid_sources[0x18]	7474	1			T3	19		T5	3		T21	7
valid_sources[0x19]	7989	1			T3	11		T5	2		T21	1
valid_sources[0x1a]	8575	1			T2	1		T3	15		T21	8
valid_sources[0x1b]	7690	1			T3	20		T5	2		T21	8
valid_sources[0x1c]	7888	1			T3	8		T5	2		T21	17
valid_sources[0x1d]	7292	1			T3	6		T5	4		T21	3
valid_sources[0x1e]	7819	1			T3	25		T5	5		T21	10
valid_sources[0x1f]	7608	1			T3	8		T5	5		T21	14
valid_sources[0x20]	7772	1			T3	18		T21	1		T20	45
valid_sources[0x21]	7435	1			T3	18		T5	1		T21	10
valid_sources[0x22]	8474	1			T3	9		T21	9		T20	27
valid_sources[0x23]	7133	1			T3	8		T5	8		T21	5
valid_sources[0x24]	7767	1			T3	13		T5	4		T21	2
valid_sources[0x25]	7937	1			T3	19		T21	9		T20	103
valid_sources[0x26]	7888	1			T3	7		T5	4		T21	4
valid_sources[0x27]	7839	1			T3	21		T5	1		T21	5
valid_sources[0x28]	9241	1			T3	13		T21	14		T20	52
valid_sources[0x29]	8544	1			T3	16		T5	2		T21	9
valid_sources[0x2a]	7596	1			T1	1		T3	12		T5	2
valid_sources[0x2b]	7890	1			T3	9		T21	2		T20	24
valid_sources[0x2c]	8698	1			T3	9		T5	7		T21	5
valid_sources[0x2d]	7315	1			T3	14		T5	9		T21	6
valid_sources[0x2e]	8059	1			T4	468		T3	3		T5	4
valid_sources[0x2f]	7184	1			T3	9		T5	3		T21	7
valid_sources[0x30]	7432	1			T2	4		T3	17		T5	4
valid_sources[0x31]	7603	1			T3	9		T21	10		T20	47
valid_sources[0x32]	6941	1			T3	12		T5	2		T21	6
valid_sources[0x33]	7560	1			T1	1		T2	1		T3	26
valid_sources[0x34]	7663	1			T3	5		T5	1		T21	3
valid_sources[0x35]	8123	1			T1	3		T2	1		T3	14
valid_sources[0x36]	8878	1			T1	1		T3	7		T5	1
valid_sources[0x37]	7651	1			T3	6		T5	3		T21	3
valid_sources[0x38]	8174	1			T3	18		T5	3		T21	5
valid_sources[0x39]	6754	1			T3	4		T5	3		T21	14
valid_sources[0x3a]	7281	1			T3	5		T5	1		T21	8
valid_sources[0x3b]	7961	1			T3	19		T5	2		T21	6
valid_sources[0x3c]	7173	1			T3	19		T21	3		T20	37
valid_sources[0x3d]	7111	1			T3	6		T5	2		T21	5
valid_sources[0x3e]	7188	1			T4	123		T2	1		T3	19
valid_sources[0x3f]	7596	1			T3	18		T5	5		T21	12
valid_sources[0x40]	7977	1			T1	4		T3	10		T5	3
valid_sources[0x41]	8278	1			T2	4		T3	9		T5	1
valid_sources[0x42]	7566	1			T2	1		T3	13		T21	5
valid_sources[0x43]	7579	1			T2	1		T3	9		T5	1
valid_sources[0x44]	6702	1			T3	10		T5	3		T21	8
valid_sources[0x45]	7903	1			T3	11		T5	4		T21	8
valid_sources[0x46]	7663	1			T3	11		T5	5		T21	6
valid_sources[0x47]	7807	1			T1	3		T3	1		T5	1
valid_sources[0x48]	7480	1			T3	8		T5	1		T21	2
valid_sources[0x49]	8166	1			T3	17		T21	12		T20	84
valid_sources[0x4a]	7205	1			T1	2		T3	8		T5	5
valid_sources[0x4b]	7973	1			T3	15		T5	1		T21	7
valid_sources[0x4c]	7539	1			T3	18		T21	8		T20	89
valid_sources[0x4d]	7834	1			T3	8		T5	1		T21	6
valid_sources[0x4e]	7830	1			T2	3		T3	15		T5	2
valid_sources[0x4f]	7452	1			T1	2		T3	14		T5	6
valid_sources[0x50]	7685	1			T3	5		T21	6		T20	4
valid_sources[0x51]	7254	1			T3	23		T21	10		T20	6
valid_sources[0x52]	7245	1			T3	12		T5	4		T21	13
valid_sources[0x53]	7517	1			T3	10		T5	2		T21	9
valid_sources[0x54]	7536	1			T3	14		T21	3		T20	31
valid_sources[0x55]	7886	1			T2	1		T3	17		T5	2
valid_sources[0x56]	8121	1			T2	1		T3	8		T5	3
valid_sources[0x57]	7769	1			T4	102		T3	6		T5	1
valid_sources[0x58]	7492	1			T3	15		T5	7		T21	2
valid_sources[0x59]	7142	1			T3	7		T5	4		T21	5
valid_sources[0x5a]	7521	1			T3	3		T5	3		T21	1
valid_sources[0x5b]	8771	1			T3	8		T5	1		T21	7
valid_sources[0x5c]	7252	1			T3	10		T5	3		T21	11
valid_sources[0x5d]	7631	1			T2	3		T3	12		T21	13
valid_sources[0x5e]	7976	1			T3	14		T5	4		T21	11
valid_sources[0x5f]	7396	1			T3	12		T5	6		T21	9
valid_sources[0x60]	7869	1			T3	7		T5	3		T21	9
valid_sources[0x61]	7165	1			T3	11		T21	8		T20	22
valid_sources[0x62]	7411	1			T3	23		T5	4		T21	9
valid_sources[0x63]	7960	1			T3	17		T5	2		T21	4
valid_sources[0x64]	6954	1			T1	1		T3	7		T5	5
valid_sources[0x65]	7798	1			T3	15		T5	5		T21	1
valid_sources[0x66]	7866	1			T1	1		T2	1		T3	5
valid_sources[0x67]	7460	1			T2	10		T3	9		T21	6
valid_sources[0x68]	7376	1			T3	7		T5	4		T21	13
valid_sources[0x69]	7475	1			T3	7		T5	5		T21	6
valid_sources[0x6a]	8677	1			T3	10		T21	7		T20	7
valid_sources[0x6b]	7534	1			T3	16		T21	10		T22	42
valid_sources[0x6c]	7404	1			T4	228		T3	7		T5	3
valid_sources[0x6d]	7827	1			T3	18		T5	2		T21	3
valid_sources[0x6e]	7535	1			T3	19		T5	2		T21	5
valid_sources[0x6f]	7800	1			T3	28		T21	14		T20	43
valid_sources[0x70]	7956	1			T3	5		T21	7		T20	14
valid_sources[0x71]	7638	1			T1	3		T3	18		T5	4
valid_sources[0x72]	7856	1			T3	8		T5	2		T21	11
valid_sources[0x73]	8359	1			T3	16		T5	4		T21	8
valid_sources[0x74]	7391	1			T3	2		T5	3		T21	2
valid_sources[0x75]	7446	1			T3	8		T5	6		T21	6
valid_sources[0x76]	7170	1			T3	16		T5	4		T21	5
valid_sources[0x77]	8248	1			T3	10		T5	1		T21	10
valid_sources[0x78]	7891	1			T2	1		T3	12		T21	4
valid_sources[0x79]	7885	1			T3	11		T5	3		T21	7
valid_sources[0x7a]	7816	1			T3	18		T5	7		T21	16
valid_sources[0x7b]	7474	1			T4	102		T3	14		T21	4
valid_sources[0x7c]	8999	1			T3	24		T21	1		T20	64
valid_sources[0x7d]	7157	1			T3	13		T5	2		T21	8
valid_sources[0x7e]	7634	1			T3	12		T5	5		T21	16
valid_sources[0x7f]	7709	1			T3	10		T5	4		T21	5
valid_sources[0x80]	7855	1			T3	6		T5	7		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28039

1

T1

2

T4

50

T2

2

values[0x0]

all_enables

biggest_size

211998

1

T4

274

T2

4

T3

348

values[0x1]

all_enables

biggest_size

28071

1

T1

3

T4

30

T2

2