Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	334567802	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334567802	0	0
T1	1720712	24908	0	0
T2	2016560	41738	0	0
T3	3236072	72158	0	0
T4	149744	9416	0	0
T5	107912	2951	0	0
T20	12231800	238733	0	0
T21	197008	8727	0	0
T22	21255808	468886	0	0
T23	1436736	35298	0	0
T24	32312	552	0	0
T25	0	22680	0	0
T26	0	14383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1720712	1720152	0	0
T2	2016560	1947120	0	0
T3	3236072	3234000	0	0
T4	149744	147504	0	0
T5	107912	105616	0	0
T20	12231800	12221664	0	0
T21	197008	196336	0	0
T22	21255808	21241864	0	0
T23	1436736	1435224	0	0
T24	32312	29120	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1720712	1720152	0	0
T2	2016560	1947120	0	0
T3	3236072	3234000	0	0
T4	149744	147504	0	0
T5	107912	105616	0	0
T20	12231800	12221664	0	0
T21	197008	196336	0	0
T22	21255808	21241864	0	0
T23	1436736	1435224	0	0
T24	32312	29120	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1720712	1720152	0	0
T2	2016560	1947120	0	0
T3	3236072	3234000	0	0
T4	149744	147504	0	0
T5	107912	105616	0	0
T20	12231800	12221664	0	0
T21	197008	196336	0	0
T22	21255808	21241864	0	0
T23	1436736	1435224	0	0
T24	32312	29120	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0
T24	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	125758949	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	125758949	0	0
T1	30727	11233	0	0
T2	36010	17505	0	0
T3	57787	22735	0	0
T4	2674	2354	0	0
T5	1927	1478	0	0
T20	218425	104488	0	0
T21	3518	3402	0	0
T22	379568	173357	0	0
T23	25656	15277	0	0
T24	577	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	85371962	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	85371962	0	0
T1	30727	3920	0	0
T2	36010	7886	0	0
T3	57787	13345	0	0
T4	2674	2354	0	0
T5	1927	751	0	0
T20	218425	33215	0	0
T21	3518	1775	0	0
T22	379568	107032	0	0
T23	25656	6596	0	0
T24	577	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1393370	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1393370	0	0
T1	30727	290	0	0
T2	36010	390	0	0
T3	57787	1907	0	0
T4	2674	463	0	0
T5	1927	10	0	0
T20	218425	1741	0	0
T21	3518	63	0	0
T22	379568	6340	0	0
T23	25656	347	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2471112	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2471112	0	0
T1	30727	106	0	0
T2	36010	383	0	0
T3	57787	978	0	0
T4	2674	463	0	0
T5	1927	10	0	0
T20	218425	650	0	0
T21	3518	63	0	0
T22	379568	6115	0	0
T23	25656	355	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1482785	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1482785	0	0
T1	30727	242	0	0
T2	36010	188	0	0
T3	57787	1988	0	0
T4	2674	210	0	0
T5	1927	14	0	0
T20	218425	3913	0	0
T21	3518	67	0	0
T22	379568	5545	0	0
T23	25656	171	0	0
T24	577	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2921890	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2921890	0	0
T1	30727	86	0	0
T2	36010	157	0	0
T3	57787	889	0	0
T4	2674	210	0	0
T5	1927	14	0	0
T20	218425	1711	0	0
T21	3518	67	0	0
T22	379568	5540	0	0
T23	25656	166	0	0
T24	577	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1443350	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1443350	0	0
T1	30727	203	0	0
T2	36010	256	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	17	0	0
T20	218425	1699	0	0
T21	3518	78	0	0
T22	379568	3353	0	0
T23	25656	256	0	0
T24	577	3	0	0
T25	0	483	0	0
T26	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3391418	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3391418	0	0
T1	30727	113	0	0
T2	36010	258	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	17	0	0
T20	218425	765	0	0
T21	3518	78	0	0
T22	379568	3878	0	0
T23	25656	187	0	0
T24	577	3	0	0
T25	0	483	0	0
T26	0	375	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1464031	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1464031	0	0
T1	30727	331	0	0
T2	36010	262	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	15	0	0
T20	218425	1600	0	0
T21	3518	61	0	0
T22	379568	3880	0	0
T23	25656	215	0	0
T24	577	2	0	0
T25	0	800	0	0
T26	0	417	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3431876	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3431876	0	0
T1	30727	196	0	0
T2	36010	224	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	15	0	0
T20	218425	725	0	0
T21	3518	61	0	0
T22	379568	3449	0	0
T23	25656	224	0	0
T24	577	2	0	0
T25	0	800	0	0
T26	0	506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1447732	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1447732	0	0
T1	30727	216	0	0
T2	36010	193	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	16	0	0
T20	218425	3935	0	0
T21	3518	67	0	0
T22	379568	1899	0	0
T23	25656	279	0	0
T24	577	5	0	0
T25	0	825	0	0
T26	0	370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2566084	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2566084	0	0
T1	30727	101	0	0
T2	36010	190	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	16	0	0
T20	218425	1797	0	0
T21	3518	67	0	0
T22	379568	1943	0	0
T23	25656	308	0	0
T24	577	5	0	0
T25	0	825	0	0
T26	0	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1444787	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1444787	0	0
T1	30727	167	0	0
T2	36010	270	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	13	0	0
T20	218425	1937	0	0
T21	3518	60	0	0
T22	379568	1712	0	0
T23	25656	151	0	0
T24	577	4	0	0
T25	0	246	0	0
T26	0	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3011935	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3011935	0	0
T1	30727	113	0	0
T2	36010	200	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	13	0	0
T20	218425	847	0	0
T21	3518	60	0	0
T22	379568	1881	0	0
T23	25656	212	0	0
T24	577	4	0	0
T25	0	246	0	0
T26	0	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1438485	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1438485	0	0
T1	30727	202	0	0
T2	36010	130	0	0
T3	57787	1467	0	0
T4	2674	0	0	0
T5	1927	24	0	0
T20	218425	1904	0	0
T21	3518	63	0	0
T22	379568	2267	0	0
T23	25656	218	0	0
T24	577	0	0	0
T25	0	238	0	0
T26	0	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3556938	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3556938	0	0
T1	30727	102	0	0
T2	36010	116	0	0
T3	57787	1150	0	0
T4	2674	0	0	0
T5	1927	24	0	0
T20	218425	793	0	0
T21	3518	63	0	0
T22	379568	2229	0	0
T23	25656	180	0	0
T24	577	0	0	0
T25	0	238	0	0
T26	0	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1405651	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1405651	0	0
T1	30727	241	0	0
T2	36010	768	0	0
T3	57787	4264	0	0
T4	2674	0	0	0
T5	1927	9	0	0
T20	218425	1562	0	0
T21	3518	56	0	0
T22	379568	2040	0	0
T23	25656	335	0	0
T24	577	3	0	0
T25	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2580766	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2580766	0	0
T1	30727	70	0	0
T2	36010	540	0	0
T3	57787	2000	0	0
T4	2674	0	0	0
T5	1927	9	0	0
T20	218425	657	0	0
T21	3518	56	0	0
T22	379568	1754	0	0
T23	25656	331	0	0
T24	577	3	0	0
T25	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1459248	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1459248	0	0
T1	30727	237	0	0
T2	36010	267	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	4056	0	0
T21	3518	67	0	0
T22	379568	1908	0	0
T23	25656	245	0	0
T24	577	4	0	0
T25	0	505	0	0
T26	0	375	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2776780	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2776780	0	0
T1	30727	67	0	0
T2	36010	247	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	1923	0	0
T21	3518	67	0	0
T22	379568	2056	0	0
T23	25656	288	0	0
T24	577	4	0	0
T25	0	505	0	0
T26	0	401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1417333	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1417333	0	0
T1	30727	255	0	0
T2	36010	390	0	0
T3	57787	1855	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	3930	0	0
T21	3518	82	0	0
T22	379568	1858	0	0
T23	25656	259	0	0
T24	577	4	0	0
T25	0	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2860315	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2860315	0	0
T1	30727	152	0	0
T2	36010	341	0	0
T3	57787	1013	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	1913	0	0
T21	3518	82	0	0
T22	379568	1887	0	0
T23	25656	337	0	0
T24	577	4	0	0
T25	0	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1467849	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1467849	0	0
T1	30727	260	0	0
T2	36010	228	0	0
T3	57787	1571	0	0
T4	2674	246	0	0
T5	1927	12	0	0
T20	218425	1676	0	0
T21	3518	72	0	0
T22	379568	1917	0	0
T23	25656	330	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2719383	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2719383	0	0
T1	30727	110	0	0
T2	36010	216	0	0
T3	57787	872	0	0
T4	2674	246	0	0
T5	1927	12	0	0
T20	218425	775	0	0
T21	3518	72	0	0
T22	379568	1910	0	0
T23	25656	290	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1476211	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1476211	0	0
T1	30727	267	0	0
T2	36010	271	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	18	0	0
T20	218425	1814	0	0
T21	3518	73	0	0
T22	379568	2095	0	0
T23	25656	250	0	0
T24	577	5	0	0
T25	0	871	0	0
T26	0	463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3600518	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3600518	0	0
T1	30727	101	0	0
T2	36010	204	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	18	0	0
T20	218425	860	0	0
T21	3518	73	0	0
T22	379568	1894	0	0
T23	25656	265	0	0
T24	577	5	0	0
T25	0	871	0	0
T26	0	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1447196	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1447196	0	0
T1	30727	210	0	0
T2	36010	120	0	0
T3	57787	4078	0	0
T4	2674	205	0	0
T5	1927	19	0	0
T20	218425	1657	0	0
T21	3518	65	0	0
T22	379568	1956	0	0
T23	25656	218	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3488674	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3488674	0	0
T1	30727	89	0	0
T2	36010	93	0	0
T3	57787	1799	0	0
T4	2674	205	0	0
T5	1927	19	0	0
T20	218425	671	0	0
T21	3518	65	0	0
T22	379568	2150	0	0
T23	25656	215	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1454180	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1454180	0	0
T1	30727	271	0	0
T2	36010	1257	0	0
T3	57787	1418	0	0
T4	2674	205	0	0
T5	1927	13	0	0
T20	218425	3592	0	0
T21	3518	69	0	0
T22	379568	2065	0	0
T23	25656	230	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3285693	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3285693	0	0
T1	30727	119	0	0
T2	36010	1169	0	0
T3	57787	1220	0	0
T4	2674	205	0	0
T5	1927	13	0	0
T20	218425	1570	0	0
T21	3518	69	0	0
T22	379568	2137	0	0
T23	25656	170	0	0
T24	577	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1423905	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1423905	0	0
T1	30727	319	0	0
T2	36010	244	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	12	0	0
T20	218425	1584	0	0
T21	3518	60	0	0
T22	379568	8201	0	0
T23	25656	271	0	0
T24	577	8	0	0
T25	0	1333	0	0
T26	0	450	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3139564	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3139564	0	0
T1	30727	128	0	0
T2	36010	182	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	12	0	0
T20	218425	716	0	0
T21	3518	60	0	0
T22	379568	8004	0	0
T23	25656	302	0	0
T24	577	8	0	0
T25	0	1333	0	0
T26	0	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1488050	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1488050	0	0
T1	30727	252	0	0
T2	36010	288	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	6043	0	0
T21	3518	74	0	0
T22	379568	2116	0	0
T23	25656	239	0	0
T24	577	3	0	0
T25	0	1001	0	0
T26	0	457	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2958198	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2958198	0	0
T1	30727	125	0	0
T2	36010	247	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	2520	0	0
T21	3518	74	0	0
T22	379568	2207	0	0
T23	25656	198	0	0
T24	577	3	0	0
T25	0	1001	0	0
T26	0	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1443394	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1443394	0	0
T1	30727	195	0	0
T2	36010	215	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	18	0	0
T20	218425	3570	0	0
T21	3518	59	0	0
T22	379568	3534	0	0
T23	25656	198	0	0
T24	577	2	0	0
T25	0	781	0	0
T26	0	483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3665307	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3665307	0	0
T1	30727	50	0	0
T2	36010	185	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	18	0	0
T20	218425	1658	0	0
T21	3518	59	0	0
T22	379568	3658	0	0
T23	25656	204	0	0
T24	577	2	0	0
T25	0	781	0	0
T26	0	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1430787	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1430787	0	0
T1	30727	252	0	0
T2	36010	239	0	0
T3	57787	1482	0	0
T4	2674	201	0	0
T5	1927	9	0	0
T20	218425	1630	0	0
T21	3518	74	0	0
T22	379568	2211	0	0
T23	25656	246	0	0
T24	577	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3134583	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3134583	0	0
T1	30727	109	0	0
T2	36010	211	0	0
T3	57787	1221	0	0
T4	2674	201	0	0
T5	1927	9	0	0
T20	218425	824	0	0
T21	3518	74	0	0
T22	379568	2151	0	0
T23	25656	195	0	0
T24	577	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1407925	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1407925	0	0
T1	30727	281	0	0
T2	36010	241	0	0
T3	57787	1319	0	0
T4	2674	554	0	0
T5	1927	11	0	0
T20	218425	5249	0	0
T21	3518	55	0	0
T22	379568	3857	0	0
T23	25656	174	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3144224	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3144224	0	0
T1	30727	157	0	0
T2	36010	207	0	0
T3	57787	1056	0	0
T4	2674	554	0	0
T5	1927	11	0	0
T20	218425	2410	0	0
T21	3518	55	0	0
T22	379568	3752	0	0
T23	25656	128	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1454898	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1454898	0	0
T1	30727	232	0	0
T2	36010	336	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	10	0	0
T20	218425	1760	0	0
T21	3518	81	0	0
T22	379568	6039	0	0
T23	25656	300	0	0
T24	577	8	0	0
T25	0	242	0	0
T26	0	347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3233371	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3233371	0	0
T1	30727	121	0	0
T2	36010	296	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	10	0	0
T20	218425	754	0	0
T21	3518	81	0	0
T22	379568	6076	0	0
T23	25656	219	0	0
T24	577	8	0	0
T25	0	242	0	0
T26	0	347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1469348	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1469348	0	0
T1	30727	265	0	0
T2	36010	375	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	7	0	0
T20	218425	1673	0	0
T21	3518	68	0	0
T22	379568	5969	0	0
T23	25656	334	0	0
T24	577	5	0	0
T25	0	285	0	0
T26	0	313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3825338	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3825338	0	0
T1	30727	125	0	0
T2	36010	254	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	7	0	0
T20	218425	667	0	0
T21	3518	68	0	0
T22	379568	5751	0	0
T23	25656	286	0	0
T24	577	5	0	0
T25	0	285	0	0
T26	0	428	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1446958	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1446958	0	0
T1	30727	323	0	0
T2	36010	241	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	19	0	0
T20	218425	1451	0	0
T21	3518	58	0	0
T22	379568	7066	0	0
T23	25656	202	0	0
T24	577	3	0	0
T25	0	250	0	0
T26	0	398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2812129	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2812129	0	0
T1	30727	121	0	0
T2	36010	212	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	19	0	0
T20	218425	669	0	0
T21	3518	58	0	0
T22	379568	8324	0	0
T23	25656	190	0	0
T24	577	3	0	0
T25	0	250	0	0
T26	0	342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1408232	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1408232	0	0
T1	30727	235	0	0
T2	36010	255	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	3131	0	0
T21	3518	60	0	0
T22	379568	2023	0	0
T23	25656	388	0	0
T24	577	9	0	0
T25	0	230	0	0
T26	0	397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3354328	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3354328	0	0
T1	30727	90	0	0
T2	36010	205	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	11	0	0
T20	218425	1935	0	0
T21	3518	60	0	0
T22	379568	2058	0	0
T23	25656	422	0	0
T24	577	9	0	0
T25	0	230	0	0
T26	0	339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1422398	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1422398	0	0
T1	30727	202	0	0
T2	36010	641	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	10	0	0
T20	218425	3684	0	0
T21	3518	53	0	0
T22	379568	1966	0	0
T23	25656	239	0	0
T24	577	8	0	0
T25	0	1052	0	0
T26	0	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2808771	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2808771	0	0
T1	30727	131	0	0
T2	36010	588	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	10	0	0
T20	218425	1621	0	0
T21	3518	53	0	0
T22	379568	1996	0	0
T23	25656	257	0	0
T24	577	8	0	0
T25	0	1052	0	0
T26	0	417	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1424856	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1424856	0	0
T1	30727	302	0	0
T2	36010	191	0	0
T3	57787	1385	0	0
T4	2674	270	0	0
T5	1927	13	0	0
T20	218425	1769	0	0
T21	3518	75	0	0
T22	379568	4146	0	0
T23	25656	239	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3745003	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3745003	0	0
T1	30727	124	0	0
T2	36010	131	0	0
T3	57787	1146	0	0
T4	2674	270	0	0
T5	1927	13	0	0
T20	218425	617	0	0
T21	3518	75	0	0
T22	379568	4195	0	0
T23	25656	191	0	0
T24	577	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1448243	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1448243	0	0
T1	30727	190	0	0
T2	36010	218	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	14	0	0
T20	218425	1504	0	0
T21	3518	57	0	0
T22	379568	5589	0	0
T23	25656	266	0	0
T24	577	3	0	0
T25	0	713	0	0
T26	0	442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	2911465	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	2911465	0	0
T1	30727	87	0	0
T2	36010	239	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	14	0	0
T20	218425	628	0	0
T21	3518	57	0	0
T22	379568	5538	0	0
T23	25656	295	0	0
T24	577	3	0	0
T25	0	713	0	0
T26	0	470	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	1495855	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	1495855	0	0
T1	30727	309	0	0
T2	36010	298	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	14	0	0
T20	218425	1621	0	0
T21	3518	58	0	0
T22	379568	2171	0	0
T23	25656	229	0	0
T24	577	3	0	0
T25	0	476	0	0
T26	0	412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304225317	3034171	0	0
DepthKnown_A	304225317	304100623	0	0
RvalidKnown_A	304225317	304100623	0	0
WreadyKnown_A	304225317	304100623	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	3034171	0	0
T1	30727	113	0	0
T2	36010	280	0	0
T3	57787	0	0	0
T4	2674	0	0	0
T5	1927	14	0	0
T20	218425	669	0	0
T21	3518	58	0	0
T22	379568	2241	0	0
T23	25656	181	0	0
T24	577	3	0	0
T25	0	476	0	0
T26	0	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304225317	304100623	0	0
T1	30727	30717	0	0
T2	36010	34770	0	0
T3	57787	57750	0	0
T4	2674	2634	0	0
T5	1927	1886	0	0
T20	218425	218244	0	0
T21	3518	3506	0	0
T22	379568	379319	0	0
T23	25656	25629	0	0
T24	577	520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0