Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1706664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269417

1

T1

6

T2

39

T3

267

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	667571	1			T1	12		T2	75		T3	603
values[0x0]	641502	1			T1	5		T2	85		T3	621
values[0x1]	667008	1			T1	12		T2	74		T3	591

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1323778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

652303

1

T1

10

T2

79

T3

595

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6992	1			T3	7		T14	2		T15	1
valid_sources[0x01]	6931	1			T3	3		T16	53		T19	13
valid_sources[0x02]	6907	1			T3	8		T15	2		T16	63
valid_sources[0x03]	6802	1			T3	8		T14	1		T17	1
valid_sources[0x04]	7471	1			T3	7		T16	58		T19	12
valid_sources[0x05]	8375	1			T3	7		T16	85		T20	8
valid_sources[0x06]	7627	1			T3	21		T14	1		T15	1
valid_sources[0x07]	7243	1			T3	12		T17	3		T18	2
valid_sources[0x08]	6792	1			T3	3		T13	9		T16	72
valid_sources[0x09]	7781	1			T3	27		T13	8		T15	1
valid_sources[0x0a]	8054	1			T3	11		T17	2		T18	2
valid_sources[0x0b]	7727	1			T2	13		T3	1		T15	3
valid_sources[0x0c]	8452	1			T2	12		T3	4		T13	12
valid_sources[0x0d]	7650	1			T3	14		T16	89		T19	11
valid_sources[0x0e]	7614	1			T1	1		T3	4		T4	34
valid_sources[0x0f]	7476	1			T3	13		T16	58		T20	3
valid_sources[0x10]	7232	1			T1	1		T3	2		T15	4
valid_sources[0x11]	7935	1			T3	12		T13	27		T18	1
valid_sources[0x12]	6637	1			T1	1		T3	5		T18	1
valid_sources[0x13]	7697	1			T3	2		T16	53		T19	12
valid_sources[0x14]	7137	1			T1	1		T3	2		T17	3
valid_sources[0x15]	8937	1			T3	5		T13	34		T17	2
valid_sources[0x16]	6678	1			T3	2		T4	154		T17	8
valid_sources[0x17]	7718	1			T3	6		T16	90		T19	20
valid_sources[0x18]	7497	1			T3	9		T13	10		T15	3
valid_sources[0x19]	7182	1			T3	2		T13	21		T15	1
valid_sources[0x1a]	7410	1			T3	17		T14	1		T16	84
valid_sources[0x1b]	7944	1			T1	1		T3	11		T15	1
valid_sources[0x1c]	7973	1			T3	2		T16	53		T20	1
valid_sources[0x1d]	8523	1			T3	7		T14	1		T18	1
valid_sources[0x1e]	7287	1			T3	10		T16	81		T19	10
valid_sources[0x1f]	7669	1			T3	6		T13	31		T14	1
valid_sources[0x20]	7660	1			T3	1		T16	86		T21	9
valid_sources[0x21]	7400	1			T3	2		T13	20		T17	3
valid_sources[0x22]	7904	1			T2	22		T3	1		T16	52
valid_sources[0x23]	8279	1			T3	14		T4	33		T16	83
valid_sources[0x24]	7534	1			T2	12		T3	11		T13	13
valid_sources[0x25]	8965	1			T2	5		T3	13		T15	1
valid_sources[0x26]	7763	1			T1	1		T3	11		T14	2
valid_sources[0x27]	7285	1			T3	1		T16	48		T20	2
valid_sources[0x28]	7436	1			T3	6		T4	87		T15	2
valid_sources[0x29]	7800	1			T3	10		T14	1		T15	2
valid_sources[0x2a]	8171	1			T3	2		T16	68		T23	1
valid_sources[0x2b]	6879	1			T1	1		T3	10		T14	1
valid_sources[0x2c]	8132	1			T3	1		T13	10		T18	1
valid_sources[0x2d]	6983	1			T1	1		T2	10		T3	6
valid_sources[0x2e]	7289	1			T3	14		T4	72		T13	27
valid_sources[0x2f]	8064	1			T3	14		T14	2		T15	1
valid_sources[0x30]	7393	1			T3	8		T15	1		T16	74
valid_sources[0x31]	8368	1			T1	1		T3	4		T18	2
valid_sources[0x32]	7734	1			T3	3		T4	494		T13	6
valid_sources[0x33]	8090	1			T3	16		T4	233		T16	73
valid_sources[0x34]	7119	1			T3	3		T15	4		T16	77
valid_sources[0x35]	8170	1			T3	14		T15	4		T18	1
valid_sources[0x36]	6793	1			T3	10		T15	3		T17	4
valid_sources[0x37]	8007	1			T1	1		T3	1		T15	2
valid_sources[0x38]	7712	1			T3	7		T13	16		T14	2
valid_sources[0x39]	8146	1			T2	6		T3	9		T13	16
valid_sources[0x3a]	7009	1			T3	2		T18	3		T16	61
valid_sources[0x3b]	7339	1			T3	2		T17	2		T16	75
valid_sources[0x3c]	8607	1			T13	16		T15	5		T17	1
valid_sources[0x3d]	8302	1			T3	3		T15	2		T16	71
valid_sources[0x3e]	9120	1			T3	9		T13	15		T17	1
valid_sources[0x3f]	8359	1			T3	10		T17	1		T18	2
valid_sources[0x40]	7608	1			T3	5		T14	1		T18	1
valid_sources[0x41]	7442	1			T3	7		T13	11		T18	1
valid_sources[0x42]	8315	1			T3	2		T16	54		T20	1
valid_sources[0x43]	7842	1			T3	7		T4	152		T15	1
valid_sources[0x44]	7737	1			T3	1		T16	82		T22	1
valid_sources[0x45]	6998	1			T18	1		T16	68		T20	2
valid_sources[0x46]	7291	1			T3	13		T15	2		T16	82
valid_sources[0x47]	7697	1			T3	13		T14	1		T18	1
valid_sources[0x48]	7905	1			T3	16		T18	2		T16	60
valid_sources[0x49]	7057	1			T3	9		T15	1		T16	63
valid_sources[0x4a]	7553	1			T3	3		T13	12		T15	3
valid_sources[0x4b]	7331	1			T13	19		T15	1		T17	2
valid_sources[0x4c]	10190	1			T3	12		T13	17		T16	87
valid_sources[0x4d]	7547	1			T3	8		T16	58		T20	10
valid_sources[0x4e]	8392	1			T1	1		T3	6		T16	79
valid_sources[0x4f]	7238	1			T3	9		T15	1		T16	75
valid_sources[0x50]	7742	1			T3	2		T16	55		T21	4
valid_sources[0x51]	7086	1			T3	2		T13	9		T18	5
valid_sources[0x52]	8065	1			T3	2		T14	1		T16	65
valid_sources[0x53]	7339	1			T3	6		T4	56		T16	68
valid_sources[0x54]	7686	1			T3	10		T15	3		T18	1
valid_sources[0x55]	7501	1			T3	8		T15	1		T16	63
valid_sources[0x56]	7645	1			T3	8		T13	12		T17	1
valid_sources[0x57]	7798	1			T3	12		T13	35		T15	2
valid_sources[0x58]	7193	1			T3	8		T13	27		T16	70
valid_sources[0x59]	7844	1			T3	9		T16	58		T19	14
valid_sources[0x5a]	8067	1			T3	8		T4	378		T16	58
valid_sources[0x5b]	7798	1			T2	9		T3	13		T15	1
valid_sources[0x5c]	8476	1			T3	7		T15	2		T18	1
valid_sources[0x5d]	6998	1			T3	6		T16	76		T20	1
valid_sources[0x5e]	6897	1			T2	9		T3	3		T15	1
valid_sources[0x5f]	7360	1			T3	11		T13	14		T14	1
valid_sources[0x60]	7198	1			T2	20		T3	5		T13	19
valid_sources[0x61]	8002	1			T3	7		T13	16		T16	74
valid_sources[0x62]	7259	1			T3	7		T4	99		T14	1
valid_sources[0x63]	7535	1			T3	3		T13	27		T14	1
valid_sources[0x64]	8448	1			T3	1		T16	97		T19	33
valid_sources[0x65]	8766	1			T3	16		T15	1		T18	2
valid_sources[0x66]	7817	1			T3	3		T14	1		T18	1
valid_sources[0x67]	7247	1			T3	8		T16	44		T22	1
valid_sources[0x68]	6937	1			T3	2		T13	8		T15	1
valid_sources[0x69]	8442	1			T3	2		T16	59		T20	1
valid_sources[0x6a]	7585	1			T3	7		T15	2		T17	1
valid_sources[0x6b]	7906	1			T3	5		T15	2		T16	69
valid_sources[0x6c]	7479	1			T3	11		T16	58		T19	31
valid_sources[0x6d]	7794	1			T3	7		T14	1		T18	1
valid_sources[0x6e]	8293	1			T3	6		T13	12		T15	1
valid_sources[0x6f]	7800	1			T3	5		T15	2		T17	1
valid_sources[0x70]	7340	1			T2	12		T3	13		T15	1
valid_sources[0x71]	7744	1			T1	1		T3	16		T13	13
valid_sources[0x72]	7640	1			T3	8		T4	64		T13	10
valid_sources[0x73]	8262	1			T3	3		T16	63		T22	1
valid_sources[0x74]	6948	1			T3	2		T16	45		T20	1
valid_sources[0x75]	7706	1			T3	2		T16	60		T20	1
valid_sources[0x76]	8061	1			T3	5		T17	2		T16	61
valid_sources[0x77]	8391	1			T3	6		T15	1		T16	71
valid_sources[0x78]	7677	1			T1	1		T3	9		T15	2
valid_sources[0x79]	8390	1			T1	1		T3	11		T14	1
valid_sources[0x7a]	7522	1			T3	7		T15	4		T18	1
valid_sources[0x7b]	8215	1			T3	3		T16	56		T19	13
valid_sources[0x7c]	7255	1			T3	9		T14	1		T16	71
valid_sources[0x7d]	7842	1			T3	8		T13	5		T15	1
valid_sources[0x7e]	7863	1			T3	8		T13	18		T14	1
valid_sources[0x7f]	8451	1			T3	8		T17	3		T18	1
valid_sources[0x80]	7702	1			T3	10		T15	2		T17	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28380

1

T1

3

T2

5

T3

21

values[0x0]

all_enables

biggest_size

212871

1

T1

3

T2

33

T3

208

values[0x1]

all_enables

biggest_size

28166

1

T2

1

T3

38

T4

40