Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	302352345	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	302352345	0	0
T1	1049664	18594	0	0
T2	499408	7438	0	0
T3	52192168	928301	0	0
T4	347592	14967	0	0
T13	2082752	28402	0	0
T14	2331504	50272	0	0
T15	6747776	166856	0	0
T16	1769712	74642	0	0
T17	7209888	119950	0	0
T18	23576	595	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1049664	1003016	0	0
T2	499408	497504	0	0
T3	52192168	52191776	0	0
T4	347592	345632	0	0
T13	2082752	2079224	0	0
T14	2331504	2330048	0	0
T15	6747776	6707232	0	0
T16	1769712	1762320	0	0
T17	7209888	7207480	0	0
T18	23576	22008	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1049664	1003016	0	0
T2	499408	497504	0	0
T3	52192168	52191776	0	0
T4	347592	345632	0	0
T13	2082752	2079224	0	0
T14	2331504	2330048	0	0
T15	6747776	6707232	0	0
T16	1769712	1762320	0	0
T17	7209888	7207480	0	0
T18	23576	22008	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1049664	1003016	0	0
T2	499408	497504	0	0
T3	52192168	52191776	0	0
T4	347592	345632	0	0
T13	2082752	2079224	0	0
T14	2331504	2330048	0	0
T15	6747776	6707232	0	0
T16	1769712	1762320	0	0
T17	7209888	7207480	0	0
T18	23576	22008	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	110199863	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	110199863	0	0
T1	18744	8097	0	0
T2	8918	1876	0	0
T3	932003	909176	0	0
T4	6207	5835	0	0
T13	37192	7480	0	0
T14	41634	21656	0	0
T15	120496	67594	0	0
T16	31602	30927	0	0
T17	128748	50470	0	0
T18	421	232	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	78457663	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	78457663	0	0
T1	18744	2666	0	0
T2	8918	1844	0	0
T3	932003	5600	0	0
T4	6207	3044	0	0
T13	37192	6736	0	0
T14	41634	8866	0	0
T15	120496	32056	0	0
T16	31602	17179	0	0
T17	128748	16219	0	0
T18	421	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1312805	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1312805	0	0
T1	18744	115	0	0
T2	8918	55	0	0
T3	932003	224	0	0
T4	6207	101	0	0
T13	37192	304	0	0
T14	41634	452	0	0
T15	120496	976	0	0
T16	31602	515	0	0
T17	128748	591	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3007238	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3007238	0	0
T1	18744	44	0	0
T2	8918	63	0	0
T3	932003	60	0	0
T4	6207	101	0	0
T13	37192	327	0	0
T14	41634	368	0	0
T15	120496	1003	0	0
T16	31602	515	0	0
T17	128748	537	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1269830	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1269830	0	0
T1	18744	79	0	0
T2	8918	85	0	0
T3	932003	286	0	0
T4	6207	99	0	0
T13	37192	220	0	0
T14	41634	402	0	0
T15	120496	1003	0	0
T16	31602	586	0	0
T17	128748	853	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2721944	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2721944	0	0
T1	18744	18	0	0
T2	8918	88	0	0
T3	932003	715	0	0
T4	6207	99	0	0
T13	37192	174	0	0
T14	41634	345	0	0
T15	120496	857	0	0
T16	31602	586	0	0
T17	128748	126	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1324395	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1324395	0	0
T1	18744	141	0	0
T2	8918	43	0	0
T3	932003	331	0	0
T4	6207	104	0	0
T13	37192	290	0	0
T14	41634	379	0	0
T15	120496	1079	0	0
T16	31602	564	0	0
T17	128748	2408	0	0
T18	421	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2439535	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2439535	0	0
T1	18744	68	0	0
T2	8918	46	0	0
T3	932003	294	0	0
T4	6207	104	0	0
T13	37192	285	0	0
T14	41634	375	0	0
T15	120496	858	0	0
T16	31602	564	0	0
T17	128748	1078	0	0
T18	421	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1393117	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1393117	0	0
T1	18744	115	0	0
T2	8918	90	0	0
T3	932003	176	0	0
T4	6207	117	0	0
T13	37192	295	0	0
T14	41634	419	0	0
T15	120496	2357	0	0
T16	31602	345	0	0
T17	128748	2623	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3925083	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3925083	0	0
T1	18744	96	0	0
T2	8918	72	0	0
T3	932003	43	0	0
T4	6207	117	0	0
T13	37192	283	0	0
T14	41634	306	0	0
T15	120496	2368	0	0
T16	31602	345	0	0
T17	128748	1159	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1344979	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1344979	0	0
T1	18744	265	0	0
T2	8918	95	0	0
T3	932003	386	0	0
T4	6207	127	0	0
T13	37192	221	0	0
T14	41634	510	0	0
T15	120496	1095	0	0
T16	31602	610	0	0
T17	128748	1746	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2890781	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2890781	0	0
T1	18744	136	0	0
T2	8918	89	0	0
T3	932003	87	0	0
T4	6207	127	0	0
T13	37192	208	0	0
T14	41634	386	0	0
T15	120496	1056	0	0
T16	31602	610	0	0
T17	128748	400	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1337922	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1337922	0	0
T1	18744	121	0	0
T2	8918	105	0	0
T3	932003	253	0	0
T4	6207	103	0	0
T13	37192	283	0	0
T14	41634	460	0	0
T15	120496	3239	0	0
T16	31602	317	0	0
T17	128748	788	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2711974	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2711974	0	0
T1	18744	37	0	0
T2	8918	98	0	0
T3	932003	66	0	0
T4	6207	103	0	0
T13	37192	228	0	0
T14	41634	365	0	0
T15	120496	2575	0	0
T16	31602	317	0	0
T17	128748	828	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1268279	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1268279	0	0
T1	18744	109	0	0
T2	8918	94	0	0
T3	932003	262	0	0
T4	6207	114	0	0
T13	37192	353	0	0
T14	41634	417	0	0
T15	120496	864	0	0
T16	31602	581	0	0
T17	128748	1310	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2698572	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2698572	0	0
T1	18744	66	0	0
T2	8918	118	0	0
T3	932003	58	0	0
T4	6207	114	0	0
T13	37192	335	0	0
T14	41634	262	0	0
T15	120496	755	0	0
T16	31602	581	0	0
T17	128748	7	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1356577	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1356577	0	0
T1	18744	255	0	0
T2	8918	116	0	0
T3	932003	341	0	0
T4	6207	115	0	0
T13	37192	350	0	0
T14	41634	306	0	0
T15	120496	2948	0	0
T16	31602	500	0	0
T17	128748	840	0	0
T18	421	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2456271	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2456271	0	0
T1	18744	96	0	0
T2	8918	77	0	0
T3	932003	69	0	0
T4	6207	115	0	0
T13	37192	257	0	0
T14	41634	308	0	0
T15	120496	2690	0	0
T16	31602	500	0	0
T17	128748	461	0	0
T18	421	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1308670	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1308670	0	0
T1	18744	198	0	0
T2	8918	107	0	0
T3	932003	289	0	0
T4	6207	113	0	0
T13	37192	323	0	0
T14	41634	352	0	0
T15	120496	887	0	0
T16	31602	831	0	0
T17	128748	1428	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2339038	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2339038	0	0
T1	18744	89	0	0
T2	8918	111	0	0
T3	932003	64	0	0
T4	6207	113	0	0
T13	37192	235	0	0
T14	41634	279	0	0
T15	120496	846	0	0
T16	31602	831	0	0
T17	128748	331	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1337432	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1337432	0	0
T1	18744	148	0	0
T2	8918	71	0	0
T3	932003	256	0	0
T4	6207	114	0	0
T13	37192	212	0	0
T14	41634	287	0	0
T15	120496	955	0	0
T16	31602	318	0	0
T17	128748	634	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1963458	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1963458	0	0
T1	18744	77	0	0
T2	8918	42	0	0
T3	932003	328	0	0
T4	6207	114	0	0
T13	37192	129	0	0
T14	41634	265	0	0
T15	120496	852	0	0
T16	31602	318	0	0
T17	128748	944	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1296737	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1296737	0	0
T1	18744	301	0	0
T2	8918	103	0	0
T3	932003	302	0	0
T4	6207	115	0	0
T13	37192	358	0	0
T14	41634	393	0	0
T15	120496	763	0	0
T16	31602	581	0	0
T17	128748	1418	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3299502	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3299502	0	0
T1	18744	142	0	0
T2	8918	119	0	0
T3	932003	75	0	0
T4	6207	115	0	0
T13	37192	299	0	0
T14	41634	343	0	0
T15	120496	663	0	0
T16	31602	581	0	0
T17	128748	823	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1349108	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1349108	0	0
T1	18744	111	0	0
T2	8918	55	0	0
T3	932003	298	0	0
T4	6207	119	0	0
T13	37192	259	0	0
T14	41634	416	0	0
T15	120496	1031	0	0
T16	31602	304	0	0
T17	128748	1285	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2933900	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2933900	0	0
T1	18744	51	0	0
T2	8918	45	0	0
T3	932003	73	0	0
T4	6207	119	0	0
T13	37192	232	0	0
T14	41634	360	0	0
T15	120496	925	0	0
T16	31602	304	0	0
T17	128748	811	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1359034	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1359034	0	0
T1	18744	209	0	0
T2	8918	80	0	0
T3	932003	300	0	0
T4	6207	89	0	0
T13	37192	306	0	0
T14	41634	338	0	0
T15	120496	713	0	0
T16	31602	518	0	0
T17	128748	757	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3308211	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3308211	0	0
T1	18744	96	0	0
T2	8918	62	0	0
T3	932003	205	0	0
T4	6207	89	0	0
T13	37192	268	0	0
T14	41634	282	0	0
T15	120496	597	0	0
T16	31602	518	0	0
T17	128748	151	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1333348	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1333348	0	0
T1	18744	353	0	0
T2	8918	93	0	0
T3	932003	337	0	0
T4	6207	129	0	0
T13	37192	312	0	0
T14	41634	435	0	0
T15	120496	1034	0	0
T16	31602	527	0	0
T17	128748	1470	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2701590	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2701590	0	0
T1	18744	245	0	0
T2	8918	121	0	0
T3	932003	73	0	0
T4	6207	129	0	0
T13	37192	263	0	0
T14	41634	432	0	0
T15	120496	882	0	0
T16	31602	527	0	0
T17	128748	988	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1369330	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1369330	0	0
T1	18744	151	0	0
T2	8918	90	0	0
T3	932003	293	0	0
T4	6207	104	0	0
T13	37192	200	0	0
T14	41634	528	0	0
T15	120496	872	0	0
T16	31602	301	0	0
T17	128748	2147	0	0
T18	421	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2871724	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2871724	0	0
T1	18744	49	0	0
T2	8918	81	0	0
T3	932003	484	0	0
T4	6207	104	0	0
T13	37192	135	0	0
T14	41634	350	0	0
T15	120496	832	0	0
T16	31602	301	0	0
T17	128748	1075	0	0
T18	421	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1381655	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1381655	0	0
T1	18744	105	0	0
T2	8918	46	0	0
T3	932003	367	0	0
T4	6207	103	0	0
T13	37192	208	0	0
T14	41634	404	0	0
T15	120496	3223	0	0
T16	31602	283	0	0
T17	128748	868	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3364591	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3364591	0	0
T1	18744	69	0	0
T2	8918	68	0	0
T3	932003	80	0	0
T4	6207	103	0	0
T13	37192	210	0	0
T14	41634	363	0	0
T15	120496	2471	0	0
T16	31602	283	0	0
T17	128748	634	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1335525	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1335525	0	0
T1	18744	74	0	0
T2	8918	22	0	0
T3	932003	337	0	0
T4	6207	125	0	0
T13	37192	268	0	0
T14	41634	364	0	0
T15	120496	976	0	0
T16	31602	308	0	0
T17	128748	765	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3005880	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3005880	0	0
T1	18744	72	0	0
T2	8918	39	0	0
T3	932003	78	0	0
T4	6207	125	0	0
T13	37192	234	0	0
T14	41634	315	0	0
T15	120496	947	0	0
T16	31602	308	0	0
T17	128748	110	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1371100	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1371100	0	0
T1	18744	207	0	0
T2	8918	41	0	0
T3	932003	321	0	0
T4	6207	129	0	0
T13	37192	218	0	0
T14	41634	419	0	0
T15	120496	1190	0	0
T16	31602	788	0	0
T17	128748	1876	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3407628	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3407628	0	0
T1	18744	138	0	0
T2	8918	49	0	0
T3	932003	74	0	0
T4	6207	129	0	0
T13	37192	226	0	0
T14	41634	307	0	0
T15	120496	955	0	0
T16	31602	788	0	0
T17	128748	994	0	0
T18	421	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1336589	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1336589	0	0
T1	18744	169	0	0
T2	8918	55	0	0
T3	932003	323	0	0
T4	6207	108	0	0
T13	37192	246	0	0
T14	41634	442	0	0
T15	120496	813	0	0
T16	31602	609	0	0
T17	128748	397	0	0
T18	421	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3198333	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3198333	0	0
T1	18744	56	0	0
T2	8918	25	0	0
T3	932003	74	0	0
T4	6207	108	0	0
T13	37192	168	0	0
T14	41634	250	0	0
T15	120496	623	0	0
T16	31602	609	0	0
T17	128748	277	0	0
T18	421	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1346592	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1346592	0	0
T1	18744	180	0	0
T2	8918	28	0	0
T3	932003	301	0	0
T4	6207	97	0	0
T13	37192	289	0	0
T14	41634	391	0	0
T15	120496	2711	0	0
T16	31602	329	0	0
T17	128748	484	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3582595	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3582595	0	0
T1	18744	124	0	0
T2	8918	43	0	0
T3	932003	61	0	0
T4	6207	97	0	0
T13	37192	356	0	0
T14	41634	273	0	0
T15	120496	2330	0	0
T16	31602	329	0	0
T17	128748	178	0	0
T18	421	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1333987	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1333987	0	0
T1	18744	182	0	0
T2	8918	41	0	0
T3	932003	301	0	0
T4	6207	118	0	0
T13	37192	222	0	0
T14	41634	276	0	0
T15	120496	918	0	0
T16	31602	563	0	0
T17	128748	1462	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2909348	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2909348	0	0
T1	18744	139	0	0
T2	8918	64	0	0
T3	932003	1147	0	0
T4	6207	118	0	0
T13	37192	215	0	0
T14	41634	267	0	0
T15	120496	888	0	0
T16	31602	563	0	0
T17	128748	78	0	0
T18	421	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1326824	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1326824	0	0
T1	18744	193	0	0
T2	8918	73	0	0
T3	932003	278	0	0
T4	6207	96	0	0
T13	37192	281	0	0
T14	41634	462	0	0
T15	120496	899	0	0
T16	31602	316	0	0
T17	128748	1699	0	0
T18	421	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2829075	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2829075	0	0
T1	18744	57	0	0
T2	8918	75	0	0
T3	932003	67	0	0
T4	6207	96	0	0
T13	37192	268	0	0
T14	41634	376	0	0
T15	120496	771	0	0
T16	31602	316	0	0
T17	128748	216	0	0
T18	421	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1345079	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1345079	0	0
T1	18744	144	0	0
T2	8918	80	0	0
T3	932003	306	0	0
T4	6207	111	0	0
T13	37192	317	0	0
T14	41634	457	0	0
T15	120496	1001	0	0
T16	31602	299	0	0
T17	128748	4176	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1978815	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1978815	0	0
T1	18744	53	0	0
T2	8918	54	0	0
T3	932003	118	0	0
T4	6207	111	0	0
T13	37192	332	0	0
T14	41634	422	0	0
T15	120496	996	0	0
T16	31602	299	0	0
T17	128748	1713	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1350315	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1350315	0	0
T1	18744	213	0	0
T2	8918	91	0	0
T3	932003	278	0	0
T4	6207	141	0	0
T13	37192	284	0	0
T14	41634	348	0	0
T15	120496	982	0	0
T16	31602	321	0	0
T17	128748	1425	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	3301428	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	3301428	0	0
T1	18744	78	0	0
T2	8918	58	0	0
T3	932003	68	0	0
T4	6207	141	0	0
T13	37192	261	0	0
T14	41634	361	0	0
T15	120496	974	0	0
T16	31602	321	0	0
T17	128748	814	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1357931	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1357931	0	0
T1	18744	222	0	0
T2	8918	6	0	0
T3	932003	226	0	0
T4	6207	122	0	0
T13	37192	332	0	0
T14	41634	489	0	0
T15	120496	973	0	0
T16	31602	1134	0	0
T17	128748	1661	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2474332	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2474332	0	0
T1	18744	60	0	0
T2	8918	18	0	0
T3	932003	53	0	0
T4	6207	122	0	0
T13	37192	229	0	0
T14	41634	320	0	0
T15	120496	924	0	0
T16	31602	1134	0	0
T17	128748	923	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1310459	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1310459	0	0
T1	18744	95	0	0
T2	8918	32	0	0
T3	932003	266	0	0
T4	6207	106	0	0
T13	37192	197	0	0
T14	41634	384	0	0
T15	120496	926	0	0
T16	31602	317	0	0
T17	128748	1072	0	0
T18	421	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2669201	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2669201	0	0
T1	18744	64	0	0
T2	8918	19	0	0
T3	932003	523	0	0
T4	6207	106	0	0
T13	37192	150	0	0
T14	41634	303	0	0
T15	120496	919	0	0
T16	31602	317	0	0
T17	128748	351	0	0
T18	421	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	1349847	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	1349847	0	0
T1	18744	785	0	0
T2	8918	78	0	0
T3	932003	289	0	0
T4	6207	125	0	0
T13	37192	327	0	0
T14	41634	354	0	0
T15	120496	1137	0	0
T16	31602	603	0	0
T17	128748	859	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	279115612	2597306	0	0
DepthKnown_A	279115612	279001412	0	0
RvalidKnown_A	279115612	279001412	0	0
WreadyKnown_A	279115612	279001412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	2597306	0	0
T1	18744	371	0	0
T2	8918	99	0	0
T3	932003	561	0	0
T4	6207	125	0	0
T13	37192	404	0	0
T14	41634	283	0	0
T15	120496	1084	0	0
T16	31602	603	0	0
T17	128748	212	0	0
T18	421	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279115612	279001412	0	0
T1	18744	17911	0	0
T2	8918	8884	0	0
T3	932003	931996	0	0
T4	6207	6172	0	0
T13	37192	37129	0	0
T14	41634	41608	0	0
T15	120496	119772	0	0
T16	31602	31470	0	0
T17	128748	128705	0	0
T18	421	393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0