Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1689572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265883

1

T1

22

T2

2

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	662048	1			T1	54		T2	18		T3	74
values[0x0]	631877	1			T1	50		T2	6		T3	69
values[0x1]	661530	1			T1	50		T2	26		T3	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1309490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

645965

1

T1

48

T2

11

T3

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7501	1			T2	1		T5	7		T4	17
valid_sources[0x01]	8260	1			T5	2		T4	13		T11	1
valid_sources[0x02]	7603	1			T2	1		T5	13		T4	5
valid_sources[0x03]	6862	1			T5	3		T4	13		T11	2
valid_sources[0x04]	7023	1			T2	1		T5	3		T12	1
valid_sources[0x05]	7409	1			T5	10		T12	1		T8	84
valid_sources[0x06]	6653	1			T2	1		T5	9		T8	71
valid_sources[0x07]	7813	1			T5	11		T4	5		T8	87
valid_sources[0x08]	6826	1			T5	6		T12	1		T8	70
valid_sources[0x09]	8154	1			T5	4		T11	1		T8	96
valid_sources[0x0a]	7584	1			T5	6		T4	16		T12	1
valid_sources[0x0b]	7720	1			T5	6		T8	117		T9	4
valid_sources[0x0c]	6898	1			T5	7		T12	1		T8	70
valid_sources[0x0d]	8257	1			T5	8		T4	14		T11	12
valid_sources[0x0e]	7370	1			T5	14		T4	10		T11	10
valid_sources[0x0f]	9360	1			T5	8		T4	36		T11	15
valid_sources[0x10]	7904	1			T2	1		T5	8		T4	19
valid_sources[0x11]	8441	1			T5	19		T4	8		T8	103
valid_sources[0x12]	7205	1			T5	3		T11	8		T12	2
valid_sources[0x13]	8071	1			T8	100		T9	2		T6	140
valid_sources[0x14]	7239	1			T5	8		T4	32		T11	4
valid_sources[0x15]	6825	1			T5	9		T12	1		T8	73
valid_sources[0x16]	6925	1			T3	16		T5	14		T4	7
valid_sources[0x17]	6889	1			T2	1		T5	4		T4	21
valid_sources[0x18]	7351	1			T2	1		T5	5		T4	14
valid_sources[0x19]	7552	1			T5	4		T4	25		T8	102
valid_sources[0x1a]	7211	1			T5	7		T4	19		T12	1
valid_sources[0x1b]	7317	1			T5	10		T4	6		T12	1
valid_sources[0x1c]	7911	1			T5	6		T8	100		T9	8
valid_sources[0x1d]	9163	1			T5	15		T11	2		T8	59
valid_sources[0x1e]	7006	1			T2	1		T5	3		T12	1
valid_sources[0x1f]	7450	1			T5	7		T4	16		T11	21
valid_sources[0x20]	8490	1			T3	7		T5	10		T4	18
valid_sources[0x21]	7645	1			T5	2		T4	16		T11	9
valid_sources[0x22]	7362	1			T5	6		T8	109		T9	1
valid_sources[0x23]	7841	1			T5	7		T8	103		T9	5
valid_sources[0x24]	8308	1			T5	6		T4	11		T11	6
valid_sources[0x25]	7380	1			T2	1		T5	6		T11	8
valid_sources[0x26]	7028	1			T5	4		T4	19		T11	4
valid_sources[0x27]	8219	1			T5	4		T4	12		T12	1
valid_sources[0x28]	7655	1			T5	13		T12	2		T8	65
valid_sources[0x29]	7720	1			T5	4		T4	10		T11	10
valid_sources[0x2a]	7841	1			T2	1		T5	2		T8	86
valid_sources[0x2b]	8041	1			T5	2		T4	24		T12	1
valid_sources[0x2c]	8720	1			T2	1		T5	6		T11	16
valid_sources[0x2d]	7045	1			T3	14		T5	13		T8	68
valid_sources[0x2e]	7226	1			T5	4		T12	3		T8	143
valid_sources[0x2f]	7642	1			T5	6		T12	1		T8	162
valid_sources[0x30]	7613	1			T5	16		T8	84		T9	4
valid_sources[0x31]	6930	1			T5	13		T4	38		T11	6
valid_sources[0x32]	8125	1			T5	5		T12	1		T8	138
valid_sources[0x33]	7534	1			T5	2		T8	109		T9	3
valid_sources[0x34]	6893	1			T3	19		T5	5		T12	1
valid_sources[0x35]	7826	1			T5	2		T4	14		T12	2
valid_sources[0x36]	7376	1			T5	11		T12	1		T8	64
valid_sources[0x37]	9258	1			T5	9		T4	19		T11	4
valid_sources[0x38]	7822	1			T5	9		T4	15		T11	9
valid_sources[0x39]	7055	1			T5	5		T11	3		T8	84
valid_sources[0x3a]	7367	1			T5	7		T4	13		T11	23
valid_sources[0x3b]	6883	1			T5	12		T4	15		T12	1
valid_sources[0x3c]	7168	1			T2	2		T3	12		T5	7
valid_sources[0x3d]	7355	1			T2	1		T5	5		T4	10
valid_sources[0x3e]	8290	1			T5	5		T8	65		T9	2
valid_sources[0x3f]	7390	1			T5	3		T4	8		T12	2
valid_sources[0x40]	7496	1			T5	6		T4	6		T8	91
valid_sources[0x41]	7890	1			T5	13		T12	1		T8	76
valid_sources[0x42]	7516	1			T1	23		T3	18		T5	4
valid_sources[0x43]	8088	1			T5	10		T4	13		T11	2
valid_sources[0x44]	8326	1			T3	10		T4	5		T12	1
valid_sources[0x45]	7412	1			T5	3		T4	28		T11	1
valid_sources[0x46]	8298	1			T3	14		T5	2		T11	3
valid_sources[0x47]	7689	1			T5	11		T12	1		T8	95
valid_sources[0x48]	8089	1			T5	2		T11	10		T12	1
valid_sources[0x49]	7363	1			T5	7		T4	11		T11	7
valid_sources[0x4a]	8125	1			T5	10		T4	8		T11	10
valid_sources[0x4b]	6961	1			T2	3		T5	3		T4	33
valid_sources[0x4c]	7468	1			T2	1		T3	15		T5	11
valid_sources[0x4d]	8273	1			T5	12		T4	52		T12	1
valid_sources[0x4e]	7904	1			T2	1		T5	10		T8	103
valid_sources[0x4f]	7347	1			T5	6		T4	10		T11	5
valid_sources[0x50]	9191	1			T5	4		T11	12		T12	1
valid_sources[0x51]	8472	1			T5	9		T4	20		T8	97
valid_sources[0x52]	8840	1			T5	11		T4	6		T12	1
valid_sources[0x53]	8171	1			T5	4		T4	13		T8	99
valid_sources[0x54]	7332	1			T5	12		T12	1		T8	119
valid_sources[0x55]	8229	1			T5	13		T4	14		T11	8
valid_sources[0x56]	8353	1			T5	5		T11	4		T12	2
valid_sources[0x57]	7041	1			T5	16		T4	17		T11	2
valid_sources[0x58]	7875	1			T5	5		T8	109		T9	6
valid_sources[0x59]	7181	1			T5	8		T4	27		T8	76
valid_sources[0x5a]	6690	1			T5	9		T11	1		T8	100
valid_sources[0x5b]	8094	1			T5	8		T12	2		T8	60
valid_sources[0x5c]	7492	1			T5	7		T4	15		T8	76
valid_sources[0x5d]	6829	1			T5	3		T4	17		T11	4
valid_sources[0x5e]	7398	1			T2	1		T5	4		T8	111
valid_sources[0x5f]	7098	1			T3	5		T5	2		T11	13
valid_sources[0x60]	7206	1			T5	20		T11	15		T12	1
valid_sources[0x61]	6837	1			T5	7		T11	6		T8	96
valid_sources[0x62]	7067	1			T5	7		T4	35		T11	16
valid_sources[0x63]	8147	1			T5	4		T4	7		T11	1
valid_sources[0x64]	8156	1			T5	5		T4	29		T12	1
valid_sources[0x65]	8124	1			T5	3		T11	9		T12	1
valid_sources[0x66]	7596	1			T5	4		T4	20		T8	79
valid_sources[0x67]	7286	1			T5	1		T12	1		T8	105
valid_sources[0x68]	8279	1			T5	5		T11	14		T8	113
valid_sources[0x69]	7552	1			T2	1		T5	11		T4	20
valid_sources[0x6a]	8700	1			T5	9		T4	11		T11	2
valid_sources[0x6b]	6981	1			T5	5		T8	82		T9	3
valid_sources[0x6c]	7424	1			T5	3		T11	9		T8	143
valid_sources[0x6d]	7110	1			T5	16		T4	8		T11	6
valid_sources[0x6e]	8350	1			T5	10		T4	25		T11	3
valid_sources[0x6f]	7661	1			T5	4		T4	6		T8	41
valid_sources[0x70]	7150	1			T3	14		T5	6		T8	73
valid_sources[0x71]	7791	1			T5	13		T11	15		T12	1
valid_sources[0x72]	6746	1			T5	3		T8	81		T9	7
valid_sources[0x73]	7743	1			T5	2		T8	112		T9	2
valid_sources[0x74]	7242	1			T5	4		T4	19		T11	2
valid_sources[0x75]	6994	1			T5	8		T8	146		T9	2
valid_sources[0x76]	7750	1			T5	9		T8	102		T9	5
valid_sources[0x77]	7545	1			T5	6		T11	2		T8	83
valid_sources[0x78]	8060	1			T5	1		T4	28		T11	10
valid_sources[0x79]	7584	1			T2	1		T5	8		T4	24
valid_sources[0x7a]	7426	1			T5	4		T8	96		T9	8
valid_sources[0x7b]	7921	1			T5	7		T11	9		T8	63
valid_sources[0x7c]	8478	1			T5	15		T12	1		T8	97
valid_sources[0x7d]	7424	1			T5	3		T12	2		T8	113
valid_sources[0x7e]	7431	1			T5	8		T4	16		T11	13
valid_sources[0x7f]	8593	1			T2	2		T5	11		T8	72
valid_sources[0x80]	7195	1			T5	5		T4	20		T11	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28469

1

T1

2

T2

1

T3

1

values[0x0]

all_enables

biggest_size

209396

1

T1

18

T3

18

T5

207

values[0x1]

all_enables

biggest_size

28018

1

T1

2

T2

1

T3

4