Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	332770487	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332770487	0	0
T1	8383144	162285	0	0
T2	1734768	42817	0	0
T3	56560	904	0	0
T4	5128928	73966	0	0
T5	234192	9329	0	0
T6	0	13208	0	0
T8	2624272	117039	0	0
T9	26514768	646196	0	0
T10	308448	10069	0	0
T11	123424	4645	0	0
T12	7161224	237458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8383144	8382416	0	0
T2	1734768	1730792	0	0
T3	56560	52192	0	0
T4	5128928	5126632	0	0
T5	234192	230384	0	0
T8	2624272	2616656	0	0
T9	26514768	26510288	0	0
T10	308448	303912	0	0
T11	123424	121016	0	0
T12	7161224	7158760	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8383144	8382416	0	0
T2	1734768	1730792	0	0
T3	56560	52192	0	0
T4	5128928	5126632	0	0
T5	234192	230384	0	0
T8	2624272	2616656	0	0
T9	26514768	26510288	0	0
T10	308448	303912	0	0
T11	123424	121016	0	0
T12	7161224	7158760	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8383144	8382416	0	0
T2	1734768	1730792	0	0
T3	56560	52192	0	0
T4	5128928	5126632	0	0
T5	234192	230384	0	0
T8	2624272	2616656	0	0
T9	26514768	26510288	0	0
T10	308448	303912	0	0
T11	123424	121016	0	0
T12	7161224	7158760	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T8	56	56	0	0
T9	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	120046181	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	120046181	0	0
T1	149699	79642	0	0
T2	30978	18883	0	0
T3	1010	228	0	0
T4	91588	18257	0	0
T5	4182	3647	0	0
T8	46862	45598	0	0
T9	473478	213615	0	0
T10	5508	4996	0	0
T11	2204	1801	0	0
T12	127879	125879	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	87350966	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	87350966	0	0
T1	149699	15888	0	0
T2	30978	7669	0	0
T3	1010	228	0	0
T4	91588	18740	0	0
T5	4182	1894	0	0
T8	46862	25002	0	0
T9	473478	153575	0	0
T10	5508	2549	0	0
T11	2204	948	0	0
T12	127879	55478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1441234	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1441234	0	0
T1	149699	2567	0	0
T2	30978	260	0	0
T3	1010	6	0	0
T4	91588	537	0	0
T5	4182	63	0	0
T8	46862	549	0	0
T9	473478	2879	0	0
T10	5508	43	0	0
T11	2204	34	0	0
T12	127879	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2980742	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2980742	0	0
T1	149699	318	0	0
T2	30978	227	0	0
T3	1010	6	0	0
T4	91588	694	0	0
T5	4182	63	0	0
T8	46862	548	0	0
T9	473478	3471	0	0
T10	5508	43	0	0
T11	2204	34	0	0
T12	127879	1591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1462716	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1462716	0	0
T1	149699	2893	0	0
T2	30978	358	0	0
T3	1010	11	0	0
T4	91588	715	0	0
T5	4182	55	0	0
T8	46862	1281	0	0
T9	473478	5059	0	0
T10	5508	39	0	0
T11	2204	33	0	0
T12	127879	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3054526	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3054526	0	0
T1	149699	124	0	0
T2	30978	301	0	0
T3	1010	11	0	0
T4	91588	794	0	0
T5	4182	55	0	0
T8	46862	1281	0	0
T9	473478	5996	0	0
T10	5508	39	0	0
T11	2204	33	0	0
T12	127879	4291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1451843	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1451843	0	0
T1	149699	1096	0	0
T2	30978	376	0	0
T3	1010	10	0	0
T4	91588	587	0	0
T5	4182	62	0	0
T8	46862	557	0	0
T9	473478	3064	0	0
T10	5508	40	0	0
T11	2204	37	0	0
T12	127879	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3266817	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3266817	0	0
T1	149699	201	0	0
T2	30978	394	0	0
T3	1010	10	0	0
T4	91588	680	0	0
T5	4182	62	0	0
T8	46862	557	0	0
T9	473478	3771	0	0
T10	5508	40	0	0
T11	2204	37	0	0
T12	127879	2758	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1485673	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1485673	0	0
T1	149699	631	0	0
T2	30978	290	0	0
T3	1010	6	0	0
T4	91588	713	0	0
T5	4182	84	0	0
T8	46862	1041	0	0
T9	473478	7704	0	0
T10	5508	50	0	0
T11	2204	31	0	0
T12	127879	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3293638	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3293638	0	0
T1	149699	109	0	0
T2	30978	259	0	0
T3	1010	6	0	0
T4	91588	758	0	0
T5	4182	84	0	0
T8	46862	1041	0	0
T9	473478	7738	0	0
T10	5508	50	0	0
T11	2204	31	0	0
T12	127879	1826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1499516	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1499516	0	0
T1	149699	2196	0	0
T2	30978	395	0	0
T3	1010	12	0	0
T4	91588	666	0	0
T5	4182	75	0	0
T8	46862	1379	0	0
T9	473478	5495	0	0
T10	5508	50	0	0
T11	2204	37	0	0
T12	127879	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2989373	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2989373	0	0
T1	149699	516	0	0
T2	30978	429	0	0
T3	1010	12	0	0
T4	91588	623	0	0
T5	4182	75	0	0
T8	46862	1379	0	0
T9	473478	5620	0	0
T10	5508	50	0	0
T11	2204	37	0	0
T12	127879	1265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1436857	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1436857	0	0
T1	149699	4492	0	0
T2	30978	276	0	0
T3	1010	7	0	0
T4	91588	746	0	0
T5	4182	74	0	0
T8	46862	588	0	0
T9	473478	3053	0	0
T10	5508	55	0	0
T11	2204	33	0	0
T12	127879	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	4352542	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	4352542	0	0
T1	149699	732	0	0
T2	30978	313	0	0
T3	1010	7	0	0
T4	91588	764	0	0
T5	4182	74	0	0
T8	46862	588	0	0
T9	473478	3669	0	0
T10	5508	55	0	0
T11	2204	33	0	0
T12	127879	1111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1415282	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1415282	0	0
T1	149699	2929	0	0
T2	30978	364	0	0
T3	1010	9	0	0
T4	91588	808	0	0
T5	4182	80	0	0
T8	46862	1280	0	0
T9	473478	1582	0	0
T10	5508	50	0	0
T11	2204	24	0	0
T12	127879	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3079219	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3079219	0	0
T1	149699	418	0	0
T2	30978	306	0	0
T3	1010	9	0	0
T4	91588	845	0	0
T5	4182	80	0	0
T8	46862	1280	0	0
T9	473478	1683	0	0
T10	5508	50	0	0
T11	2204	24	0	0
T12	127879	2493	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1451419	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1451419	0	0
T1	149699	1947	0	0
T2	30978	320	0	0
T3	1010	10	0	0
T4	91588	851	0	0
T5	4182	67	0	0
T8	46862	1217	0	0
T9	473478	4538	0	0
T10	5508	44	0	0
T11	2204	42	0	0
T12	127879	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3334043	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3334043	0	0
T1	149699	620	0	0
T2	30978	273	0	0
T3	1010	10	0	0
T4	91588	836	0	0
T5	4182	67	0	0
T8	46862	1217	0	0
T9	473478	5594	0	0
T10	5508	44	0	0
T11	2204	42	0	0
T12	127879	3986	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1443477	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1443477	0	0
T1	149699	3081	0	0
T2	30978	354	0	0
T3	1010	11	0	0
T4	91588	668	0	0
T5	4182	52	0	0
T8	46862	510	0	0
T9	473478	4948	0	0
T10	5508	50	0	0
T11	2204	25	0	0
T12	127879	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3530847	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3530847	0	0
T1	149699	684	0	0
T2	30978	384	0	0
T3	1010	11	0	0
T4	91588	792	0	0
T5	4182	52	0	0
T8	46862	510	0	0
T9	473478	5762	0	0
T10	5508	50	0	0
T11	2204	25	0	0
T12	127879	1661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1399672	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1399672	0	0
T1	149699	2327	0	0
T2	30978	311	0	0
T3	1010	5	0	0
T4	91588	698	0	0
T5	4182	83	0	0
T8	46862	775	0	0
T9	473478	1726	0	0
T10	5508	50	0	0
T11	2204	32	0	0
T12	127879	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3019256	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3019256	0	0
T1	149699	489	0	0
T2	30978	317	0	0
T3	1010	5	0	0
T4	91588	607	0	0
T5	4182	83	0	0
T8	46862	775	0	0
T9	473478	1927	0	0
T10	5508	50	0	0
T11	2204	32	0	0
T12	127879	2984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1407456	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1407456	0	0
T1	149699	1667	0	0
T2	30978	424	0	0
T3	1010	7	0	0
T4	91588	594	0	0
T5	4182	67	0	0
T8	46862	560	0	0
T9	473478	3691	0	0
T10	5508	45	0	0
T11	2204	42	0	0
T12	127879	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3180128	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3180128	0	0
T1	149699	826	0	0
T2	30978	355	0	0
T3	1010	7	0	0
T4	91588	601	0	0
T5	4182	67	0	0
T8	46862	560	0	0
T9	473478	3697	0	0
T10	5508	45	0	0
T11	2204	42	0	0
T12	127879	2357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1488469	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1488469	0	0
T1	149699	2361	0	0
T2	30978	326	0	0
T3	1010	9	0	0
T4	91588	706	0	0
T5	4182	68	0	0
T8	46862	969	0	0
T9	473478	4980	0	0
T10	5508	35	0	0
T11	2204	30	0	0
T12	127879	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3783548	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3783548	0	0
T1	149699	1042	0	0
T2	30978	270	0	0
T3	1010	9	0	0
T4	91588	694	0	0
T5	4182	68	0	0
T8	46862	969	0	0
T9	473478	5207	0	0
T10	5508	35	0	0
T11	2204	30	0	0
T12	127879	3529	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1426688	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1426688	0	0
T1	149699	292	0	0
T2	30978	269	0	0
T3	1010	7	0	0
T4	91588	724	0	0
T5	4182	72	0	0
T8	46862	835	0	0
T9	473478	4931	0	0
T10	5508	43	0	0
T11	2204	37	0	0
T12	127879	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3135834	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3135834	0	0
T1	149699	1	0	0
T2	30978	195	0	0
T3	1010	7	0	0
T4	91588	651	0	0
T5	4182	72	0	0
T8	46862	835	0	0
T9	473478	4947	0	0
T10	5508	43	0	0
T11	2204	37	0	0
T12	127879	3184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1408148	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1408148	0	0
T1	149699	2918	0	0
T2	30978	335	0	0
T3	1010	6	0	0
T4	91588	727	0	0
T5	4182	73	0	0
T8	46862	1023	0	0
T9	473478	1516	0	0
T10	5508	45	0	0
T11	2204	49	0	0
T12	127879	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3171078	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3171078	0	0
T1	149699	2870	0	0
T2	30978	375	0	0
T3	1010	6	0	0
T4	91588	679	0	0
T5	4182	73	0	0
T8	46862	1023	0	0
T9	473478	1520	0	0
T10	5508	45	0	0
T11	2204	49	0	0
T12	127879	1376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1416993	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1416993	0	0
T1	149699	602	0	0
T2	30978	277	0	0
T3	1010	8	0	0
T4	91588	747	0	0
T5	4182	73	0	0
T8	46862	831	0	0
T9	473478	4041	0	0
T10	5508	46	0	0
T11	2204	32	0	0
T12	127879	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2828270	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2828270	0	0
T1	149699	2	0	0
T2	30978	187	0	0
T3	1010	8	0	0
T4	91588	767	0	0
T5	4182	73	0	0
T8	46862	831	0	0
T9	473478	4047	0	0
T10	5508	46	0	0
T11	2204	32	0	0
T12	127879	1741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1442967	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1442967	0	0
T1	149699	1875	0	0
T2	30978	342	0	0
T3	1010	4	0	0
T4	91588	742	0	0
T5	4182	69	0	0
T6	0	8480	0	0
T8	46862	562	0	0
T9	473478	6073	0	0
T10	5508	36	0	0
T11	2204	33	0	0
T12	127879	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2570395	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2570395	0	0
T1	149699	319	0	0
T2	30978	278	0	0
T3	1010	4	0	0
T4	91588	706	0	0
T5	4182	69	0	0
T6	0	4728	0	0
T8	46862	562	0	0
T9	473478	7795	0	0
T10	5508	36	0	0
T11	2204	33	0	0
T12	127879	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1458622	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1458622	0	0
T1	149699	1838	0	0
T2	30978	437	0	0
T3	1010	9	0	0
T4	91588	609	0	0
T5	4182	71	0	0
T8	46862	1076	0	0
T9	473478	1551	0	0
T10	5508	40	0	0
T11	2204	32	0	0
T12	127879	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3693954	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3693954	0	0
T1	149699	820	0	0
T2	30978	406	0	0
T3	1010	9	0	0
T4	91588	558	0	0
T5	4182	71	0	0
T8	46862	1076	0	0
T9	473478	1644	0	0
T10	5508	40	0	0
T11	2204	32	0	0
T12	127879	906	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1467251	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1467251	0	0
T1	149699	2150	0	0
T2	30978	207	0	0
T3	1010	8	0	0
T4	91588	583	0	0
T5	4182	73	0	0
T8	46862	546	0	0
T9	473478	8240	0	0
T10	5508	51	0	0
T11	2204	31	0	0
T12	127879	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2860436	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2860436	0	0
T1	149699	441	0	0
T2	30978	165	0	0
T3	1010	8	0	0
T4	91588	608	0	0
T5	4182	73	0	0
T8	46862	546	0	0
T9	473478	8436	0	0
T10	5508	51	0	0
T11	2204	31	0	0
T12	127879	2762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1428237	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1428237	0	0
T1	149699	1401	0	0
T2	30978	270	0	0
T3	1010	11	0	0
T4	91588	534	0	0
T5	4182	70	0	0
T8	46862	733	0	0
T9	473478	3668	0	0
T10	5508	52	0	0
T11	2204	42	0	0
T12	127879	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2241479	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2241479	0	0
T1	149699	566	0	0
T2	30978	184	0	0
T3	1010	11	0	0
T4	91588	659	0	0
T5	4182	70	0	0
T8	46862	733	0	0
T9	473478	3859	0	0
T10	5508	52	0	0
T11	2204	42	0	0
T12	127879	1209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1379887	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1379887	0	0
T1	149699	1796	0	0
T2	30978	271	0	0
T3	1010	11	0	0
T4	91588	668	0	0
T5	4182	65	0	0
T8	46862	1070	0	0
T9	473478	3376	0	0
T10	5508	53	0	0
T11	2204	45	0	0
T12	127879	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3279818	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3279818	0	0
T1	149699	1007	0	0
T2	30978	225	0	0
T3	1010	11	0	0
T4	91588	653	0	0
T5	4182	65	0	0
T8	46862	1070	0	0
T9	473478	3363	0	0
T10	5508	53	0	0
T11	2204	45	0	0
T12	127879	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1430747	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1430747	0	0
T1	149699	1427	0	0
T2	30978	353	0	0
T3	1010	6	0	0
T4	91588	641	0	0
T5	4182	84	0	0
T8	46862	740	0	0
T9	473478	10368	0	0
T10	5508	57	0	0
T11	2204	35	0	0
T12	127879	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2865184	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2865184	0	0
T1	149699	176	0	0
T2	30978	365	0	0
T3	1010	6	0	0
T4	91588	644	0	0
T5	4182	84	0	0
T8	46862	740	0	0
T9	473478	10581	0	0
T10	5508	57	0	0
T11	2204	35	0	0
T12	127879	2601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1444873	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1444873	0	0
T1	149699	1808	0	0
T2	30978	332	0	0
T3	1010	5	0	0
T4	91588	669	0	0
T5	4182	56	0	0
T8	46862	1028	0	0
T9	473478	6009	0	0
T10	5508	60	0	0
T11	2204	32	0	0
T12	127879	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3136049	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3136049	0	0
T1	149699	1425	0	0
T2	30978	235	0	0
T3	1010	5	0	0
T4	91588	797	0	0
T5	4182	56	0	0
T8	46862	1028	0	0
T9	473478	6056	0	0
T10	5508	60	0	0
T11	2204	32	0	0
T12	127879	1676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1428754	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1428754	0	0
T1	149699	1789	0	0
T2	30978	345	0	0
T3	1010	18	0	0
T4	91588	579	0	0
T5	4182	68	0	0
T8	46862	764	0	0
T9	473478	9444	0	0
T10	5508	44	0	0
T11	2204	36	0	0
T12	127879	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3367198	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3367198	0	0
T1	149699	396	0	0
T2	30978	261	0	0
T3	1010	18	0	0
T4	91588	534	0	0
T5	4182	68	0	0
T8	46862	764	0	0
T9	473478	9617	0	0
T10	5508	44	0	0
T11	2204	36	0	0
T12	127879	1963	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1479642	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1479642	0	0
T1	149699	1410	0	0
T2	30978	256	0	0
T3	1010	8	0	0
T4	91588	691	0	0
T5	4182	85	0	0
T8	46862	967	0	0
T9	473478	7212	0	0
T10	5508	42	0	0
T11	2204	42	0	0
T12	127879	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3363730	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3363730	0	0
T1	149699	676	0	0
T2	30978	240	0	0
T3	1010	8	0	0
T4	91588	699	0	0
T5	4182	85	0	0
T8	46862	967	0	0
T9	473478	7670	0	0
T10	5508	42	0	0
T11	2204	42	0	0
T12	127879	3392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1507400	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1507400	0	0
T1	149699	1222	0	0
T2	30978	257	0	0
T3	1010	3	0	0
T4	91588	671	0	0
T5	4182	58	0	0
T8	46862	1056	0	0
T9	473478	9897	0	0
T10	5508	40	0	0
T11	2204	39	0	0
T12	127879	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	3093292	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	3093292	0	0
T1	149699	176	0	0
T2	30978	215	0	0
T3	1010	3	0	0
T4	91588	724	0	0
T5	4182	58	0	0
T8	46862	1056	0	0
T9	473478	9819	0	0
T10	5508	40	0	0
T11	2204	39	0	0
T12	127879	2739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1437643	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1437643	0	0
T1	149699	481	0	0
T2	30978	266	0	0
T3	1010	12	0	0
T4	91588	724	0	0
T5	4182	67	0	0
T8	46862	524	0	0
T9	473478	6262	0	0
T10	5508	52	0	0
T11	2204	31	0	0
T12	127879	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	2609036	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	2609036	0	0
T1	149699	740	0	0
T2	30978	208	0	0
T3	1010	12	0	0
T4	91588	751	0	0
T5	4182	67	0	0
T8	46862	524	0	0
T9	473478	7292	0	0
T10	5508	52	0	0
T11	2204	31	0	0
T12	127879	313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	1493138	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	1493138	0	0
T1	149699	1671	0	0
T2	30978	325	0	0
T3	1010	5	0	0
T4	91588	645	0	0
T5	4182	80	0	0
T8	46862	759	0	0
T9	473478	3330	0	0
T10	5508	50	0	0
T11	2204	32	0	0
T12	127879	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303313938	4258304	0	0
DepthKnown_A	303313938	303197308	0	0
RvalidKnown_A	303313938	303197308	0	0
WreadyKnown_A	303313938	303197308	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	4258304	0	0
T1	149699	194	0	0
T2	30978	302	0	0
T3	1010	5	0	0
T4	91588	608	0	0
T5	4182	80	0	0
T8	46862	759	0	0
T9	473478	3588	0	0
T10	5508	50	0	0
T11	2204	32	0	0
T12	127879	1759	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303313938	303197308	0	0
T1	149699	149686	0	0
T2	30978	30907	0	0
T3	1010	932	0	0
T4	91588	91547	0	0
T5	4182	4114	0	0
T8	46862	46726	0	0
T9	473478	473398	0	0
T10	5508	5427	0	0
T11	2204	2161	0	0
T12	127879	127835	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0