Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1792871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282235

1

T1

17

T4

344

T2

90

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	703028	1			T1	57		T4	883		T2	209
values[0x0]	669927	1			T1	47		T4	851		T2	208
values[0x1]	702151	1			T1	68		T4	884		T2	201

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1389399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

685707

1

T1

57

T4

846

T2

197

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7489	1			T4	14		T2	2		T14	8
valid_sources[0x01]	7983	1			T4	17		T2	3		T3	1
valid_sources[0x02]	8264	1			T4	8		T2	3		T3	1
valid_sources[0x03]	9366	1			T1	1		T4	4		T2	3
valid_sources[0x04]	7375	1			T1	1		T4	15		T2	5
valid_sources[0x05]	8789	1			T1	2		T4	14		T2	1
valid_sources[0x06]	8257	1			T4	9		T2	4		T3	2
valid_sources[0x07]	7685	1			T4	7		T3	4		T14	8
valid_sources[0x08]	8075	1			T4	5		T2	1		T3	1
valid_sources[0x09]	8751	1			T1	1		T4	10		T2	4
valid_sources[0x0a]	7679	1			T1	1		T4	6		T2	2
valid_sources[0x0b]	7703	1			T1	1		T4	15		T2	2
valid_sources[0x0c]	8600	1			T1	1		T4	8		T2	1
valid_sources[0x0d]	7984	1			T4	9		T16	1		T17	4
valid_sources[0x0e]	7839	1			T4	19		T2	2		T3	4
valid_sources[0x0f]	8624	1			T1	1		T4	8		T2	4
valid_sources[0x10]	8419	1			T1	1		T4	5		T2	3
valid_sources[0x11]	8486	1			T1	2		T4	12		T2	5
valid_sources[0x12]	8403	1			T1	2		T4	9		T2	4
valid_sources[0x13]	8374	1			T1	2		T4	12		T2	4
valid_sources[0x14]	8271	1			T4	12		T2	1		T16	1
valid_sources[0x15]	7956	1			T1	1		T4	17		T2	6
valid_sources[0x16]	8521	1			T4	11		T2	2		T3	4
valid_sources[0x17]	7913	1			T1	2		T4	10		T2	3
valid_sources[0x18]	8217	1			T4	12		T2	3		T3	6
valid_sources[0x19]	8263	1			T4	12		T2	1		T3	2
valid_sources[0x1a]	7659	1			T4	15		T14	9		T19	3
valid_sources[0x1b]	7490	1			T4	9		T2	2		T16	1
valid_sources[0x1c]	7883	1			T4	9		T2	2		T17	1
valid_sources[0x1d]	8697	1			T4	13		T2	2		T3	2
valid_sources[0x1e]	8131	1			T4	7		T2	3		T3	4
valid_sources[0x1f]	7674	1			T1	4		T4	10		T2	4
valid_sources[0x20]	8317	1			T1	2		T4	12		T3	9
valid_sources[0x21]	7695	1			T1	1		T4	12		T2	3
valid_sources[0x22]	8830	1			T4	18		T2	6		T3	1
valid_sources[0x23]	7801	1			T1	3		T4	9		T2	3
valid_sources[0x24]	8101	1			T4	12		T2	1		T3	15
valid_sources[0x25]	8042	1			T1	2		T4	7		T2	3
valid_sources[0x26]	8133	1			T4	13		T2	1		T3	2
valid_sources[0x27]	8023	1			T4	12		T2	6		T3	1
valid_sources[0x28]	8471	1			T4	9		T2	2		T3	2
valid_sources[0x29]	8141	1			T4	14		T2	4		T3	2
valid_sources[0x2a]	8234	1			T4	10		T2	2		T17	3
valid_sources[0x2b]	7726	1			T4	11		T2	1		T3	2
valid_sources[0x2c]	9294	1			T4	10		T2	2		T3	1
valid_sources[0x2d]	7878	1			T4	17		T2	3		T17	1
valid_sources[0x2e]	8066	1			T1	1		T4	13		T2	1
valid_sources[0x2f]	8243	1			T1	1		T4	9		T2	2
valid_sources[0x30]	8279	1			T1	1		T4	11		T2	3
valid_sources[0x31]	7906	1			T1	1		T4	7		T2	3
valid_sources[0x32]	7799	1			T4	9		T2	2		T3	4
valid_sources[0x33]	8447	1			T4	10		T2	2		T14	7
valid_sources[0x34]	7821	1			T1	1		T4	11		T2	5
valid_sources[0x35]	8139	1			T1	2		T4	3		T2	3
valid_sources[0x36]	7630	1			T1	2		T4	20		T2	1
valid_sources[0x37]	8789	1			T4	12		T2	3		T3	2
valid_sources[0x38]	8208	1			T1	1		T4	6		T2	3
valid_sources[0x39]	7815	1			T4	9		T2	5		T17	1
valid_sources[0x3a]	8980	1			T4	8		T2	1		T3	2
valid_sources[0x3b]	7681	1			T1	1		T4	9		T2	2
valid_sources[0x3c]	7769	1			T4	5		T2	3		T16	2
valid_sources[0x3d]	7257	1			T1	2		T4	8		T2	1
valid_sources[0x3e]	8065	1			T4	6		T2	3		T3	2
valid_sources[0x3f]	7693	1			T1	3		T4	10		T14	8
valid_sources[0x40]	8722	1			T4	10		T2	1		T3	1
valid_sources[0x41]	8152	1			T4	15		T2	2		T14	7
valid_sources[0x42]	7989	1			T4	11		T2	1		T14	8
valid_sources[0x43]	7545	1			T1	1		T4	7		T2	4
valid_sources[0x44]	8200	1			T1	1		T4	7		T2	2
valid_sources[0x45]	9774	1			T1	2		T4	4		T2	5
valid_sources[0x46]	7366	1			T1	2		T4	12		T2	3
valid_sources[0x47]	8341	1			T1	1		T4	9		T2	1
valid_sources[0x48]	8809	1			T4	11		T2	2		T17	3
valid_sources[0x49]	7612	1			T4	14		T2	1		T3	2
valid_sources[0x4a]	8633	1			T1	1		T4	13		T2	2
valid_sources[0x4b]	6824	1			T4	11		T2	1		T16	1
valid_sources[0x4c]	9272	1			T4	17		T2	3		T3	3
valid_sources[0x4d]	7851	1			T1	1		T4	11		T2	2
valid_sources[0x4e]	8391	1			T1	1		T4	9		T2	2
valid_sources[0x4f]	8193	1			T4	12		T3	1		T14	8
valid_sources[0x50]	7232	1			T1	1		T4	10		T3	1
valid_sources[0x51]	9600	1			T4	8		T2	1		T3	2
valid_sources[0x52]	7812	1			T4	9		T2	2		T3	2
valid_sources[0x53]	8502	1			T1	1		T4	6		T2	1
valid_sources[0x54]	8884	1			T1	1		T4	15		T2	1
valid_sources[0x55]	8276	1			T4	7		T2	3		T3	2
valid_sources[0x56]	7719	1			T4	15		T2	3		T17	1
valid_sources[0x57]	8076	1			T1	1		T4	14		T2	2
valid_sources[0x58]	8526	1			T4	7		T2	3		T14	8
valid_sources[0x59]	8098	1			T1	2		T4	6		T2	1
valid_sources[0x5a]	7474	1			T1	2		T4	5		T2	1
valid_sources[0x5b]	8109	1			T1	4		T4	17		T2	3
valid_sources[0x5c]	8549	1			T4	7		T2	1		T16	1
valid_sources[0x5d]	7741	1			T4	5		T2	7		T3	1
valid_sources[0x5e]	8152	1			T1	1		T4	7		T2	3
valid_sources[0x5f]	8359	1			T4	13		T2	2		T3	5
valid_sources[0x60]	7822	1			T4	7		T3	4		T17	1
valid_sources[0x61]	7911	1			T1	1		T4	10		T2	5
valid_sources[0x62]	9880	1			T1	1		T4	14		T2	2
valid_sources[0x63]	7914	1			T4	10		T2	3		T16	2
valid_sources[0x64]	7533	1			T1	2		T4	10		T2	3
valid_sources[0x65]	7748	1			T1	1		T4	11		T2	2
valid_sources[0x66]	8666	1			T4	6		T2	2		T3	1
valid_sources[0x67]	8315	1			T4	9		T2	3		T3	1
valid_sources[0x68]	8178	1			T4	8		T2	3		T17	2
valid_sources[0x69]	7965	1			T4	13		T2	4		T16	1
valid_sources[0x6a]	7602	1			T1	2		T4	6		T2	2
valid_sources[0x6b]	8469	1			T4	8		T2	2		T14	8
valid_sources[0x6c]	8715	1			T1	1		T4	6		T2	1
valid_sources[0x6d]	7778	1			T4	12		T2	2		T3	2
valid_sources[0x6e]	8082	1			T4	15		T2	3		T14	9
valid_sources[0x6f]	7556	1			T1	1		T4	14		T2	2
valid_sources[0x70]	7938	1			T1	1		T4	9		T3	1
valid_sources[0x71]	8118	1			T1	1		T4	11		T2	2
valid_sources[0x72]	8386	1			T4	14		T2	5		T14	8
valid_sources[0x73]	8033	1			T1	3		T4	9		T2	4
valid_sources[0x74]	8484	1			T4	8		T2	1		T14	8
valid_sources[0x75]	7968	1			T4	10		T2	7		T3	1
valid_sources[0x76]	8140	1			T1	1		T4	7		T2	2
valid_sources[0x77]	8625	1			T1	1		T4	7		T2	5
valid_sources[0x78]	7858	1			T4	15		T2	5		T14	8
valid_sources[0x79]	7787	1			T4	6		T2	1		T3	3
valid_sources[0x7a]	7124	1			T1	1		T4	12		T2	1
valid_sources[0x7b]	9471	1			T4	6		T2	3		T16	1
valid_sources[0x7c]	7664	1			T4	7		T2	3		T3	1
valid_sources[0x7d]	7968	1			T4	18		T2	1		T14	8
valid_sources[0x7e]	7613	1			T1	1		T4	8		T2	1
valid_sources[0x7f]	9605	1			T4	9		T2	3		T3	3
valid_sources[0x80]	9981	1			T4	13		T16	2		T14	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30111

1

T1

1

T4

29

T2

9

values[0x0]

all_enables

biggest_size

222361

1

T1

14

T4

286

T2

69

values[0x1]

all_enables

biggest_size

29763

1

T1

2

T4

29

T2

12